. MICROPROCESSOR-BASED SOFT VARIABLE STRUCTURE CONTROL FOR

D.C MOTOR SPEED REGULATION

by

JAE RYONG LEE

THESIS submitted to the Faculty of the

Virginia Polytechnic Institute and State University

in partial fulfillment of the requirements for the degree of

MASTER OF SCIENCE

in

ELECTRICAL ENGINEERING

APPROVED:

F. C. Lee, Chairman

C. E. Nunnally

May, 1985

Blacksburg, Virginia

J. G. Tront

MICROPROCESSOR-BASED SOFT VARIABLE STRUCTURE CONTROL FOR

D.C MOTOR SPEED REGULATION

by

JAE RYONG LEE

F. C. Lee, Chairman

ELECTRICAL ENGINEERING

(ABSTRACT)

The theory of soft variable structure control, which

produces robustness to parameter variation and fast transient

response, is discussed in this thesis.

The digital implementation techniques are presented in the

aspects of sample rate, prefilter design, hardware selection,

and microprocessor arithmetic operation.

Simulation and experimental results showed good perform-

ance in negative speed range, but this controller created

unwanted high armature current fluctuation in positive speed

range. The reasons turned out to be the limitation of sample

rate, noise from the tachometer, and high gain at positive

speed.

ACKNOWLEDGEMENTS

I wish to express my gratitude to Dr. Fred C. Lee for

providing the opportunity to investigate and research the

topic discussed in this thesis. The encouragement and sug-

gestions Dr. Lee has provided is greatly appreciated.

I wish to express my appreciation to my committee members,

Dr. C. E. Nunnully and Dr. J. G. Tront for their support.

A special thanks to for providing many

useful advices throughout the research.

With much love and gratitude, I thank my parents for their

constant support of my academic pursuits.

Acknowledgements iii

TABLE OF CONTENTS

CHAPTER 1. INTRODUCTION

1.1 Overview

1.2 Background

1

1

3

CHAPTER 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 4

2.1 Introduction 4

2.2 DC Motor Model

2.3 Theory of Soft Variable Structure Control

CHAPTER 3. DIGITAL CONTROLLER DESIGN

3.1 Introduction ....... .

3.2 Digital Controller Design Technique

3.3 Computer Simulation of Overall System

3.4 Digital Controller Configuration

CHAPTER 4. SOFTWARE IMPLEMENTATION

4.1 System Requirements

4.2 Choice of Arithmetic

4.3 Execution Time

CHAPTER 5. HARDWARE IMPLEMENTATION

5.1 Microprocessor

5.2 Interface Circuitry

Table of Contents

7

12

35

35

36

41

42

46

48

50

53

62

62

65

iv

CHAPTER 6. EVALUATION AND CONCLUSION . . . 74

6.1 Comparison of Analog and Digital Design 74

6.2 Microprocessor Speed 74

6.3 Noise consideration 78

6.4 Gain effect 81

6.5 Conclusion 83

REFERENCES 85

APPENDIX A Simulation Program Listing

APPENDIX B Microprocessor Software Program Listing

VITA

Table of Contents v

CHAPTER 1. INTRODUCTION

1.1 OVERVIEW

This thesis presents a microprocessor-based implementa-

tion of the nonlinear DC motor speed control system. This

nonlinear control, here referred to as "soft variable struc-

ture (SVS) control" was recently proposed by Franke [l].

In motor control, a control with a fast transient response

and robustness, insensitivity to plant parameters, has often

been sought in many applications. This SVS control gives the

fast transient response and the required robustness to pa-

rame't.er changes with the good steady state accuracy. This

controller has recently been applied successfully to DC motor

speed regulation with the analog hardware by Borojevic [2].

In this thesis, the SVS di~ital controller has been imple-

mented with Intel 8751 microprocessor. There are three main

advantages in the digital implementation. First, several

expensive

Secondly,

analog hardware components can be eliminated.

since small number of hardware components are re-

quired simple design can be achieved. Thirdly, interfacing

with other digital control system becomes possible.

chapter 1. INTRODUCTION 1

The sample rate of the motor speed was increased through

several techniques of reducing execution time of software

program. The hardware selection and circuit implementation

techniques are presented in the hardware implementation sec-

tion. Finally, the experimental results are evaluated and

problems of digital controller performance are discussed.

chapter 1. INTRODUCTI~~ 2

1.2 BACKGROUND

In recent years, the nonlinear control theory has often

been applied to controller design to obtain better perform-

ances. For DC motor control, although a linear PI controller

has been used traditionally, it is very difficult to tune the

controller parameters "on-line". Even if they are tuned for

specific disturbances, steady state and dynamic errors can

result when the system is subjected to other disturbances

[ 3 ] .

The method, called sliding mode control [4], belongs to a

wider class of variable structure system, was introduced to

get a system dynamics that is insensitive to parameter

variations. This sliding mode controller implemented in both

analog and digital forms gave very good results. However,

the inherent switching action causes undesired power dissi-

pation in the motor and the power conditioner. The high

frequency switching (chattering) may sometimes excite higher

resonant frequ~ncies in the system. Another approach to mo-

tor control is to use the high gain state feedback [5], but

this may result in low accuracy and poor stability, unless

all states are available for direct measurement and/or the

measurements are noise-free. The soft variable structure

control was introduced to achieve the high gain output feed-

back, without the mentioned difficulties.

chapter 1. INTRODUCTION 3

CHAPTER 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR

2.1 INTRODUCTION

The DC motor is unsurpassed in applications requiring ac-

curate control of speed and/or torque. In spite of their

relatively high cost and maintenance requirements, DC motors

are nearly the universal choice for driving power shovels,

steel and aluminum rolling mills, electric elevators, rail-

road locamotives and large earth-moving equipment. All these

applications require the precise control characteristics in-

herent in DC motors [6].

For the evaluation of the performance of a motor control

system, the accuracy, the speed of response and the sensi-

tivity of the system are usually considered as primary per-

f ormancc indices [ 7] . Several control methods of motor

drives are classified according to accuracy, response and

robustness. The PI control is a conventional method and

widely used in industrial applications. The phase-locked

loop (PLL) control system gives more precise speed accuracy

than that of the PI control system [8]. For the dynamic re-

sponse, however, the speed settling time of a PLL controlled

motor is very long since it is based on integral control. The

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 4

minimum time settling control achieves very fast response

is optimally designed to when the system configuration

achieve the deadbeat response [9]. The minimum-time settling

control system is a very high gain feedback system, and the

performance of this system is sensitive to the deviation of

motor parameters.

The sliding mode control and SVS control, so called, var-

iable structure control was introduced to obtain a robust

control performance to the parameter deviation and/or the

load torque disturbances.

Robustness, in other words, low sensitivity to deviations

in the motor parameters, is a very important index in indus-

trial applications.

The performance of three control methods such as PI con-

trol, sliding mode control and SVS control was compared and

the result was shown in the paper [ 10] . The performance

summary is as follows.

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 5

Table 1. Performance comparison

CHARACTERISTICS PI s·LIDING svs MODE

accuracy excellent good poor

transient response fair good excellent

robustness poor good good

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 6

2.2 DC MOTOR MODEL

A lumped parameter model of armature controlled DC motor

used in this thesis, is schematically shown in Fig 2.1. The

elements shown are defined as follows:

Armature voltage

Armature current

Shaft speed

Armature resistance

Armature inductance

Mechanical damping

Total moment of inertia

Electromechanical constant

Counter EMF

Field current

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 7

T

J D

Fig.2.1 D.C Dotor model

8

The equations describing the model are

di Va= Raia+ L dta + K¢(if)w (2.1)

,where

Then the following linearized model of DC motor is de-

rived from the above equations.

; de /dt 1 10 :dw /dt: = lo I di /di I Io L a J L

0 1

K /J I m I

-R /L I a aJ

,where e is rotor positon and

r e 1

I w I + I I I i I L aJ

0 0 1

: 0 -1/L: I l/L o I L J

is a electromechanical conversion constant.

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OE DC MOTOR 9

Defining mechanical and electrical intrinsic frequencies

as w = D/J and w = R /L , and mechanical and electrical m e a a input gains as am = Km/J and

be rewritten as:

a = K /L , e m a

r d9 /dt 1 r 0 :dw /dt: = : 0 I di /di I I o L a J L

1 -w m -a e

0 a m

-w e

1 r 9 1

I I w I + I I I I I i I

J L a,

r 0 I o I I a L e

0 l

-a I ml o I

j

the equations can

The above DC motor model is reduced for speed control as:

r dw /dt I r -w a 1 I 1 + I I m m I I w I = L di /dt. L -a -w J L i aJ a - e e

r 0 -a 1 r v 1 I a om I I Tai (2.2) L e J L LJ

The motor parameters used in this experiment are listed

in Table.2.1.

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 10

Table 2. Motor parameter values

PARAMETERS UNITS VALUES

rated power w 18.6

rated torque NM 0.00635 I --i

armature resistance OHM 0.85 I armature inductance µH 80 I torque constant NM/A 0.001976

EMF constant Volt 0.001976 sec/rad

Motor Inertia Kg M2 0.000055

tachometer output Volt 1. 03 gradient sec/rad

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 11

2.3 THEORY OF SOFT VARIABLE STRUCTURE CONTROL

This section describes the general concept of SVS control.

The following description is basically originated from

Borojevic's work [11], which is a very good summary for

understanding SVS control.

2.3.l Basic concept

In this section, the general idea of SVS control is de-

scribed. A plant to be controlled can be described with

steady state representation as

x = Ax + Bu , x € Rn , u ~ RP (2.3)

y = Cx

To obtain the SVS control the followig time varying control

is introduced:

u(t) = k w 0 s

r + ky ( t) + l:. p. ( t) N. y ( t)

i=l 1 1 (2.4)

, where the first term provides independent input, the second

term provides classical output feedback, and the third term

introduces variable structure. N. are arbitrary matrices and 1

vector [pi(t)] is to be determined. When equati~n (2.4) is

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 12

substituted into equation (2.3), this new state equation is

obtained

r x = {A + BkC + r p. (t)BN.C}x + Bk w

i=l 1 1 0 s (2.5)

It is expected that in steady state, the system (2.5) returns

to the original system (2.3) with only linear output feed-

back. This can be achieved if

p.(t) = 0, whenever x(t} = 0 l.

(2.6)

From Eq.(2.6) p. has to be a function of the velocity vector l.

• x( t).

vector,

Also, if p. (t) is expressed as a function of state l.

it must be a dynamic function, that is,

pi(t) = f(x,p) (2.7)

Equations (2.4) and (2.7) determine a dynamic behavior of the

new, overall system, Fig.2.2. The new system has the order

of n+r during transient and the order of n in steady state.

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 13

,____ ___ _. ( 1 Is )·I <:;: P ( t ) f(x,p) ~

' '

p(t)

SI f (p,y) I Nonlinear Part

-- - - -- - -- - - -- - - - - - -- - - - - - - - - - - -Linear Part

\/ 11 ( t) ( t) y ( '- ~o ' '[] ,, k x = Ax + Bu

/\ -- ~---- I " - ---

t)

PLANT

w '- k s / 0

Fig.2.2 SVS control system block diagram ·

1 4

Therefore, the variable structure is obtained. General de-

sign goals used to select N. and f(x,p) can be stated as l.

follows.

1. Global asymptotic stability of the overall system should

be secured.

2. The overall system has to have better performance than the

system with output feedback only; in particular,

a) control loop dynamics should be improve~,

b) the system should be robust and bounded in relation to

variation of plant parameters.

c) The control vector u ( t) should be able to have any

values in given permissible range.

For global asymptotic stability of the system described

by equations (2.3),(2.4) and (2.7) , it is sufficient that

f (x,p) -1 = -Q2 [gi(x) + R(x,p)p] (2.8)

provided that the system with p=O is asymptotically stable.

Q2 is any positive definite r X r matrix , R is any positive

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 15

semidefinite r X r matrix for all·x and p, and 9.(x) is a 1

vector with components

i=l,2, ... r (2.9)

The above statement can be proved using the Liapunov func-

tion. The proof is given in the following.

<THEOREM>

x = Ax + Bu n p I x E: R I u ~ R

y = Cx

r u(t) = k 0 ws + ky(t) + ! p.(t)N.y(t) . 1 1 1 1=

p = f (x,p)

(2.10)

(2.11)

( 2. 12)

For global assymptotic stability of the system of the

above equations, it is sufficient

f (x,p) (2.13)

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 16

provided that the system with p=O is asymptotically stable.

Q2 is any positive definite r X r matrix, R2 is any positive

semidefinite r X r matrix for all x and p, and g . ( x ) is a l.

vector with components

= [x(t)-x (t)]TQ1BN.Cx(t) s l. I i=l,2, ... ,r

,where Q1 is a n X n positive definite matrix.

<proof>

Equati~n (2.11) is substituted into equation (2.10)

r x = [A+ BkC + ! p.(t)BN.C]x + Bkows

i=l l. l.

Let

A = A + BkC

, then the steady state solution is

Ys = Cxs

If p=O

(2.14)

(2.15)

(2.16)

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 17

x = Ax + Bk0 ws (2.17)

In order for equation (2.17) to be asymptotic stable, it is

sufficient that from the Liapunov function defined as

follows

-R 1

.

(2.18)

(2.19)

, where Q1 and R1 are positive definite. For the overall

system, introduce nonsingular linear transformation as

fix = and fix = x (2.20)

Substituting equations (2.15),(2.16) and (2.20) into (2.14),

the equivalent description of the overall system is obtained.

r ·fix =Alix + r p.BN.y

i=l 1 1

p = f (x,p)

Define the Liapunov function of the overall system as

(2.21)

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 18

(2.22)

,where Q2 is a positive definite matrix. Then using

equations (2.19),(2.21) and the fact that Q1 and Q2 are sym-

metric matrix,

T T · T r T = ~x (A Q1 + Q1A)~x + 2~x Q1 I p.BN.y + 2p Q2 f i=l 1 1

chapter 2. SOFT'VARIABLE STRUCTURE CONTROL OF DC MOTOR 19

It can be set as

T -p R p 2 (2.23)

Then, since R1 is positive definite, if R2 is positive semi-

definite, v will be negative definite, which is sufficient

condition for global asymptotic stability. From equation

(2.23), it follows

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 20

Since equation (2.23) must be satisfied for all p E. Rr, and

then

or f -1 = -Q 2 (g + R2p)

,which is the same as equation (2.13}.

<Q.E.D>

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 21

2.3.2 Single-input Single-output System

Single input, single output systems for linear system can

be described by

x = Ax + bu (2.24)

y = ex

The control input equation ( 2. 4) now becomes, without the

linear feedback term

r u = k0ws + ! p. (t)bn.y(t) . 1 1 1 1=

(2.25)

In the above equation, all elements are scalers. To get

steady state accuracy,

(2.26)

must hold. Since bn.y must be linearly independent vectors, 1 s

r must be equal to one. Then the control is

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 22

, where n 1 =1 is set, without any loss of generality. Now

condition for global asymptotic stability, equation ( 2. 13)

is

(2.28)

,where Q2 > 0 , r 2 (x,p1 ) > 0 , and Q1 is positive definite.

Obviously r 2 (x,p1 ) is very important because it is the term

that determines intrinsic dynamic behavior of p 1 . If

the parameter p 1 (t) will be only integral function of state

and output vectors. If

(2.30)

the nonlinear control part of the system will have its in-

trinsic dynamics. These two important cases will.be further

examined.

2.3.2.1 Nondynarnic Control

When equation (2.29) holds, equation (2.28) becomes

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OE DC MOTOR 23

(2.31)

,which can be realized with a simple integrator, yielding

(2.32)

In order that equation (2.31) is globally asymptotically

stable around p 1 =O for x=x , the function ' must go through s the origin and lie in the 1 and 3 quadrants in order to

maintain the condition of poi ti ve definite of p 1 . If the

nonlinear feedback, i.e, p 1 , is to be very responsive to de-

viations from the steady state, Q2 should be small. However,

this would cause p 1 to be excessive, should the deviation

from the steady state become large. Therefore, the limits

on p 1 have to be imposed. If Q2 is very small, equations

(2.31) and (2.32) will give the approximate solution

(2.34)

If the system is asymptotically stable, equation (2.34) ac-

tually describes the sliding mode, where

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 24

defines the sliding hypersurface. Equation (2.34) shows that

in real systems, where switching frequency cannot be infi-

nite, the sliding mode either unstable around steady state

if the feedback gain is very large (Q2 very small) or it is

very sluggish when approaching the steady state. However if

r 2 >0, equation (2.34) can be avoided.

2.3.2.2 Dynamic Control

Integrator realization of equation (2.30), together with

limits (2.33) is shown in Fig.2.3.(a). The equivalent real-

ization using feedback is shown in Fig.2.3.(b). This equiv-

alent realization is needed to satisfy the global asymptotic

stability equation (2.28). If the output of the feedback

block is described as

(µ(pl-ml) I P1 ~ ml i

z

= t: (pl-Ml)

I ml < pl < Ml

I P1 ~ Ml

with µ very large, it follows, for

example, for p 1 ~ m1 , that

If the transfer function of the feedback block is set to be

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 25

Fig.2.3.(b) is described by

,which is equivalent to equation (2.28), with

(ll(l-m1/p1 ) I P1 < ml

r2(pl) =)O I ml < P1 < Ml

I

I \µ(l-M1/p1 ) I P1 < Ml

and µ is very large. Normally it is not p 1 that is limited,

but rather input u(t) which is:

m ~ u(t) ~ M , m ~ 0 , M ~ 0 (2.35)

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 26

T - ( x-x ) Q by ' 1

T (x-x5

) Q1by \I .... ,.

....

(a)

m1

I

~ (b)

- - - - n 1

1 Q2 s

M1

t

Fig.2.3 Two realizations of output limiting

>

~

'

p1 ( t) ..... ....

27

Substituting equation (2.25) into (2.35), it follows that for

y(t) > 0

and for y(t) < 0

M-k w 0 s y

m-k w 0 s y

In section 4.1, the equation (2,24) is used to get the limit

of p as

WR S p ~ U(ma~)-WR -w-,where m = o, w = y, k 0 = 1 and WR =

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 28

2.3.3 Soft Variable Structure Controller for DC Motor

In this section, the application of SVS theory to the ar-

mature controlled DC motor controller is presented. This

work has already done by Borojevic in his paper [2]. How-

ever, since this background information is of fundamental

importance toward understanding this thesis, it is reviewed

again in this section. In the Section 2.3.2, it has been

derived that for linear, single-input, single-output globally

asymptotically stable system

x = Ax + bu

y = ex

a SVS control can be achieved by making

u = Y + PY s

(2.36)

,where ys and xs are steady state values, Q2 > 0, Q1 is a

positive definite matrix, and r>O. The block diagram of the

controlled system is shown in Fig.2.4.

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 29

-- -· -·- - ·- - -· - - - -· -- -- -,

I

I I m

I I - - -- ··- - - . ·-· I I I I

-v : _nm-I ~: )I g I ~ - i !t

--· :_

INPUT AMPLIFIER

D.C MOTOR

'vJ 0

Fig.2.4 ModBl of the controlled system (2)

-- --- - - .

sJ+D

- .. I I I

I I I

I

i

! TACHOMETF.R &

FILTER

y ~

In the absence of disturbance, by adjusting the input gain g

to

= (k 2 + R D)/Ck g m a m

the system will have unity steady state gain, i.e,

First in order to avoid the singular point around the zero

speed, all the variables in the model is offset by their

corresponding maximum negative equilibrium values. The state

variables of this "offset" system are

- i am

and the input and output are

y = y - y m

The allowable input range is given by

0 s u s 2v = u m m (2.37)

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 31

In this way the output will be zero only for the maximum

negative speed, which can always be made to be outside of the

speed range necessary for the application.

Secondly since the desired steady state of the armature

current is not known due to the presence of disturbance, the

term (x2 -x2 s.> can not be used in the calculation of the

feedback gain p for SVS control. This problem was solved

through introducing "dummy state variable" equation

(2.38)

, where A. > 0 is an arbitrary parameter. Then the overall

plant can be represented as follows:

x = Ax + bu (2.39)

y = ex

, where from equations ( 2. 38.) and ( 2. 39), the SVS control is

given by

r-D/J A = I _k /L I m

I o L

km/J O 1

-R/L 0 I

0 A I J

r 0 i

b = lg/LI I A I L J

(2.40)

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 32

c = [ c 0 0 1

Now, in order to eliminate the x 2 term in equation (2.36)

,the matrix [Q1bJT should have a form of

[k I 0 k ]T 1 2

From the Liapunov stability condition

-R 1

and equations (2.39), (2.40), the above form of [Q1b]T can

be obtained with these conditions

* ,where X is some large positive constant. From the condi-

* tion X > X , X = ~ can be assumed. Then it is possible to

make x 3 = u from the equation (2.38). Therefore,

p = -Q[{k1 (y-y ) + k 2 (u-y )}y + rp] (2.41) s s .

,where Q = l/Q2 , k 1 = k 11 /c. In order to keep the input to

the plant inside the limits (2.37), the following limiting

inequality is derived.

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 33

um-ys s p s = y

(2. 42)

As a result, the following equations are derived and they are

ready to be used in digital control algorithm.

u = Y + PY s

Ys y < p <

u -y m s y

(2.43)

chapter 2. SOFT VARIABLE STRUCTURE CONTROL OF DC MOTOR 34

CHAPTER 3. DIGITAL CONTROLLER DESIGN

3.1 INTRODUCTION

Before discussing the digital controller design, the

following merits and demerits are considered. The digital

scheme serves to avoid the complexity of the control circuit,

the offset error and the thermal drift which are inherent

problems in the analog scheme.

On the other hand, a demerit of digital system is the

limit of its accuracy. The control inaccuracy is introduced

by the quantization error, which inevitably exists due to the

finite bit length of a logic code.

The A/D converter used in the digital circuit interfacing

with the analog hardware is basically a quantization opera-

ti on which introduces roundoff or truncation error. The -b+l quantization level is determined by a equation: q = 2 (b:

the bit length of a logic code) [12]. Practically, the bit

length of 12 is almost the maximum accuracy in most indus-

trial applications because the LSB of 12-bi ts represents

about SmV when the full range of A/D converter input voltage

is 20V. It is very difficult to protect the circuit from the

noise level of SmV in practical circuit design, especially

with high frequency digital components.

chapter 3. DIGITAL CONTROLLER DESIGN 35

3.2 DIGITAL CONTROLLER DESIGN TECHNIQUE

3.2.1 Sample Rate

There are several things to be considered for digital

system design. First, the sample rate should be properly

selected to ensure a good performance. The selection of the

best sampling rate for a digital system is a compromise among

many factors. Al though the lower sampling rate results in

lower cost, a sampling rate at least twice of the frequency

contained in the unknown signal should be selected so that

the signal can be reconstructed.

The sample rate, therefore, must be at least twice the

required closed-loop bandwidth of the system and possibly as

much as 20 times the system closed-loop bandwidth, depending

on the particular performance requirements of the system and

the relation between the tracking signal and the plant dy-

namics. In this implementation, since the sample rate of 1.4

kHz was used and the measured closed-loop bandwidth was about

50 Hz, the general requirements were fulfilled. However,

this sample rate was not enough for this controller because

it was a nonlinear controll~r with very high gain.

The performance of each sample rate for a nonlinear

controller can be predicted through computer simulation of

the overall system. The sample rate is limited by the

software program execution time of microprocessor. There-

chapter 3. DIGITAL CONTROLLER DESIGN 36

fore, the fast processor and compact program is essential to

obtain high sample rate.

3.2.2 Effect of Prefilter Design

Digital control systems with analog sensors typically in-

elude an analog prefilter between the sensor and the sampler

or A/D converter as an antialiasing device.

Prefilters are usually low pass, and the simplest transfer

function is

G ( s) = a s + a

so that the noise above the prefilter. corner frequency "a"

is attenuated. The design goal is to provide enough atten-

uation at one half the sample rate (w /2) so that the noise s above w /2, when aliased into lower frequencies by the samp-s ler, will not be detrimental to the control system perform-

ance.

A conservative design procedure is to select the corner

frequency and the sample rate sufficiently higher than the

system bandwidth so that the phase lag from the prefi 1 ter

does not significantly alter the system stability.

In this implementation, a simple RC filter was used for

the prefilter and its corner frequency was 160Hz, that is,

a=lOOO rad/sec and its time constant was 1 msec. The

second-order and fourth-order Butterworth filters were tested

chapter 3. DIGITAL CONTROLLER DESIGN 37

with this controller, but the performance turned out to be

worse than the first order filter. This result comes from the

fact that the higher order filter gives more time delay to

the controller.

In addition, the first order RC filter with the corner

frequency of 320Hz, which was twice the original value was

tested. However, it gave almost the same result as the ori-

ginal case. The reason is that al though its time delay is

short it generates more noise to the controller.

chapter 3. DIGITAL CONTROLLER DESIGN 38

3.2.3 Offset Technique

As explained in the previous section, this SVS control

signal should be offset to avoid singularity around zero.

While the offsetting requires more components in the analog

implementation, it does not.in the digital implementation.

It can be accomplished by assigning a digital zero to the

maximum negative speed and a digital maximum value (OFFFH in

this case) to the maximum positive value.

The following table shows the motor speeds, control signal

voltage level, and the corresponding offset digital values.

chapter 3. DIGITAL CONTROLLER DESIGN 39

Table 3. Comparison table for motor speed

[RAD/SEC] [RPM] [VOLT]

240 2000 5.0

120 1000 2.5

I o I o 0.0

-120 -1000 -2.5

-240 -2000 -5.0

chapter 3. DIGITAL CONTROLLER DESIGN

OFFSET DIGITAL VALUE

4096

3072

2048

1024

I o

40

3.3 COMPUTER SIMULATION OF OVERALL SYSTEM

Computer simulation is very important and should precede

implementing new systems, especially nonlinear systems. From

this simulation, most of the important characteristics of the

system can be predicted before the system is actually imple-

mented and experimented. A lot of time and expenses to be

used in experiments can be usually saved through simulation.

A simulation program was written using DC motor model

equation (2.2) ,a prefilter equation

y = cw w/(s + w ) g . g

and the digital controller equations (4.45)-(4.48).(Refer to

Fig.3.1) The parameter values used in this simulation are as

follows: The tachometer gain "c" was chosen as 0.05 since

the tachometer output voltage was set to produce 5 V at the

motor speed of 100 rad/sec. The motor inertia "J" and EMF

constant k come from the motor specification, Table 2. in m

Section 2.2. The armature resistance R , 2.3 n, is the sum a of motor armature resistance (0.85 Q), armature current

sensing resistance ( 1 Q) and current limiting circuit re-

sistance (0.45 Q). TL is a measured value without external

load, and the mechanical damping "D" was approximated as

2.0Xl0- 6 although D was a nonlinear function of speed.

chapter 3. DIGITAL CONTROLLER DESIGN 41

With this program, the system can be simulated with any

sample rate and noise level. For the integration routine,

the fourth order Runge-Kutta method was used and the noise

was simulated by the normal distribution random number gen-

erator.

The simulation results is presented in Chapter 6 and the

commented program listing is given in Appendix A.

3.4 DIGITAL CONTROLLER CONFIGURATION

This digital controller has two inputs, WR (reference

speed) and W (measured motor speed feedback), and one output

U (control signal to motor).

Fig.3.1.

The block diagram is shown in

chapter 3. DIGITAL CONTROLLER DESIGN 42

The detail schematic diagram of the controller is shown

in Fig. 3. 2. For the reference speed· input an 8-bi t A/D

conveter instead of 12-bi t converter was used for this re-

search since it does not affect any system performance.

The description of each component is presented in Chapter

4.

chapter 3. DIGITAL CONTROLLER DESIGN 43

~ ~

WR A/D ~ , .__ __

I I

I

i I

' I I I I

' I I I I I I

I I I I I I I I I I

·I

u (0 -4095)!-{~j +, , ' ~

+ I I I I

' I I

' I I I I I

P•W u I .. ;

I svs 'w ,. .__ EQUATIONS ,, .

I (0 - 4095) I - I I\

I WR I

I I

DIGITAL CONTROLLER

g'-c~r 1 .---=----

----:'>

Tachometer c - Gain

v ·--Prefilter ~.1_

s + w~ I

A/D ~ y

(-10 V - +10 V)

Fig.3.1 Closed loop system with digital controller

~ V'1

12-bit A/D LSB

-0-- SC

' , Analog In)ut (W

MSB

Analog Input (WR)

MSB ..... ,

'RD ~ WR

LSB

8-bit.A/D

...

... ,

.... ,

' I ,

Intel 8155 Intel 8751 PAO ADC ' PO.O P1 • C '

,

PA7 AD~ ' P0.7 ' , PBO

ALE , ALE - P1 • ~ IO/;'." :' +5 v P2. L PB3 P2 .1

P2.0 PB7 P2.2 P2.? -

P3.6(WR) PB4 WR , . PC3 ITT> , PJ.7(RD) PCO CE I]_

-· -

Fig.J.2 Digital controller connection diagram

12-bit D/A

LSB

MBS

0 pu

CHAPTER 4. SOFTWARE IMPLEMENTATION

This chapter describes the software loaded in the 8751

microprocessor. This software performs the SVS control al-

gorithm every 0.7 msec. It is composed of main program, one

interrupt service routine and one multiplication subroutine.

As shown in the flowchart (Fig.4.1), two inputs, motor

speed and reference speed, are sampled through the 8155 port

expander during the interrupt (DINTO) and the result calcu-

lated in the main program is output.

The detail program flow is described in this chapter and

the whole commented program listing is given Appendix B.

chapter 4. SOFTWARE IMPLEMENTATION 46

( START

' INIT: Initialization

1. Set W(k),WR(k) and U(k-1) as 0 speed values (0800H).

2. Set P(k-1)W(k-1) as O. 3. Set timer 0 as 0.7 msec.

Ir

MAIN: Calculation routine for SVS control algorithm (Refer to Fig.4.2)

' I Waiting loop I

DINTO: Interrupt service routine 1. Reload timer 0 as 0.7 msec. 2. Sample the input values

W(k) and WR(k). 3. Output the calculated result.

Fig.4.1 Flowchart for SVS controller program

47

4.1 SYSTEM REQUIREMENTS

As stated in Section 2. 3, the main equations for this

system are as follows:

u = wr + PY

u -w m r w

,where w = y and w = y. r s

(4.44)

The above equations can be converted to the following

difference equations for digital implementation.

U(k) = WR(K) + P(K) * W(K)

P(k) = -Q * [Kl{W(k)-WR(k)} + K2{U(k-l)-WR(k)}] * W(k)

P(k) = P(k-1) + T s * P(k)

chapter 4. SOFTWARE IMPLEMENTATION

(4.45)

(4.46)

(4.47)

48

0 $ U(k).$ U(max) ==> -WR(k) $ P(k)W(k) $ U(max) - WR(k)

(4.48)

,where T is a sampling interval. s The above equations should be implemented as compact as

possible in order to minimize the execution time.

chapter 4. SOFTWARE IMPLEMENTATION 49

4.2 CHOICE OF ARITHMETIC

There are two arithmetics such as floating point arithme-

tic and fixed point arithmetic to implement this type of

control algorithm. Since this system requires 12-bit accu-

racy, 16-bit floating point and 16-bit fixed point arithmetic

were tested to see whether it could satisfy the requirement

of this system.

4.2.1 Floating point arithmetic method

In this system, there are several multiplications, divi-

sions, additions and subtractions and the values of each op-

erator range from small fractional numbers to .large integer

numbers. Therefore, at first, the proper way of implementing

this algorithm can be considered as a floating point arith-

metic.

4.2.1.1 Floating Point Arithmetic Method

The software program wa~ written to implement this algo-

rithm using the 16-bi t floating point arithmetic routines

such as FADD(floating point. addition), FMUL, and FDIV.

These routines for the Intel 8751 assembler were developed

through modifying the existing routines for the Intel 8080

q.ssembler. The 8080 floating point routines were referred

from "The floating point arithmetic routines for an Intel

8080" authored by S.N. Cope.[13]

chapter 4. SOFTWARE IMPLEMENTATION 50

According to his paper, the typical and maximum execution

time for those routines at 5 MHz clock are as follows: (12]

Table 4. Comparison of execution time

ROUTINE TYPICAL MAXIMUM NAME

FADD 0.25msec 0.53msec

FMUL 0.75msec 0.861msec

FDIV 0.75msec 0.845msec

Al though the above routines written in 8751 assembler

takes about one half of the execution time of 8080 assembler

routines due to using 9 MHz clock, the total executon time

of the software program for the SVS control algorithm turned

out to be about 3.5 msec for the maximum execution time case.

With this execution ~ime it is predicted from the simulation

result that the SVS controller can not give good performance.

It was found that these existing routines were only useful

for the ALU of computers or the systems which did not require

short execution time.

4.2.2 Fixed Point Arithmetic

chapter 4. SOFTWARE IMPLEMENTATION 51

The fixed point arithmetic has some advantages over

floating point arithmetic, speed being the principal one.

The main problem of the fixed point arithmetic is an

overflow during the calculation process. Although the final

result of the whole control algorithm is between the minimum

and the maximum value of the binary number (e.g. between -2 16

and 2 16 -1 for 16-bit case ), the intermediate result of some

operation could be larger or smaller than these limits. The

most common way of solving this problem is a scaling method

which means that the intermediate result is divided by two

to the power of some value and the final result is multiplied

by the same value as the value of division. Only the scale

values of 28 or 2 16 were used in this implementation since

the other scaling procedure also takes some time. The fixed

point arithmetic with the scaling method is very useful to

reduce the execution time and to maintain good accuracy of

calculation. Therefore, the fixed point arithmetic with the

scaling was employed in this thesis.

chapter 4. SOFTWARE IMPLEMENTATION 52

4.3 EXECUTION TIME

As stated in the previous section, the execution time of

the software program loaded in the microprocessor should be

minimized to achieve a good performance of controller.

The execution time could be reduced through the following

steps:

Step l; Reduce the number of arithmetic operations.

The equation (4.46) was modified as follow:

P(k) = -Q*Kl[{W(k)-WR(k)} + (K2/Kl){U(k-l)-WR(k)}]*W(k)

Since one constant value can be assigned for Q*Kl or K2/kl

total number of arithmetic operation is reduced.

-6 Step 2; Fix the value of K2/Kl as a power of two.(e.g. 2 )

The multiplication by this value can be performed through

shifting registers by the number of exponent value. It can

eliminate many assembly instructions compared with the normal

multiplication and/or division.

chapter 4. SOFTWARE IMPLEMENTATION 53

Step 3; Scale the DEL(W)[=W(k)-WR(k)] and

DEL(U)[=(K2/Kl)*{U(k-l)-WR(k)}] by the scale factor of 28

Since the K2/Kl is 1/64 in this implementation, the

scaling is needed to maintain the DEL(U) as a integer value

insteady of a fractional value. For this scaling, the above

scale factor is used to reduce some assembly instructions.

As a result, the value of [U(k-1)-WR(k)] is shifted left

twice and then the result is added to the scaled DEL(W) for

addition of DEL(W) and DEL(U) as shown in the flowchart,

Fig .. 4.2.

Step 4; Combine equations (4.46) and (4.47) to obtain one

constant value instead of two multiplications.

The combined equation is

P(k) = P(k-1) + Ts*(-Q*Kl)*[DEL(W) + DEL(U)]*W(k).

Sabsequently, one constant value can be assigned to

Ts*(-Q*Kl), which is 1/2 in this implementation.

Step S; Simplification of equation.

Equation (4.47) is approximated as

P(k)W(k) = P(k-l)W(k-1) + T P(k)W(k) s

chapter 4. SOFTWARE IMPLEMENTATION 54

instead of

P(k)W(k) = P(k-l)W(k) + T P(k)W(k) s

for the limiting inequality (4.48). In order to get the

value P(k-l)*W(k), the value P(k-1) should be calculated and

stored, and then a multiplication is needed. However, if

P(k-l)*W(k-1) is used instead , the value is available from

the previous interval calculation. Since the value of

P(k-l)*W(k-1) is getting closer to the value of P(k-l)*W(k)

when the system response reaches the steady state, the error

from this can be ignored at the steady state.

chapter 4. SOFTWARE IMPLEMENTATION 55

4.4 Program details (Refer to Fig.4.2)

This section describes the detail program flow of "MAIN"

routine. This program used several techniques to minimize

the execution time and to maintain proper accuracy of pro-

gram.

First, the main program calculates 6W and 6U, then 6W and

6U scaled by 2 8 is added together to obtain DEL.

The sign of DEL is checked and changed so that it will be

always a positive number in order to make multiplications

simple. Since the proper value of T*Q*Kl was decided as one

half, W(k) is shifted right once. At this stage, the LSB of

W(k) is lost, but it does not affect anything since the noise

level of the system is much higher. 6P(k) is calculated by

24-bi t X 16-bi t multiplication routine and if the hig}1est

8-bi t is not zero, it goes to a "MAX" or "MIN" routine. If

the 8-bi-: is not zero, tiP(k) is so large or small that it

causes ~~e final result of maximum or minimum. The maximum

or minim".,;...'t\ routine is chosen according to the negation flag

R7. The result of multiplication is ~escaled by 2- 8 by just

ignoring the last 8-bit.

After that, ~P(k)*W(k) is calculated by the same multi-

plicatic:. routine and the overflow is checked. .The result

is divid~1 by 2- 16 in order to compensate the gain effect of

A/D conv:rter, that is, when the signal is converted into

digital ·,·alue, the digital value is multiplied by 409. 6

chapter ~- SOFTWARE IMPLEMENTATION 56

( =4096/10 v) . -16 The total system gain is adjusted by 2 and

the constant value of -T*Q*Kl.

Negation check routine is needed since the negative sign

in -T *Q*Kl was ignored to obtain the positive mul tipli-s cation in the previous step.

The 6P(k)*W(k) is limited by the equation

-WR(k) $ P(k)*W(k) $ Umax - WR(k)

The new P(k)*W(k) is calculated by adding the stored

P(k-l)*W(k-1) and 6P(k)*W(k). The controller output U(k) is

obtained through adding WR ( k) and the new P ( k) *W ( k) . The

U(k) and P(k)*W(k) is stored for the next cycle in the memory

locations UK_lO,UK_ll and PWK_lO,PWK_ll respectively.

chapter 4. SOFTWARE IMPLEMENTATION 57

MAIN:

.:\ W : W ( k ) - WR ( k )

Ll U: U ( k-1 ) - WR ( k)

(k2/k1)L\U * 28 shift left twice

I EO f R1 I

LMJ + DEL: ~W * 28 + (k2/k1)AU * 28

( - )

l Negate DEL & ; set negation : fla R7

p (k): DEL *

MAX YES -

(+)

W(k) * TQK

w (k) * TQK

Divide by 2 8

fiQ l i R1 I

by shifting

RO

x '

I RS Iii RO R1

overflow

YES(+) MIN

1 RO l I R 1

F. 4 2 Flowchart for "MAIN" ig. •

' ' tirIJ I R3 1

R1 I IR3 r

I R4 i LRs_l

I R3 i; • E~ ;

I l" 'sea ing

l RJ

58

I RO I 11fli I R 3 i .6P(k) * W(k) X I R4 I rn:2J

~1 l.B.~J R1 I I R2 I I R4 I ---- ~----- --overflow scaling

MAX MIN

NO

Divide by 216

Rounding

YES

NO

Negate t.P(k)W(k)

P(k)W(k) = P(k-1)W(k-1) + 6P(k)W(k)

NO

U(max) - WR(k)

59 Fig.4.2 Flowchart for "MAIN"

MAX

MIN

P ( k) W ( k) - {u (max) - WR ( k)}

( + )

( -)

P(k)W(k) + WR(k)

( + )

U(k) = WR(k) + P(k)W(k) P(k-1)W(k-1) *= P(k)W(k) u ( k - 1 ) <= = u ( k )

Wiating loop

Fig.4.2 Flowchart for "MAIN"

60

MAX:

MIN:

I U(rnax) - WR(k) I "'

P(k-1)W(k-1) == U(rnax) U(k-1) -- U(rnax) U(k) -- U(max)

'~

Waiting loop

P(k-1)W(k-1) ~= -WR(k) U(k-1) <== 0 u ( k) <== 0

Waiting loop

- WR(k)

Fig.4.2 Flowchart for "MAIN"

61

CHAPTER 5. HARDWARE IMPLEMENTATION

In this chapter, the electrcnic components in the digital

controller are described. The major chips used in this con-

troller are composed of a micrcprocessr (Intel 8751), a port

expander (Intel 8155), a 12-b:t D/A converter, a 12-bit A/D

converter, and a 8-bit A/D con..-erter (Refer to Fig.3.2).

Basically this controller nf:eds two inputs, one for the

reference speed input and the other for the feedback signal

input. They are implemented ~ith 12-bit A/D converter for

the feedback input and 8-bit A/D converter for the reference

input. The 8-bi t A/D converte!" instead of 12-bi t A/D con-

verter was used just for this research purpose. For real

application, the 12-bit A/D cor:"ierter for the reference input

also should be used to adjus-: the reference input to the

whole 12-bit range.

5.1 MICROPROCESSOR

For designing the digital ::peed controller, the micro-

processor should be selected, !irst. In this system the I/O

ports for two 12-bi t inputs c..1.d one 12-bi t output are re-

quired and this controller nee~s fast real time operation in

chapter 5. HARDWARE IMPLEMENTA:ION 62

order to obtain the short sampling interval which guarantees

the good control performance.

In addition, sufficient program memory space is required

to load the complete software program which contains the

complicated nonlinear control algorithm.

To achieve the above requirements, simple circuit, and

low cost implementation, the Intel 8751 microprocessor (so

called one chip microcomputer) was selected for this con-

troller.

The 8751 is an updated version of the Intel 8051 and it

comprises four 8-bit input/output ports,one of which provides

I/O expansion. This processor can be operated at a maximum

12 MHz clock frequency which is more than two times faster

than the popular Intel 8085 processor. In this controller,

a 9 MHz clock was selected for more stable operation with the

other interface circuitry.

Moreover, the Intel 8751 has a 4K byte built-in program

memory space (EPROM) which is large enough to accomodate the

whole program of this system.

The function block diagram of 8751 is shown in Fig. 5 .1.

[ 14].

chapter 5. HARDWARE IMPLEMENTATION 63

°' -I!'--

CLOCK 4K PROGRAM MEMORY

• , I f I

8751 CPU

INTERRUPTS .

- l EXPANSION CONTROL

CONTROL

128 DATA MEMORY

PROGRAMMABLE I/O

COUNTERS l 2 - 16-bit

TIMERS

SERIAL PORT

FUNCTION MULTIPLEXED IN PARALLEL PORTS

OUT

Fig.5.1 Function block diagram of Intel 8751

5.2 'INTERFACE CIRCUITRY

5.2.1 Port Expander (Intel 8155) [15]

The 8155 contains the following functions:

1. A 2k bit static RAM organized as 256 X 8

2. Two 8-bit I/O ports (PA & PB) and one 6-bit I/O port (PC)

3. A 14-bit timer-counter

This chip was used as an port expander in this controller.

In the 8155, there are two registers such as a command

register and a status register so that this chip can be

programed as a port expander or a timer. The IO;M (IO/Memory

select) pin selects either the five registers (command, sta-

tus, PA, PB, PC) or the memory (RAM) portion.

The IO/M pin was connected with +5 V through a resistor

to keep this pin high because only the five registers were

used in this system.

5.2.2 A/D converters

The necessary specifications for A/D converters were also

determined by the control scheme. In this case, since the

system requires fast real time operation ,the conversion time

chapter 5. HARDWARE IMPLEMENTATION 65

of the A/D converters should be fast enough not to reduce the

samlpe rate significantly.

5.2.2.1 12-bit A/D Converter (DATEL-HX12B)

A. Description

It was used for the speed feedback input signal. This

chip !'las many useful built-in functions in one chip. At

first, it has its own internal clock which can be used in the

clock frequencies of 600 KHz, 720 KHz, and 880 KHz depending

on the voltage level of pin 17. And at these clock rate, the

maxim~"Tl conversion time is 20 micro seconds. Secondly, it

has a~ internal buffer amplifier which provides the high in-

put i~pedence. However, this buffer amplifier was not used

since it produced more noise. Thirdly, its parallel output

pins are the TTL compatible so that any other interface chips

are net necessary.

Arncng several input voltage ranges programmable by ex-

terna: pin connection, the -10 to +10 V input range was cho-

sen tc interface with the measured motor speed signal and to

minirn:ze the susceptibility-of noise.

B. Ca:ibration procedure

Th:s A/D converter provides both the complementary offset

binar~ output and the complementary two's complemen"t output

for tr.: unipolar input operation. Since this system requires

chapt~r 5. HARDWARE IMPLEMENTATION 66

offset values, the complemented offset binary output con-

nection was used.

For zero adjustment, the 0 V input was used instead of

-10 V input because the real motor speed zero rather than the

maximum negative speed should be maintained accurately.

Therefore, the trimming potentiometer was adjusted so that

the o~tput code produced 0111 1111 1111 at the input of 0.000

v. Tr.4= full scale adjustment was achieved by adjusting the

gain -:rimming potentiometer so that the output code created

0000 ::QO 0000 at the input voltage of +9.995.

C. C:r=~it diagram

T:.-: circuit .diagram of 12-bi t A/D converter is shown in

Fig.:.2.

cha=~~= 5. HARDWARE IMPLEMENTATION 67

+5V ~-~-------16(+5V POWER 1 7 .

18 19

+5V GND

---15 (DIGITAL COM.) 14(SHOP.T CYCLE) 13 20

(START CONVERT)21 12 1 1 ( COMPAR. INPUT) 22 i--..--... ,

10 (BIPOLAR OFFSET)23 9 24 ANALOG INPUT 8 (20V INPUT)25

+15V

25k

7 261--..-------+-__.,---~~

6 27__.-~,

5 (+15V POWER)28i----...---...... 4 (BUFFER OUT)29

(BUFFER IN)30 3 2 (-15V PO~·::SR) 311---..-----+------+--+--~

1 32

Fig.5.2 Bipolar operation circuit diagram . of 12-bit A/J converter

-15V

68

5.2.2.2 8-bit A/D converter (ZN 447)

A. Description

This A/D converter was used for a voltage input of the

motor reference speed. This chip should be a 12-bi t A/D

converter in order to vary the reference input in the range

of 12-bit resolution.

However, this 8-bit A/D converter was used for this re-

search experiment and the 8-bi t input is converted to a

12-bit data in the software program. It does not matter be-

cause the step change responses of the reference input are

required.

The con·:ersion time of this converter is 9 lJSec and it has

also on-cl::;:: clock which can vary from 1 KHz to 1 MHz de-

pending or. ~he capacitor value connected between pin 3 and

pin 9.

An :;,. tel':'. of importance for a start conversion signal is

that this p"..llse should have a larger pulse width than the

required rr:~imum width, which is 180 nsec.

B. Ca:ibr:~ion procedure

Since ~!:is converter provides the offset binary logic

coding, t!".~ potentiometer was adjusted to obtain 1000 0000

at the ir .. ;:·..:.:. voltage, 0. 000 V, for the off set adjustment.

The gain adjustment was done by adjusting the gain

chapter 5 . .:i..a.RDWARE IMPLEMENTATION 69

potentiometer to obtain 1111 1111 at the input voltage of

4.941 v.

C. Circuit diagram

The circuit diagram of 8-bit converter is shown in

Fig.5.3.

chapter 5. HARDWARE IMPLEMENTATION 70

ANALOG INPUT

I 20~pF 1 (NC) (LSB 18 5K

2 17

3(CLK) 16

13K 4 1 5

-15V 226K 5(V-) 14

6 ( v. ) in 13 7.5K

7(V f IN) 5K 12 re 360 .n..

8(V f OUT) (MSB)11 re 4. 7 µ.

9(GND) 10 13K

Fig.5.3 Bipolar operation circuit diagram of 8-bit A/D converter

DATA

OUT

+5V

71

5.2.3 :2-it D/A Converter (AD 565A)

A. Desc~iption

This 12-bit D/A converter was used for the analog conver-

sion of the digital controller output. This output should

be inte~faced with the amplifier for the control input signal

of the J.C motor.

In ~rder to be consistent with the control input voltage

range, -5 V to +5 V bipolar voltage output configuration was

chosen. The added output amplifier ensures the gain adjust-

ment of the D/A converter.

B. Cal:~ration procedure

Due to the same reason as the A/D converters, the offset

adjust~ent should be performed to obtain 0.000 V output at

the di~:tal output value of 1000 0000 0000.

The gain adjustment was performed to otain 4.9976 V at the

digita: output value of 1111 1111 1111.

C. Cir:~it diagram

The ~ircuit diagram of 12-bit D/A converter is shown in

Fig.5.~.

chapte~ 5. HARDWARE IMPLEMENTATION 72

1K

1 OpF

(-5V - +5V)

1 (NC) 2(NC)

+15V 3(VCC) 4(REF OUT) 5(REF GND) 6(REF IN)

-15V ?(VEE) 8(BIPOLAR OUTPUT) 9(ANALOG OUTPUT)

10(10V SPAN) 1 1 12(GND)

2.4K

-- -

Fig.5.4 Bipolar operation circuit diagram of 12-bit D/A converter

24 23 22 21 20 19 18 DATA IN

17 16 15 14 13

73

CHAPTER 6. EVALUATION AND CONCLUSION

6.1 COMPARISON OF ANALOG AND DIGITAL DESIGN

In analog implementation, since the SVS control algorithm

contains more complicated caculations than the popular PI

control algorithm, the SVS controller requires considerably

more hardware components than the PI controller. However,

in digital implementation, the circuit is simple. It re-

quires only the same number of components as the simplest

digital controller requires, that is, a microprocessor (in-

cluding port expander and memory), two A/D converter (one for

reference input and the other for feedback input), and a D/A

converter for output. As a result, the digital SVS control-

ler design was much simpler than the analog controller de-

sign.

6.2 MICROPROCESSOR SPEED

The speed of Intel microprocessor is more than two times

faster than that of the popular Intel 8085 microprocessor.

Its maximum clock frequency is 12 MHZ, but 9 MHz clock was

used in this implementation beca~se the proper op~ration at

chapter 6. EVALUATION AND CONCLUSION 74

12 MHz was very hard to achieve. With this clock rate, the

minimized software program with proper accuracy of calcu-

lation took about 0.68 msec. Therefore, the sample rate was

chosen as 0.7 msec. Fig.6.1 shows the effect of sample rate

in this system. The higher armature current fluctuation in

a low sample rate results from the fact that the motor speed

changes significantly during the sample interval.

As a result, if the faster microprocessor is used for this

controller, the armature current fluctuation can be obviously

improved. In this case, the faster processor corresponds the

higher clock frequency and/or the 16-bit operation processor.

Fig. 6. 2 shows the expected performance of the faster

processors. The s:mulation result shows that the system with

the high sample rate approaches the analog system.

chapter 6. EVALU~::~N AND CONCLUSION 75

-..._) 0,

1'.1 it11111.•111il -!l.'/'•V

'I' II.'/ 111ti111• ,,

SPEED 0

CURRENT 0

Command = -0.75V T =1.4msec s

SPEED

CURRENT

•"··: 'J-~ '·" 1.S z.r) l.S

,~a : ~.; . p,

.._, f!

~ i

8 ;

8 ... 'o.oo

------~-;:::! .. . o,

.._, f!-

8 a

f! i

f! ., ·~ ..

10.00

CURRENT

SPEED

O.fiO I.DO 1.51) 2.00

CURRENT

SPEED

O.&O 1.00 1.50 z.oo

Noise N(O, 1.1)

2.so ( x1 o2 msec)

Noise N(O, 1.1)

2.m ( x1 o2 r11:.w1•)

Fif.6.1 Effect of sample rate ( experimental and simulation results )

--8 ::s • • . 0... .........

8 _.

~ -8 0

~ i

~ "o.• a.• I.CID ••• Z.CD 2 2·• ( x 1 0 ms e c )

command. = • ',. 75V

noise N(C, ~.1)

T =0.7 msec s

.-8 ....... ~~T"""""---..-~----..-----. ::s• .

II .,a .... m---a.~.--s-.. --.""' . .,---2+.ao--z-r.• ( x 1 O 2 ms~ c )

command =+~.-~V

noise N(O, · .. ~)

T =0.07 msec s

Fig.6.2 Expected ·:~formance of fast pre:~_- ::::ir

77

6.3 NOISE CONSIDERATION

Due to the fact that this system has a very high gain the

small noise produces large variation in the output command

signal of digital controller.

From the experimental results, it was found that the noise

effect on the controller performance mainly comes from the

tachometer and the 12-bi t A/D converter. The noise level

without the tachometer operation was about 10 mV and the

noise level with the tachometer was about 32 mV on the

oscilloscope. The 12-bit A/D converter is more susceptible

to noise than 8-bi t converter because the LSB equivalent

voltage of 8-bi t A/D converter is about 40 mV ( 10 V /256 )

and that of 12-bi t A/D converter is about 5 mV ( 20 V/4096

) . Originally, the veil tage level of 12-bi t A/D converter was

-5 V to +SV which is the same as the 8-bit A/D converter, and

it was changed to -10 V to +10 V to reduce the noise suscep-

tibility.

Originally, the voltage level of 12-bi t A/D was -5 V to

+5 V which was the same as the 8-bi t A/D converter. But it

was changed into -10 V to +10 V input system to reduce the

noise susceptib:lity of 12-bit A/D converter.

The noise level wi~hout the tachometer operation was about

10 mV and the noise level with the tachometer was about 32

mV. In order to get ~he exact noise level of the system, the

chapter 6. EVALUATIOK AND CONCLUSION 78

input data from the 12-bit A/D converter was collected at the

fixed reference input voltage with the open loop system.

With these data, the microprocessor calculated the standard

deviation using the equation as

a = 2 11/2 +e(n) } I

J

,where e(k) is an error of each measured data. From the above

result, the standard deviation of 1.05, which is equivalent

to noise level of 32 mV, was used for computer simulations.

Fig.6.3 shows the effect of noise in the digital controller.

chapter 6. EVALUATION AND CONCLUSION 79

. 0..

'-"B .. II -8 ci

SPEEI'

CURRENT

command =+0.75V noise N(O, 1 .1)

T =0.7 msec s

.---. 8 ~-,_.----,,--------------------­.

8 " ~ -8 ci

8

SPEED

CURRENT

\~.m----o~ .• '-----,~1-----,.~m----2~.m----2~.m(x10 2 msec)

command =+0.75V noise N(O, 0.2)

T =0.7 msec s

Fig.6.3 Effect of noise. 80

6.4 GAIN EFFECT

The SVS control equations

U(k) = WR(k) + P(k)W(k)

P(k)=-QK1 [{W(k)-WR(k)}+K2/K1{U(k-l)-WR(k)}]W(k)

shows that the controller output u(k) has the gain effect of

{W(k) }2 , and the value W(k) is offset so that the negative

maximum speed desig:iates 0 and the positive maximum speed

designates 4095. ~s a result, for the negative speed (0 to

2047) it has low sys~em gain and for the positive speed (2048

to 4095) it has hi~~ system gain. The problem is that this

high gain deteriora~:s the waveforms. It makes the effect

of noise and the i~s~fficient sampling rate more pronounced.

This fact was ver:::ed from the experimental and simulation

results shown in F:~.6.4

chapter 6. EVALUA'!: :~; AND CONCLUSION 81

CX> l\)

Command = -0.75V T = 0.7 msec s

SPEED

CURRENT

Command = +0.75 T = 0.7 msec s

fl l fl, ~ i. I) I . r7 ( 0 ~ S

. •:,~,-.• .. ·~,+,·~'···1~;-~T:T~;;,,,;,: ...... ' ~ '.: ·) !· :~~'.'" ·.~::~: :~: ~.:· ::.,-:1 ,i:~:·~;· -; :~:r:-f:·:·-.J·L: ·. · .. ~~· .< . . ...

'·'.'I .. t • ~ 1.·.-.... ~: .. ' ~ .. : ·'...- . ·~~~- -~\ , . '· ' _:.;. r -: · ;·,~ ') .: .: · -,~ !~ ''.••'""t '~ ~·~f'~'.;-'1¢•;, ~.--.·~~-.J '-~:c- ... ~!.,' :~.; ·/\/·:·

II .;.~ ..... ~f: .. ::.

',,";;._

--11r--r-----,---,.-~­:::l NI . p,.

......, 11--11 L ~ CURRENT a

11 i

8 ti

8

SPF.F~D

Noise N(O, 1.1)

; I f I I I I ::i 0.00 O.liO I.OD l.&O z.oo Z.liO ( X 1 ()' 111:~"1 • )

~11-r-,---~-· . ;i• . ~~~~

p,. --e

H

8

SPEED Noise N(O, 1.1)

et I I I I I I ? 0.00 O.IO 1.00 I.ID z.oo Z.liO ( x1 n 111;······)

Fig.6.4 Effect of gain (experimental and simulation results)

6.5 CONCLUSION

This thesis introduced the digital implementation of the

new control concept. The digital SVS controller regulated

the motor speed as good as the analog implementation in case

of the negative speed. The main problem is that this con-

troller produces significant armature current fluctuation in

the positive speed range. This is a result of the limitation

of the sample rate and the noise generated from the

tachometer. Although there was a current fluctuation prob-

lem, the digital controller could achieve the major charac-

teristics of SVS control such as robustness to parameter

variation and fast transient response.

This thesis has demonstrated the feasibility of SVS con-

trol using digital implementation. The armature current

fluctuation problem san be alleviated by using faster micro-

processor and/or eli~inating noise. Most of the noise comes

from the tachometer which is basically a generator using

brushes. If other s~eed measuring device such as a disk en-

coder is used, the ~oise can be significantly reduced. For

the faster processo::- a 16-bi t microprocessor with maximum

clock frequency of 20 MHz, e.g., F9450 (Fairchild ,product),

is currently availab:e. It is certain that this digital SVS

controller performan~e can be further improved as the speed

of processors is inc::-easing.

chapter 6. EVALUATIC: AND CONCLUSION 83

In addition, the digital hardware cost becomes low and

there is an opportunity to expand system capabilities with

little additional hardware cost. As a result the digital

implementation will provide a more powerful controller at a

competitive cost.

chapter 6. EVALUATI:~: AND CONCLUSION 84

REFERENCES

1. Franke, Von D., Stellgrossenbeschrankungen Strukturvariabler Regelung," No.10, pp. 348-355, 1982.

"Aussch~pfen von Mittels Weicher

Regelungstechnik, Vol.30,

2. Borojevic, Dusan., "Soft Variable Structure Control for DC Motor Speed Regulation," Conference Record of 1984 IAS Annual Meeting, pp. 404-410.

3. Dote, Y., Hoft, R. G., "Microprocessor Based Sliding Mode Controller for D.C Motor Drives," Conference Re-cord of 1980 IAS Annual Meeting, pp. 641-645.

4. Utkin, Vadim I., "Variable Structure Systems with Sliding Modes," IEEE Transactions on Automatic Control, Vol. AC-22, No.2, Apr, 1977.

5. Young, Kar-keung David, "Analysis and Synthesis of High Gain and Vari able Structure Feedback Systems," Ph. D dissertation, EE Dept. of University of Illinois, 1978.

6. McPherson, George., "An Introduction to Electrical Ma-chines and Transformers," John Wiley & Sons, 1981.

7. Harashima, Fumio., Kondo, Seiji., "A design Method for Digital Speed Control System of Motor Drives," Confer-ence Record of 1982 IEEE PESC, pp. 289-297.

8. Harashima, F. et al, "Performance Improvement in Microprocessor-Based Digital PLL Speed Control System," IEEE Transaction, Vol. IECI-28, No.l, pp.56-61 ; Feb, 1981.

9. Harashima, F., Kondo, S., "Microprocessor Based Optimal Speed Control System," IEEE 1981 IECI Procedings.

10. Borojevic, Dusan., "Performance Comparison Structure Controls with PI Control for D.C Regulation," Conference Record of 1984 Meeting, pp.395-403.

of. Variable Motor Speed IAS Annual

11. Borojevic, Dusan., "Study of Variable Structure Control Systems," Independent Study at EE Dept. of VP I & SU. ;Dec, 1982.

References 85

12. Ahmed, Moustafa Elshafei., Belanger, Pierre R., "Limit Cycles in Fixed Point Implementation of Control Algo-rithms," IEEE Transaction, Vol. IE-31, No.3, pp. 235-242 ;Aug, 1984.

13. Cope, S. N., "Floating-Point Ari thmatic Routines and Macros for an Intel 8080 Microprocessor," O.E.U.L. Re-port No. 1123/75.

14. Intel Corp., "r·~CS-51 Family of Single-Chip Microcom-puters User's Manual," 1981.

15. Intel Corp., "MCS-80/85 Family User's Manual," 1979.

References 86

APPENDIX A

SIMULATION PROGRAM LISTING

87

00 00

CONTSP FORTRAN Al 04/29/85 12111 JAElEE

c

IHPllCIT REAl•8 CA-H,O-Z> DIHEHSIOH X(lOl,DXCIO>,CONC3,3) DATA DSEED / 1Z3457.DO /

F 80 204 RECS VA TECH

N • 3 C••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• C THE FOLlOHINO EQUATIONS ASSIGN CONSTANT VALUES TO THE • C SYSTEH·VARIAILES. • C•••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••

c

0 = l.812DO D ,. 2.D-6 FJ• 55.D-6 FKH • 0.02DO R = 2.3DO Fl = 8.D-5 Tl • 0. 0167DO C ,. 0.050DO HO ,. 1000.DO UHAX = 4095.DO X2HAX s 3.6DO CONCl,l> • -D / FJ C••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• C THE FOLlOHINO COEFFICIENTS COHE FROH THE EQUATIONS AS •

C DXCl)/DT = CONCl,l>XCl> + CON(l,2>XC2> + CONCl,3) W C DXC2)/DT ,. CON(Z,llXCl> + CONC2,2)XC2> + CONC2,3) • C DXC3l/DT • CON(3,l)X(l) + CONC3,2>X<2> + CONC3,3) W C ,HHERE XCl>,XCZ), AHD XC3) REPRESENT HOTOR SPEEDCN>, • C ARHATURE CURRENT<IA>, AND TACHOMETER OUTPUT<Y>, W C RESPECTIVELY. w C•••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••

c

~c

c

-:c

CON<l,2> • FKH / FJ CON(l,3> • -TL/FJ CONC2,l> = -FKH / Fl CONC2,2> = -R / Fl CONC3,l) = C • HO CON(3,2) • 0.0 CON(3,3> • -NO

DO 10 I=l,10 X<I> = O.ODO

10 CONTINUE U = 2048.DO PH = O.ODO US • 2048.DO ITIHE • 0 HRITEC6, 1000) READCS,•> HR,IPRINT,THAX,INC,DT,SIO IF <HR .LT. Z048.DO> CONCl,3) • -CONCl,3) H = DT./ FlOATCINC> FDT • -1. • DT / l.D-3 FDT = -1. ODO HR • 1

PRINTED 04/29/85 12•12 PAGE 001

00

'°

CONTSP FORTRAN Al 04,29,15 12•11 JAELEE

c

c

100 CONTINUE TIME • FLOAT<ITIME> I DT IF<TIME .GT.TMAX > 00 TO 500 UC • U' 409.6 - 5.0 IF ( MOO<ITIME,IPRINT> .NE. 0 XX2= X<Z> ' 10.

> 00 TO 200 IF <XXZ .OT. 0.11> IF <XXZ .LT. -0.18) HH2=<H ,4095. - 0.5 HRITE<7,3000) TIME,

XX2 • 0.11 XX2 •-0.11

) • 2. MHZ ,X<Z>

200 CONTINUE DO 300 K = 1, INC

C VA = 0 • UC - X2LIM(X(2),X2MAX> VA • 0 • UC CON<2,3> = VA ' Fl c CALL RUGKUT ( N,DX,H,X,CON

300 CONTINUE c TOY • X<3> + 10.DO CALL OGNML <DSEED,NR,RANDOM> ITOY = SIO•RANOOM+ 204.IDO • TOY + 0.5DO

C ITOY • 204.1 I TOY + 0.5DO H = ITOY c

c

c

CALL CONTRL ( H,U,US,NR,UMAX,PN,FDT TOY = U u = us US = TOY ITIME • ITIME + 1 00 TO 100

500 STOP

F IO

1000 FORMAT<lX,'INSERT NR,IPRINT,TMAX,INC,DT,SIO'> 3000 FORMAT< lX, ElZ.5, ZX, El2.5, 5X, Fl0.3) 4000 FORMAT<l4X, 1 DX =',3FI0.3,' U= 1 ,FI0.3>

END c

204 RECS VA TECH

SUBROUTINE CONTRL ( N,U,US,NR,UMAX,PH,FDT > C••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• C THIS SUBROUTINE HAS THE FUNCTION AS THE DIGITAL 1 C CONTROLLER, HHICH PERFORMS THE SVS CONTROL ALGORITHM. I C THEREFORE, THIS SUBROUTINE IS EQUIVALENT TO THE 1751 I

~C ASSEMLER PROGRAM LOADED IN THE 1751 MICROPROCESSOR. I c11111111111111111111111111111111111111111111111111111111111111111111111

IMPLICIT REAL I I ( 1\-H,O-Z > c

-:c

ND = H - HR UD "' US - WR DP • FDT I ( ND+ U9' 64.DO > I <W•W>,<256.DO•Z56.DO> PW = PH + DP

PRINTED 04,29,15 12112 PAGE 002

'° 0

CONT SP FORTRAN Al 04/29/15 12111 JAELEE F ID 204 RECS

c

c

c

c

UXMHR • UMAX - HR IF ( PH.GT.O.DO .AND. PH.GT.UXMHR ) PH• UXltHR IF ( PH.LT.O.DO .AND. PN.LT.-HR ) PH • -HR IU • HR + PH + 0.5 U = IU IF ( U.LT.O.DO ) U•O. IF< U.GT.4095.DO > U • 4095. RETURN

2000 FORMAT(/lX, 1••• UIS LESS THAN ZERO ••• 1 /lX, 1 U • 1 ,El6.5) END SUBROUTINE XDOT ( N,X,DX,C )

VA TECH

c C••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• C THIS SUBROUTINE COMPUTES DERIVATIVES OF X<I>, X<2>, AND • C X<l> FOR RUNGE-KUTTA INTEGRATION. • C••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• c

c

c

c

IMPLICIT REAL • I ( A-H,O-Z ) DIMENSION X<IO>,DX(l0),C(3,3> M • N-1 DO 10 I=l,N DX<I> = O.l>O DO 10 J = 1, M

10 DXCI> = DXCI> + CCl,J> • XCJ> DXCI> = DXCI> + CCl,3> DXC2> = DXC2> + CC2,3) DXCl> = DX<l> + CC3,3) • XCl> RETURN END SUBROUTINE RUGKUT ( N,FN,H,Y,C ) C••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• C THIS SUBROUTINE PERFORMS FOURTH ORDER RUNGE-KUTTA •

C INTEGRATION. • C••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• c

_c

c c

IMPLICIT REAL • I C A-H,O-Z > DIMENSION FNCIO>,YC10J,CC3,3),SAVEY<IO>,PHIC10) CALL XDOT C N,Y,FN,C DO 10 J = 1, N SAVEYCJ) = YCJ) PHH J > = FNC J >

10 YCJ) = SAVEYCJ> + 0.5DO W H • FNCJ) CALL XDOT C N,Y,FN,C > DO 20 J = I, N PHICJ> = PHICJ) + 2.DO • FNCJ>

PRINTED 04/29/15 12112 PAGE 003

'° ~

CONT SP FORTRAN Al 04/29/15 12111 JAELEE

c c

c c

20 Y(J) • SAVEY<J> + 0.5DO • H • FH<J> CALL XDOT ( H,Y,FN,C > DD 30 J = I, N PHl(J) • PHl(J) + 2.DO • FH<J>

30 Y<J> • SAVEY(J) + H • FH<J> CALL XDOT ( N,Y,FN,C ) DO 40 J • I, N

F IO

40 Y(J) • SAVEY(J) + (H/6,DO) • ( PHl(J) + FN(J) ) c

RETURN END c

204 RECS VA TECH

FUNCTION X2LIH ( A,Al ) C••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• C THIS FUNCTION ACTS AS A CURRENT LIHITERS. • C••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• c

c

c

c

-.

IHPLICIT REAL • a ( A-H,O-Z > DATA AHi I l.D4 I

IF (A .LT. -Al ) 00 TO 10 IF ( A .GT. Al >GO TO 20 X2LIH = D. DO RETURN

10 X2LIH = AHi • ( A + Al HRITE(7,1000) A,X2LIH RETURN

20 X2LIH = AHi • ( A - Al HRITE(7,2DOO> A,X2l:H RETURN

1000 FORHAT<tIX,•--- NEGATIVE CLIP IA•',FI0.3, 1 X2LIH• 1 ,El6.5,' ---'> 2000 FORHAT<tIX,•+++ POSITIVE CLIP IA•',FI0.3,' X2LIH= 1 ,El6.5,' +++')

END

PRINTED 04/29115 12•12 PAOE 004

APPENDIX E

MICROPROCESSOR SOFTWARE PROGRAM LISTING

92

'° \.>.)

INTO LST Al 04/23/85 0111 JAELEE v 120 654 RECS VA TECH PRINTED 05/09/85 15157

1 MCS-51 MACRO ASSEMBLER INTO,

ISIS-II MCS-51 MACRO ASSEMBLER V2.0 OBJECT MODULE PLACED IN 1Fl1INTG.OIJ ASSEMBLER INVOKED IY1 ASM51 1Fl11NTG.A51 DI XR PLC42)

LDC OBJ LINE l 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 l8 19 20 21 22 23 24

0025 25 OOZ6 Z6 OOZ7 Z1 OOZ8 Z8 OOZI Z9 ooze 30 OOZD 31 OOZE 32

1 ~HCS-51 MACRO ASSEMBLER

LDC OBJ LINE 0036 33 0037 34 003& 35 - 0039 36

SOURCE

•••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• I 1 SOFT VARIABLE STRUCTURE CONTROL PROGRAM I ·-------------------------------------------------------------------------' IY JAE RYONO LEE I LAST REVISED ON MARCH 29, 1985 ·-------------------------------------------------------------------------' THIS PROGRAM IS USED FOR DIGITAL SOFT VARIABLE STRUCTURE CONTROLLER I FOR DC MOTOR SPEED REGULATION. THE EQUATIONS USED IN THIS PROGRAM I AS FOLLOHS1 I 1 U<K> = HR<K> + PCK>H<K> I P<K> = -Q2 • Kl 1 C <H<K>-HR<K>J + <KZ/Kl)(UCK-1>-HR<K>J l • H<K> I P<K>H<K> = P<K-l>H<K-1> + TCSAMPLE>P<K>H<K> 1 -HR<K> < P<K>H<K> < UCMAX) - HR(K) I ,WHERE 1 U<K> 1 OUTPUT OF CONTROLLER I H<K> 1 MEASURED MOTOR SPEED I WR<K> 1 REFERENCE SPEED I P<K> 1 FEEDBACK GAIN I UCMAX> 1 MAXIMUM OUTPUT VALUE , ........................................................................ . ' HKO EQU 25H 1HIGHER BYTE OF W(K)

HKl EQU 26H 1LOHER BYTE OF W<K> HRKO EQU 27H 1HIGHER IYTE OF HR<K> WRKl EQU Z8H 1LOHER BYTE OF HR<K> UK_lO EQU ZIH 1HIGHER BYTE OF U(K-1> UK_ll EQU 2CH 1LOHER BYTE OF UCK-1> UKO EQU 2DH 1HIGHER BYTE OF U<K> UKl EQU ~EH 1LOHER BYTE OF U<K>

INTO

SOURCE

~ri~:l~ EQU 36H 1P<K-l >•H<K-1> EQU 37H

PHKO EQU 38H 1P<K>•W<K> PHKl EQU 39H

PAGE 001

PAGE l

PAGE z

'° """"

INTO LST Al 04,23,15 0111 JAELEE v 120 654 RECS VA TECH PRINTED 05,09,15 15157 PAGE 002

0000 l

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

MCS-51 MACRO ASSEMBLER

LOC OBJ

0000 02oon

0009 OOOB 758AOC OOOE 758CFE OOll 0140 0040 0040 D2Al

"':0042 C2Al

LINE 70 71 12 73 14 75 76 11 78 79 80 81 82 83 84

, ............................................................................. . 1 1,0 PORT PIH ASSIGNMENT FOR COMMUNICATION WITH A'D CONVERTERS ·------------------------------------------------------------------------------' P2.0=0 1 START CONVERSION FOR MOTOR SPEED REFERENCE IHPUT<8-BIT A'D> 1 P2.l=l 1 START CONVERSION FOR MEASURED MOTOR SPEED INPUT<l2-81T A/D) 1 P2.2=0 1 READ ENABLE FOR MOTOR SPEED REFERENCE INPUT<8-BIT A/D) , ............................................................................. . I ·------------------------------------------------------------------------------' MACRO PROGRAM FOR NEGATION OF 16 BIT SIGNED NUMBER ·------------------------------------------------------------------------------' I ·--------------------------------------------------------------------------' MACRO PROGRAM FDR SHIFT LEFT OF 16 BIT NUMBER ·--------------------------------------------------------------------------' I ·------------------------------------------------------------------------------' MACRO PROGRAM FOR 16 BIT ADDITION ·------------------------------------------------------------------------------' I ·------------------------------------------------------------------------------' MACRO PROGRAM FOR 16 BIT SUBTRACTION ·------------------------------------------------------------------------------' ORO OOOOH

INTO

SOURCE LJMP INIT 1GO TO INITIALIZATION ROUTINE.

I , ........................................................................... . I INTERRUPT SERVICE ROUTINE I 1 DURING INTERRUPT, THIS PROGRAM RELOADS THE TIMER, OBTAINS THO INPUTS 1 HCK> AND NRCK>, AND OUTPUTS THE CALCULATED RESULT. 1••·········································································· ORO OOOBH 1INTERRUPT 0 SERVICE ROUTINE DINT01 MDV TLO,IOCH 1RELOAD THE TIMER 0 AS 0.7 MSEC.

HOV THO,IOFEH 1sno IN 9 MHZ CLK = 01F4H => OOOO-OlF4H • FEOCH AJHP SAMPLE ORO 0040H

SAHPLE1 SETB P2.1 1START CONVERSION FOR 12-BIT A'D CONVERTER CLR P2.1 1POSITIVE GOING PULSE

PAGE 3

'° \J'l

INTO LST Al 04/23/15 0111 JAELEE v 120

0044 C2AO 0046 D2AO 0048 A4 0049 A4 004A A4 004B A4 004C 7400 004E 7800 0050 F2 0051 7801 0053 E2 0054 F4 0055 F526 0057 C2A2 0059 7802 005B E2 005C F4 0050 540F 005F F525 0061 E2 0062 54FO 0064 C4 l

85 86 87 aa 89 90 91 92 93 94 95 96 97 911 99

100 101 102 103 104 105 106

HCS-51 MACRO ASSEMBLER

LOC OBJ 0065 F527 0067 7803 0069 E2 006A 540F 006C C4 0060 F528 006F D2A2 0071 E52D 0073 C4 0074 54FO 0076 4405 0078 F5AO 007A 852E90 007D 752100 0080 752201 0083 C02l 0085 C022

-0087 75A88A 008A 32 0088 752B08 008E 7 52COO 0091 753600 0094 753700 0097 7 52508 009A 752600

"':0090 752708

LINE 107 1011 109 110 111 112 113 114 115 116 117 1111 119 120 121 122 123 124 125 126 127 1211 129 130 131 132

INTO

SOURCE

IHIT1

CLR P2.0 SETB P2.0 HUL AB MUL Al HUL AB HUL AB HOV A,10 HOV RO, IO HOVXRO,A HOV RO,IOlH HOVX ARO CPL A HOV WKl,A CLR P2.2 HOV R0,102H HOVX ARO CPL A AllL A,IOFH HOV WKO,A HOVX ARO AllL A,IOFOH SWAP A

HOV HRKO,A HOV RD,103H HOVX ARO ANL A,IOFH SHAP A HOV HRKl,A SETB PZ.2 HOV A,UKO SHAP A ANL A,IOFOH ORL A,105H HOV P2,A HOV Pl, UKl HOV 21H,IO HOV 22H,ID1H PUSH 21H PUSH 22H HOV IE, lllAH RETI HOV UK 10, I08H HOV UK-11, IO HOV PHK_lO, IO HOV PHK 11, IO HOV HK0:-to11H HOV HKl. 10 HOV WRKO,IOllH

654 RECS VA TECH PRINTED 05/09/85 15157

1 START COtlVERSION FOR 8-BIT A/D CONVERTER 1NEGATIVE GOING PULSE 1DUHHY INSTRUCTIONS FOR WAITING FOR 1 A/D CONVERSION

1LOAD ACC AS 0000 0000 1ADDRESS OF INTERNAL COMMAND REGISTER OF 8155

1PORT A,B,C ARE USED AS AN INPUT PORT 1SELECT PORT A AS AN INPUT PORT

1HOVE THE CONTENTS OF PORT A TO ACC

' 1ENABLE READ FOR REFERENCE INPUT 1SELECT PORT B AS AN INPUT PORT

1HOVE THE CONTENTS OF PORT B TO ACC 1HASK OUT HIGH HIBBLE

1GET DATA FROM THE INPUT PORT I 1HASK OUT THE LOH NIBBLE

l 1SELECT PORT 3 AS AN INPUT PORT

1HOVE THE CONTENTS OF PORT C TO ACC 1HASK OUT HIGH NIBBLE

1DISABLE READ OF REFERENCE INPUT A/D CONVERTER 10UTPUT THE CALCULATED RESULT

1END OF OUTPUT 1SET UP THE ADDRESS TO RETURN FROM 1 INTERRUPT

1ENABLE INTERRUPT 1INITIALIZE THE PREVIOUS OUTPUT AS 0 SPEED I UCK-l>=5V 1INITIALIZE THE FEEDBACK GAIN AS 0 I PCK-l>WCK-1>=0 1INITIALIZE THE INPUT AS 0 SPEED=5V 1INITIALIZE THE REFERENCE INPUT AS 0 SPEED

PAGE OOS

PAGE 4

'° CJ'

INTO LST

OOAO 752800 OOA3 7 58911 OOA6 758802 OOA9 75ASSA OOAC 75SAOC OOAF 75SCFE 0082 D2SC 0084 2104 0100 0100 D022 0102 D021 l

Al 04/23/85 0111 JAELEE v 120 6511 RECS VA TECH PRINTED 05/09/15 15157

133 134 135 136 137 138 139 140 141 142 143

START•

HOV WRKl, IO HOV THOD,1000100011 HOV JP,102H HOV IE,1100010101 HOV TLO, IOCH MDV THO,IOFEH SETI TRO AJMP MAIN ORO DlOOH PDP 22H POP 21H

1SET THE TIMER MODE 1SET THE INTERRUPT PRIORITY 1ENAILE THE INTERRUPT

1LDAD THE TIMER 0 AS 0.7 MSEC 1RUN TIMER 0 100 TO MAIN PROGRAM.

MCS-51 MACRO ASSEMBLER INTO

LOC OBJ 0104 7FOO 0106 AA27 0108 AB2S OlOA C3 0108 E526 OlOD 9B OlOE F9 OlOF E525 0111 9A 0112 FS 0113 E52C 0115 C3 0116 98 0117 Fii 0118 E52B OllA 9A 0118 FA

01 lC EB 011 D C3 OllE 33 OllF FD 0120 EA

-0121 33 0122 FA 0123 EB 0124 C3 0125 33 0126 FD 0127 EA

-:012a 33

LINE 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 +2 167 +3 168 +2 169 +2 170 +3 171 +3 172 +2 173 +3 174 +2 175 +3 176 +2 177 +2 178 +3 179 +3 no +2

SOURCE MAIN• HOV R7,IO

HOV R2,HRKO HOV R3,HRK1 CLR C MOV A,HKl sun A,R3 MOV RI.A HOV A,HKO SUBI A,R2 HOV RO,A MOV A,UK_ll CLR C SUBI A,R3 MOV R3,A HOV A,UK_lO SUBI A,R2

1CLEAR THE NEGATION FLAG 1H<K>-HR<K>

1END OF SUBTRACTION, DEL<H> IN RO,Rl 1U<K-l>-HR<K>

MOV R2,A 1DEL<U> IN R2,R3 1-------------------------------------------------------------------------, SHIFT DEL<U> LEFT TWICE TO GET THE SCALED <BY 256> VAULE 1 THEN THE RESULT IN R2,R3 IS <K2/Kl)(U<K-1>-WR<K>)•256 1 BECAUSE K2/Kl = l/64 ·-------------------------------------------------------------------------

HOV A,R3 CLR c RLC A HOV R3,A MDV A,R2 RLC A HOV R2,A HOV A,R3 CLR c RLC A MOV R3,A HOV A,R2 RLC A

PAGE 004

PAGE 5

INTO LST Al 04/2.S/15 Doll JAELEE v 120 654 RECS VA TECH PRINTED 05/09/15 15157 PAGE 005

1 MCS-51 MACRO ASSEMBLER INTO PAGE 6

LOC OIJ LINE SOURCE 0129 FA Ill +3 HOV R2,A

112 +2 012A 20E709 113 JI ACC.7,CADD2 1JF DEL(U) JS NEGATIVE, 0120 E9 114 CADDlo HOV A,Rl 1DEL(U) IS POSITIVE 012E 2A 115 ADO A,R2 Ol2F F9 116 MDV Rl,A 0130 ES 117 MDV A,RO 0131 3400 111 ADDC A, 10 0133 Fl 119 MDV RO,A 0134 2130 190 AJMP CADD3 0136 E9 191 CADD2o HOV A,Rl 1DEL<H>•256+DELCU>•256 0137 2A 192 ADD A,R2 1DEL(U) IS NEGATIVE CASE 0131 F9 193 MDV RI.A 0139 Ea 194 MDV A,RO 0 l 3A 34FF 195 ADDC A,IOFFH 013C Fl 196 MDV RO.A 013D 30E715 197 CADD3o JllB ACC.7,CADD4 1IF DEL(Hl+DEL(U) IS POSITIVE 0140 El 191 HOV A,RO 1NEGATJON OF DEL IN RO,Rl,R3 0141 F4 199 CPL A 0142 Fl 200 HOV RO,A 0143 E9 201 HOV A,Rl 0144 F4 202 CPL A 0145 F9 203 MDV Rl.A 0146 EB 204 HOV A,R3 0147 F4 205 CPL A Ol4B 2401 206 ADD A,11 Ol4A FB 207 HOV R3,A 014B E9 201 MDV A,Rl 014C 3400· 209 ADDC A, IO Ol4E F9 210 HOV Rl,A 014F El 211 HOV A,RO 0150 3400 212 ADDC A, 10 0152 Fl 213 HOV RO,A 0153 7F01 214 HOV R7, 11 1NEGATJON FLAG 0155 E525 215 CADD41 HOV A,HKO 1DIVIDE H<K> BY 2 USING 0157 C3 216 CLR c I SHIFTING 0151 13 217 RRC A 1

~HCS-51 MACRO ASSEMBLER INTO PAGE 7

'° LOC OBJ LINE SOURCE

-.J 0159 FC 211 HOV R4,A Ol5A E526 219 HOV A,HKl Ol 5C 13 220 NRC A

-:01so FD 221 HOV RS,A 1H HITH GAIN IN R4,RS

'° 00

INTG LST Al 04/23/15 0111 JAELEE v 120

OISE 12D26E Dl6 l 3DDOD7 0164 EF Dl65 20ED54 0161 D20229 0161 AC25 0160 A026 016F 12D26E 0172 30D007 0175 Ef 0176 20E043 0179 02D229 Ol7C E8 0170 3DE701 0110 EB 0111 EF 0112 2DE037 Dll5 D20229 Dlll EB Dl89 3DE7ll DllC E9 0180 2401 Dl8F F9 0190 E8 0191 3400 0193 3D0207 0196 EF Dl97 20E022 019A 02D229 0190 EF 019E 2DEOOA OlAl E9 DIAZ F4 I

222 223 224 225 226 227 221 229 230 231 232 233 234 235 236 237 231 239 240 241 242 243 244 245 246 247 248 249 25D 251 252 253 254

MCS-51 MACRO ASSEMBLER

LDC OBJ LINE OlA3 2401 . 255 01A5 F9 256 OlA6 El 257 OlA7 F4 251 OIAI 3400 259 OlAA F8 260

-DIAB AA36 261 OlAD AB37 262 OlAF E9 263 0180 21 264 01 Bl F9 265 0182 FO 266 0183 El 267 0184 3A 261 -:ous 3D0207 269

OK11

OK21

OK31

OK41

INTO

SOURCE

OK51 BAOlh

LCALL CHUL JNB 32.0,0Kl MDV A,R7 JB ACC.O,AHAX LJHP HIN HOV R4,WKO MDV RS,HKl LCALL CMUL JllB 32.0,0K2 HOV A,R7 Jll ACC.O,AHAX LJHP HIN MDV A,RO JllB ACC.7,0K3 MDV A,R3 MDV A,R7 Jll ACC.O,AHAX lJHP HIN HOV A,R3 Jllll ACC.7,0K4 HOV A,Rl ADD A, II HOV RI ,A HOV A,RO ADDC A, ID Jllll PSW.2,0K4 MDV A,R7 JB ACC.O,AMAX LJHP MIN HOV A,R7 JB ACC.O,OKS HOV A,Rl CPL A

AOD A, II HOV Rl,A HOV A,RD CPL A ADDC A,10 HOV RO,A HOV R2,PW!C_l0 HOV R3,PWK_ll HOV A,Rl AOD A,R3 HOV Rl,A HOV R5,A HOV A,RO ADDC A,R2 JllB PSW.2,CllAOl

654 RECS VA TECH

iOEL•CW•TQK>=OEL<P> iIF HOT OVERFLOW,

10EL<P>•W

10VERFLOW CHECK FOR RO

1ROUNOINO

PRINTED 05/09/15 15157

1CHECK NEGATION COUNTER illEGATE THE -OELCP>•W

1P<K>WCK>=P<K-l>+T•POOTCK>•WCK> 1POW IS STORED IN RO,Rl ANO PWCK-1> IS STORED I IN R2,R3.

1STORE THE RESULT OF LOWER BYTE ADDITION IN R5.

1If HO OVERFLOW OCCURS, GO TO.CBAOl.

PAOE 006

PAGE I

'° '°

IllTG LST Al 04/21.185 01 ll JAELEE v 120 654 RECS VA TECH PRINTED 05.t09.tl5 15157 PAGE 007

0188 EA 270 0189 20E719 271 OlBC 02024C 272 AHAX1 OIBF Fl 271 CIADl I OlCO FC 274 OlCl lDE714 275

276 +l 01C4 OF 277 +l 01C5 Cl 271 +l 01C6 E9 279 +2 01C7 F4 210 +l OlCI 2401 281 +1 OlCA F9 212 +2 OlCll El 213 +2 OlCC F4 214 +l OlCD 3400 215 +l OlCF Fl 216 +2

217 +l 0100 El 211 DIDI 54FO 219 OlDl 600A 290 01D5 020229 291 AMIN• l HCS-51 HACRO ASSEMBLER INTO

LDC OBJ LINE SOURCE DIDI 54FO 292 CllAD21 OlDA 6001 29l OlDC 02024C 294 01 DF IC38 295 CllADl1 OlEl 8D39 296 OlEl 710F 297 01E5 79FF 291 OlE7 AA27 299 01E9 All21 lOO

lOl +l OlEll Cl 102 +l OlEC E9 lDl +l OlED 911 l04 +1 OlfE F9 105 +1 OlEF El 106 +l OlFO 9A 107 +l -Olfl Fl lOI +1

109 +l 01F2 El llO OlFl FA 311 01F4 E9 112 01F5 Fii lll OIF6 Alla ll4 OlFI A9l9 115

316 +l -:01FA Cl 317 +l

HOV A,R2 1IF OVERFLOH OCCURS AND ONE OPERAND IS NEGATIVE, Jll ACC.7,AHIN ' GO TO HIN. IF ONE OPERAND IS POSITIVE, GO TO LJHP HAX ' HAX. HOV RO,A HOV R4,A 1STORE THE RESULT OF HIGHER llYTE ADDITION IN R4. JNll ACC. 7, CIAD2 1IF THE RESULT IS POSITIVE, GO TO CllAD2 IllC R7 CLR c HOV A,Rl CPL A ADD A,IOlH HOV RI.A HOV A,RO CPL A ADDC A,10 HOV RO,A HOV A,RO ANL A,IOFOH JZ CIADl LJHP HIN

ANL A,IOFOH JZ CllADl LJHP MAX HOV PWKO,R4 HOV PWK1.R5 HOV RO,IOFH HOV Rl,IOFFH HOV R2,WRKO HOV R3,WRK1 CLR C HOV A,Rl SUllll A,Rl HOV Rl,A HOV A,RO SUllll A, R2 HOV RO,A HOV A,RO HOV R2,A HOV A,Rl HOV Rl,A HOV RO,PHKO HOV Rl,PHKl CLR C

1THO'S COMP. OF LOH llYTE

1STORE IT 1THO'S COMP. OF HIGH llYTE

1STORE IT 1CHECK SIGNED ll lllT OVERFLOH 1IF THE RESULT OF AND LOGIC IS O, IT IS NOT

' NOT OVERFLOH. IF NOT, IT IS NEGATIVE OVERFLOH.

1CHECK SIGHED 13 lllT OVERFLOH FOR POSITIVE CASE.

1THE RESULT OF PH<K-l>+PDH IS STORED IN PHKO,PHKl 1U<MAX> IS STORED IN RO,Rl. 1HR<K> IS STORED IN R2,Rl.

1SUllTRACT LOH BYTES 1STORE IT 1SUBTRACT HIGH BYTES 1STORE IT

1U<HAX>-WR<K> 1HOVE THE RESULT OF SUBTRACTION IN RZ,Rl.

1STORE THE PH<K> IN RO,Rl.

PAGE 9

lllTO LST Al 04/23/15 0111 JAELEE v 120 654 RECS VA TECH PRINTED 05/09/15 15157 PAOE 001

OlFll E9 311 +l 110V A,Rl 1SUBTRACT LOH BYTES OlFC 911 319 +l sun A.R3 OlFD F9 320 +l 110V RI.A 1STORE IT OlFE El 321 +l HOV A,RO 1SUBTRACT HIGH BYTES OlFF 9A 322 +l sun A,R2 0200 Fl 323 +l 110V RO,A 1STORE IT

324 +l 1PH-(UCHAX>-HRCK>> 0201 20E702 325 JI ACC.7,PR04 1IF THE RESULT IS MINUS, IT IS PROPER VALUE. 0204 414C 326 AJHP 11AX 1IF THE RESULT IS PLUS, GO TO MAX 0206 Al31 327 PR041 HOV RO,PHKO 1LOAD RO,Rl MITH PHCK>. 0201 A939 321 HOV Rl,PHKl

l MCS-51 11ACRO ASSEMBLER INTO PAGE 10

LOC OllJ LINE SOURCE 020A AA27 329 MDV R2,HRKO 020C AB21 330 HOV R3,HRK1

331 +l 020E E9 332 +l HOV A,Rl 1ADD THO LOH BYTES 020F 211 333 +l ADD A,R3 0210 F9 334 +l HOV Rl,A 1STORE IT 0211 El 335 +l HOV A,RO 1ADD THO HIGH BYTES 0212 3A 336 +l ADDC A,R2 0213 Fl 337 +l HOV RO.A

331 +l 1PHCK>-(-HRCK)) 0214 30E702 339 JNll · ACC. 7, PR05 0217 4129 340 AJHP MIN 1IF THE RESULT IS MINUS, GO TO MIN 0219 153136 341 PR051 HOV ~:~~-I t ~~~ ~ 1STORE THE PHCK> IN PHCK-1> 021C 153937 342 HOV 021 F SS211 343 MDV ~~:Ir::~ 1STORE UCK> IN UCK-1). 0221 192C 344 HOV 0223 112D 345 HOV UKO,RO 0225 192E 346 HOV UKl,Rl 0227 4127 347 HAIT• AJMP HAIT 1HAITINO LOOP. 0229 AS27 341 MIN1 HOV RO,HRKO 1STORE -HRCK> IN PH<K-1>. 0228 A921 349 HOV Rl,HRKl

350 +l 022D OF 351 +l INC R7 022E C3 352 +l CLR c 022F E9 353 +2 HOV A,Rl 1TH0 1 S COMP. OF LOH BYTE 0230 F4 354 +l CPL A 02:n 2401 355 +l ADD A, IOlH 0233 F9 356 +2 HOV RI ,A 1STORE IT

-0234 El 357 +2 HOV A.RO 1TH0 1S COMP. OF HIGH BYTE 0235 F4 351 +l CPL A 0236 3400 359 +l ADDC A, ID 0231 Fl 360 +2 HOV RO.A 1STORE IT __.. 361 +l

0 0239 1136 362 HOV ~r,~-t~:=~ 0 0238 1937 363 HOV 0230 7521100 364 HOV UK_I0,10 1STORE 0 IN U<K-1>.

"":0240 752COO 365 HOV UK_ll, 10

~

0 ~

INTO LST Al 04/23/85 0111 JAELEE v 120 654 RECS VA TECH PRINTED 05/09/85 15157 PAGE 009

1 MCS-51 MACRO ASSEMBLER INTO

LDC OBJ LINE 0243 752000 366 0246 752EOO 367 0249 020227 368 024C 780F 369 024E 79FF 370 0250 AA27 371 0252 A828 372

373 +1 0254 Cl 374 +1 0255 E9 375 +1 0256 98 376 +1 0257 F9 377 +1 0258 EB 378 +1 0259 9A 379 +l 025A F8 380 +l

381 +l 0258 8836 382 0250 8937 383 025F 752BOF 384 0262 7 52CFF 385 0265 7 52DOF 386 0268 752EFF 387 0268 020227 388

389 390 391 392 393 394 395 396 397 398 399 400 401 402

1

SOURCE

HAXo

'

HOV UK0,10 HOV UKl,10 LJMP HAIT HOV RO,IOFH MOV Rl, IOFFH HOV R2,HRKO MDV R3,HRK1 CLR HOV SUBB HOV HOV SUBB HOV

c A,Rl A,R3 Rl,A A,RO A,R2 RO,A

1LOAD U<K> MITH O.

1U<HAX>•l2V 1LOAD R2,R3 MITH HRCK>.

1SUBTRACT LOH BYTES 1STORE IT 1SU8TRACT HIGH BYTES 1STORE IT

1U<HAX>-HR<K> HOV PHK 10,RO 1STORE THE RESULT HOV PHK 11, Rl

OF SUBTRACTION IN PHCK-1).

~g~ ~~;!i~!!~~H HOV . UKl, IOFFH LJMP HAIT

1STORE MAX. VALUE IN UCK-1>. 1LOAD U<K> MITH MAX. VALUE.

·-··----------------------------------------------------------------------------' 16 BIT• 16 BIT MULTIPLICATION SUBROUTINE

: X _Ro_ ==~= ==~= ' ---------------------------------------1 _54H<B>_ =~~~~!~: =:~::::= _4FH<A>_ ~i~~~ : _5AHCB>_ =~~~~=~= _57HCA>_ Rl•R4 ' -------------------------------------------------------------------' _RS __ RO __ Rl __ Rl __ R4_

-MCS-51 MACRO ASSEMBLER INTO

LOC OBJ

026E 752000 0271 EB

":0212 8DFO

LINE 403 404 405 406

SOURCE 1-------------------------------------------------------------------------------1 CMULo HOV ZOH,10

HOV A,R3 1R3•R5 HOV 8,R5

PAGE 11

PAGE 12

INTO LST Al 04/231'15 0111 JAELEE v 120 654 RECS VA TECH PRINTED 051'091'15 15157 PAOE 010

0274 A4 407 HUL AB 027 5 30E702 401 JllB ACC.7,RRl 0271 05FO 409 me B 027A 15F050 410 RRl• MDV 50H,B 027D E9 411 MDV A,RI 1Rl•R5 027E IDFO 412 HOV B,R5 0210 A4 413 HUL AB 0281 F551 414 HOV 51H,A 0283 15F052 415 HOV 52H,B 0286 E8 416 HOV A,RO 1ROMR5 0287 IDFO 417 HOV B,R5 0289 A4 418 HUL AB 028A f 553 419 HOV 53H,A 028C 15F054 420 MDV 54H,B 028F EB 421 HOV A,R3 1R3•R4 0290 ICFO 422 HOV B,R4 0292 A4 423 HUL AB 0293 f 555 424 HOV 55H,A 0295 85F056 425 HOV 56H,B 0291 E9 426 HOV A,RI 1Rl•R4 0299 ICFO 427 HOV B,R4 02911 A4 421 HUL AB 029C F557 429 HOV 57H,A 029E 15F0511 430 HOV 58H,B OZAi ES 431 HOV A,RO 1ROWR4 02A2 ICFO 432 HOV ll,R4 02A4 A4 433 HUL All 02A5 F559 434 HOV 59H,A 02A7 E5FO 435 HOV A,11 02A9 6003 436 JZ RR2 OZAB 0202FO 437 LJHP OVFL 02AE E550 438 RR21 HOV A,50H 150H+51H 0280 2551 439 ADD A,51H l MCS-51 HACRO ASSEHllLER INTO PAOE IS

LDC OllJ LINE SOURCE 02112 5002 440 JNC RR3 0284 0552 441 INC 52H 0286 2555 442 RR31 ADD A,55H I +55H 02111 FB 443 HOV R3,A I GET R3 0289 E552 444 HOV A,52H 1 52H+CARRY 0288 3400 445 ADDC A,10

-02BD 5002 446 JNC RR4 ...... 028F 0554 447 INC 54H

02CI 2553 441 RR41 ADD A,53H I 52H+CARRY+53H 0 02C3 5002 449 JllC RR5 TV 02C5 0551 450 me 51H 02C7 2556 451 RR51 ADD A,56H 1 52H+53H+56H 02C9 500C 452 JtlC RR7 02CB F5FO 453 HOV B,A

"':02CD E554 454 HOV A,54H

~

0 VJ

INTO LST Al 04/23/15 0111 JAELEE v 120 654 RECS VA TECH PRINTED 05/09/15 15157

02CF 3400 02Dl 5002 0203 41FO 0205 E5FO 0207 2557 0209 F9 020A E554 020C 3400 020E 5002 02EO 41FO 02E2 2551 02E4 5002 02E6 41FO 02EI 2559 02EA 5002 02EC 41FO 02EE FS 02EF 22 02FO 0520 02F2 22

1

455 456 457 451 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475

RR61 RR71

RRl1

RR91

RRl01 OVFL1

MCS-51 HACRO ASSEMBLER INTO

XREF SYHIOL TABLE LISTING ---- ------ ----- -------N A M E T Y P E V A L U E ACC .••. D ADDR OOEOH A AMAX .. , C ADDR OUCH A AMIN ••• C ADDR 01D5H A B ... • . D ADDR OOFOH A BADD ... C ADDR OlAFH A CADDl •.• C ADDR 012DH A CADD2. , • C ADDR 0136H A CADD3 ... C ADDR 013DH A CADD4. , .. C ADDR 0155H A CBADl •.• C ADDR OlBFH A CBAD2. C ADDR OlDIH A CBAD3. • , C ADDR OlDFH A CMUL •.• C ADDR 026EH A

_DlllTO. • C ADDR OOOBH A IE . • • D ADDR OOAIH A lllIT • • • C ADDR OOIBH A IP . D ADDR OOBIH A MAIN • , . C ADDR 0104H A MAX. , • C ADDR 024CH A Miii .... C ADDR 02?9H A OKI •• , • C ADDR Ol61H A

_OK2 .. , • C ADDR Ol7CH A -OK3. . . C ADDR OlllH A

ADDC A,10 JNC RR6 AJHP OVFL HOV A,1 ADD A,57H HOV Rl,A HOV A,54H ADDC A, 10 JNC RRI AJHP OVFL ADD A,51H JllC RR9 AJHP OVFL ADD A,59H JllC RRlO AJHP OVFL HOV RO,A RET INC 20H RET EllD

152H+53H+56H+57H 1 GET Rl 154H+CARRY

154H+51H

1GET RO

ATTRIBUTES AND REFERENCES 113 197 225 232 235 231 241 249 252 271 275 325 339 401 225 232 231 249 2721 271 2911 406 409 410 412 415 417 420 422 425 427 430 432 435 453 451 2631 1141 113 1911 190 1971 197 2151 269 2731 275 2921 290 293 2951 222 229 41141 791 124 136 70 1261 135 140 1441 272 294 326 3691 226 233 239 250 291 340 3411 223 2271 230 2341 235 2401

PAGE 011

PAGE 14

INTO LST Al 04123185 Dill JAELEE v 120 654 RECS VA TECH PRINTED 05109115 15157 PAGE 012

OK4 .. , • C ADDR Dl9DH A 241 247 2511 OK5 .... C ADDR DlABH A 252 2611 OVFL •.• C ADDR 02FOH A 437 457 464 467 470 4731 Pl .. D ADDR 009DH A 119 P2 ..•• D ADDR OOAOH A 13 14 15 16 91 113 111 PR04 .•. C ADDR 0206H A 325 3271 PR05 •.. C ADDR 0219H A 339 3411 PSH .•.• D ADDR OODOH A 247 269 PHK_lO , , NUMB 0036H A 331 121 261 341 362 312 PHK_l l • . NUMB 0037H A 341 129 262 342 363 313 l HCS-51 MACRO ASSEMBLER INTO PAGE 15

N A M E TY P.E V A L U E ATTRIBUTES AND REFERENCES PHKO •.• NUMB 0031H A 351 295 314 327 341 PHKI . llUMB 0039H A 361 296 315 321 342 RRl ...• C ADDR 027AH A 401 4101 RRlO ... C ADDR 02EEH A 469 4711 RR2 .•.. C ADDR 02AEH A 436 4311 RR3 ..•• C ADDR 0286H A 440 4421 RR4. , .. C ADDR 02ClH A 446 4411 RR5 ••.• C ADDR 02C7H A 449 4511 RR6 .•• , C ADDR 02D5H A 456 4511 RR7 ..•• C ADDR 02D7H A 452 4591 RRI ... , C ADDR 02E2H A 463 4651 RR9 .. , • C ADDR 02EIH A 466 .4611 SAMPLE •• C ADDR 0040H A 11 131 START .•• C ADDR OlOOH A 1421 THO ...• D ADDR OOICH A 10 131 HO. , .. D ADDR OOIAH A 79 137 THOD .•• D ADDR 0019H A 134 TRO ..•• B ADDR OOllH.4 A 139 UK_lO ... NUMB 002BH A 291 126 151 343 364 314 UK_ll .. , llUMB 002CH A 301 127 154 344 365 315 UKO ... , NUMB 002DH A 311 114 345 366 316 UKl .• , . NUMB 002EH A 321 119 346 367 317 HAIT •••. C ADDR 0227H A 3471 347 361 311 HKO .... llUMB 0025H A 251 103 130 151 215 227 HKJ. ... NUMB 0026H A 261 97 131 141 219 221 HRKO •.• llUHll 0027H A 271 107 132 145 299 329 341 371 HRKI .. NUMll 0021H A 211 112 133 146 300 330 349 372

~REGISTER BANKCS> USED• O, TARGET MACHINE<S>1 1051 _.

ASSEMBLY COMPLETE, NO ERRORS FOUND 0 ~

The vita has been removed from the scanned document