microprocessor and peripherels
TRANSCRIPT
There are 3 types of data transfer between processor and I/OProgrammed I/O : Data transfer is accomplished through an I/O port and controlled
by software.Interrupt driven I/O : I/O device will interrupt the processor and initiate data
transfer.Direct memory access (DMA) : Data transfer between memory and I/O can be
performed by bypassing the microprocessor
INTERFACING I/O AND PERIPHERAL DEVICES
For data transfer from input device to processor the following operations performed.
1) The input device will load the data to the port.
2) When the port receives a data, it sends message to the processor to read the data.
3) The processor will read the data from the port.
4) After a data have been read by the processor the input device will load the next data into the port.
Interfacing of 8085 with IC 8255 8255 is a widely used programmable parallel I/O device. It can be programmed to transfer data under various condition. Intel’s 8255 is designed for use with Intel’s 8-bit, 16-bit and higher capability
microprocessors. It has 24 input/output lines These lines may be individually programmed in two groups of twelve lines each,
or three groups of eight lines. The two groups of I/O pins are named as Group A and Group B. Each of these two groups contains a subgroup of eight I/O lines
called as 8-bit port and another subgroup of four lines or a 4-bit port.
Thus Group A contains an 8-bit port A along with a 4-bit port C upper and Group A contains an 8-bit port B along with a 4-bit port C lower.
Pin Configuration of 8255
Signals of 8255
The 8-bit data bus buffer is controlled by the read/write control logic. The read/write control logic manages all of the internal and external transfers of
both data and control words. RD (low): This control signal enables the read operation. When
this signal is low, the microprocessor reads data from a selected I/O port of the 8255A.
WR (low): This control signal enables the write operation. When this signal goes low, the microprocessor writes into a selected I/O port or the control register.
RESET: This is an active high signal. It clears the control register and set all ports in the input mode.
CS (low), A0 and A1: These are device select signals.
PA7-PA0: There are eight port A lines that acts as either latched output or buffered input lines depending upon the control word loaded into the control word
PC7-PC4 : Upper nibble of port C lines. They may act as either output latches or input buffers
lines.This port also can be used for generation of handshake lines in mode 1 or mode 2
PC3-PC0 : These are the lower port C lines, other details are the same as PC7-PC4 lines.
PB0-PB7 : These are the eight port B lines which are used as latched output lines or buffered input lines in the same way as port A.
RD : This is the input line driven by the microprocessor and should be low to indicate read operation to 8255.
WR : This is an input line driven by the microprocessor. A low on this line indicates write operation.
CS : This is a chip select line. If this line goes low, it enables the 8255 to respond
to RD and WR signals, otherwise RD and WR signal are neglected.
D0-D7 : These are the data bus lines those carry data or control word to/from the
microprocessor.
RESET : A logic high on this line clears the control word register of 8255. All
ports are set as input ports by default after reset.
A1-A0 : These are the address input lines and are driven by the microprocessor.
These lines A1-A0 with RD , WR and CS from the following operations for
8255. These address lines are used for addressing any one of the four registers, i.e.
three ports and a control word register as given in table below.
Interfacing I/O mapping Example
Interfacing Memory Mapping Example
8255 interfacing with 8086 I/O mapping
Hex address
Port A
80h
Port B
82h
Port C
84h
CWR 86h
8255 interfacing with 8086 I/O mapping
8255(low)
8255(high)
Port A
80 h 81 h
Port B
82 h 83 h
Port C
84 h 85 h
CWR 86 h 87 h
The content of register is called control wordBit D7 specifies the either I/O function or BSR functionTo communicate with peripheral through 8255 necessary steps are
(1)Determine the address of port A,B and C and of the control register according to the chip select logic and the address A0 and A1
(2)Write a control word in the control register
(3)Write I/O instruction to communicate with peripheral through port
A,B and C
A7 A6 A5 A4 A3 A2
A1 A0
HEX ADDRESS
PORT
1 0 0 0 0 0
0 0
80 H A
0 1
81 H B
1 0 82 H C
1 1
83 H CONTROL REGISTER
control word format
D7
0/1
D6 D5 D4 D3 D2 D1
D0
BSR Mode I/O mode
Mode 0Simple I/OFor port A,B and C
Mode 1Handshake I/OFor port A and/or BPort C used for handshake
Mode 2 Bidirectional data bus for Port APort B: Either 0 or 1Port C bit used for handshake
CONTROL WORD
Mode of operation of 8255 These are two basic modes of operation of 8255.
I/O mode and Bit Set-Reset mode (B SR)BSR Mode: In this mode any of the 8-bits of port C can
be set or reset.
I/O mode: In this mode the 8255 ports work as programmable I/O ports,
The I/O mode of operation, further there are three modes of operation of 8255, so as to support different types of applications, mode 0, mode 1 and mode 2.
B S R ModeBSR Mode: In this mode any of the 8-bits of port C can be set or reset depending
on D0 of the control word. The bit to be set or reset is selected by bit select flags
D3, D2 and D1 of the CWR.
Write a control word subroutine to set PC7 and PC3 and reset them after 10ms. Assume that delay subroutine is available
BSR control word
D7 D6
D5
D4
D3
D2
D1
D0
To set PC7
0 0 0 0 1 1 1 1 0F H
To reset PC7
0 0 0 0 1 1 1 0 0E H
To set PC3
0 0 0 0 0 1 1 1 07 H
To reset PC3
0 0 0 0 0 1 1 0 06H
Example
MVI A,0FH
OUT 83 H
MVI A,07 H
OUT 83 H
CALL DELAY
MVI A,06 H
OUT 83 H
MVI A, 0E H
OUT 83 H
RET
MODE 0-Simple I/O This mode is also called as basic input/output mode. This mode provides simple input and output using each of the three ports. Data can be simply read from and written to the input and output ports respectively
1) Two 8-bit ports ( port A and port B )and two 4-bit ports (port C upper and lower ) are available.
2) The two 4-bit ports can be combined as a third 8-bit port.3) Any port can be used as an input or output port.4) Output ports are latched. Input ports are not latched.5) A maximum of four ports are available so that overall 16 I/O configuration are
possible.6) Ports do not have handshake or interrupt capability 7) All these modes can be selected by programming a register internal to 8255 known as
CWR.
Question:-write control word for Port A as InputPort CL as InputPort CU as output Port B not used
=> 91 H
Mode 1 Input/output with handshake
Handshake signal are transferred before and after the data transfer to check whether the data transfer is done correctly or not(without any error)
In this mode the handshaking control the input and output action of the specified port.
Port A and Port B can be operated in I/O mode where as port C is used for transferring handshake signal.
Port C lines PC0-PC2, provide strobe or handshake lines for port B. Port C lines PC3-PC5 provide strobe lines for port A. PC6, PC7 may be used as independent data lines Each group contains one 8-bit data I/O port and one 4-bit control/data port The 8-bit data port can be either used as input and output
port Input and output data are latched Interrupt logic supported
Mode 1 control signal
STB( Strobe input ) – If this lines falls to logic low level the data available at 8-bit input port is loaded into input latches. It indicates that a byte of data has been transmitted.
IBF ( Input buffer full ) – This signal is acknowledge by 8255 to indicate that latch has received the data byte.
INTR ( Interrupt request ) – This active high output signal can be used to interrupt the CPU whenever an input device requests the service. INTR is set if STB, IBF and INTE are all at logic 1. This is reset by falling edge of RD signal
INTE(Interrupt Enable) This is an internal flip flop used to enable or disable the generation of the INTR signal. 2 flip flop INTEA and INTEB set or reset by BSR mode. INTEA is enable or disable through PC4 and INTEB is enable or disable through PC2
Input control signal
Control word sets up port A and port B as input port in mode 1.Status word placed in accumulator if port C is read.
Output control signalOBF (Output buffer full ) – This status signal, whenever falls to low,
indicatesthat CPU has written data into the output latch of 8255. This line indicate to an output peripheral that a new data are ready to be read.
ACK (Acknowledge input) – ACK signal acts as an acknowledgement to begiven by an output device. ACK signal, whenever low, informs the CPU that thedata transferred by the CPU to the output device through the port is received bythe output device.
INTR ( Interrupt request ) – Thus an output signal that can be used to interruptthe CPU when an output device acknowledges the data received from the CPU to request for next data byte for the output. INTR is set when ACK, OBF and INTE are 1. It is reset by a falling edge on WR.
INTE(Interrupt enable)- Internal flip-flop to a port and needs to be set to generate the INTR signal.
PC4,5- can be set up either input or output
Control word sets up port A and port B as input port in mode 1.Status word placed in accumulator if port C is read.
ExamplePort A is designed as input port for a keyboard with interrupt I/O and port B is designed as out put port for a printer with status check I/O
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 0 1 0 0
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 1 0 0 1
D7 D6 D5 D4 D3 D2 D1 D0
X X X X X X OBF X
5) Program
MVI A,B4H—intilize port A & port B
OUT FFH
MVI A,09H—set INTEA(PC4)
OUT FFH
EI
CALL PRINT
PRINT : LXI H,MEM ADDR
MVI B,COUNT
NEXT: MOV A,M
MOV C,A
STATUS:IN FEH
ANI 02H
JZ STATUS
MOV A,C
OUT FDH
INX H
DCR B
JNZ NEXT
RET
Mode 2 Bidirectional ModeThis mode of operation of 8255 is also called as strobed bidirectional I/O.Port A can be used as bidirectional port and port B either in mode0 or mode1. port C
used for transferring handshake signal between port A and B.Handshaking signals are provided to maintain proper data flow and synchronization
between the data transmitter and receiver.
The Salient features of Mode 2 of 8255 are listed as follows:1. The single 8-bit port in group A is available.2. The 8-bit port is bidirectional and additionally a 5-bit control port is available.3. Three I/O lines are available at port C.( PC2 – PC0 )4. Inputs and outputs are both latched.5. The 5-bit control port C (PC3-PC7) is used for generating / accepting handshake signals for the 8-bit data transfer on port A.
Control signal definitions in mode 2
INTR – (Interrupt request) This control signal is active high and is used to interrupt the microprocessor to ask for transfer of the next data byte to/from it. This signal is used for input ( read ) as well as output ( write ) operations.
Control Signals for Output operations:OBF ( Output buffer full ) – This signal when falls to low level indicates that the
CPU has written data to port A.
ACK ( Acknowledge ) This control input, when falls to logic low level acknowledges that the previous data byte is received by the destination and next byte may be sent by the processor. This signal enables the internal tristate buffers to send the next data byte on port A.
INTE1 (Flag associated with OBF) This can be controlled by bit set/reset mode with PC6.
Control signals for input operations : STB (Strobe input) A low on this line is used to strobe in the data into the input latches of 8255.
IBF ( Input buffer full ) When the data is loaded into input buffer, this signal rises to logic ‘1’. This can be used as an acknowledge that the data has been received by the receiver.
Port B can either be set to Mode 0 or 1 with port A( Group A ) is in Mode 2.Mode 2 is not available for port B. The following fig shows the control word
8254-Timer
8254-TimerThe 8254 is a programmable interval timer/counter designed for use with Intel microcomputer systems.
It is a general purpose, multi-timing element that can be treated as an array of I/O ports in the system software
The 8254 solves the problem of generation of accurate time delays under software control. Instead of setting up timing loops in software, the programmer configures the 8254 to match his requirements and programs one of the counters for the desired delay After the desired delay, the 8254 will interrupt the CPU.
Features:
Status Read-Back Command
Six Programmable Counter Modes
Three Independent 16-Bit Counters
Binary or BCD Counting
Standard Temperature Range
Event-counter
Digital one-shot
Programmable rate generator
It provides three independent 16-bit counters, each capable of handling clock inputs up to 10 Hz.
Pin DiagramCompatible with All Intel and Most other Microprocessors Handles Inputs from DC to 10 MHz
• 8 MHz 8254• 10 MHz 8254-2
All modes are software programmable. The 8254 is a superset of the 8253.The 8254 uses HMOS technology and comes in a 24-pin plastic or CERDIP package.
Accurate time delayDivide by N counterSquare wave generator
Block Diagram
Data Bus Buffer: 8 bit bidirectional buffer connected to data bus of MPU
READ/WRITE LOGIC : The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the 8254.
A1 and A0 select one of the three counters or the Control Word Register to be read from/written into.
CONTROL WORD REGISTER :
The Control Word Register is selected by the Read/Write Logic when A1,A0 = 11.
It is used to write a command word to specify the counter to be used, its mode and either read or write operation.
A0 A1
Selection
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Register
Both RD and WR are qualified by CS.RD and WR are ignored unless the 8254 has been selected by holding CS low.A ``low'' on the RD input tells the 8254 that the CPU is reading one of the counters.A ``low'' on the WR input tells the 8254 that the CPU is writing either a Control Word or an initial count.
Counters: The Counters are fully independent. Each Counter may operate in a different Mode. 8254 can operate in 6 different mode. Gate of counter used to enable or disable the counting
The Control Word Register contents determine how the Counter operates.The status register when latched, contains the current contents of the Control Word Register and status of the
output and null count flag The actual counter is labeled CE (for ``Counting Element''). It is a 16-bit presettable synchronous down
counter. When a new count is written to the Counter, the count is stored in the CR and later transferred to the CE. The Control Logic allows one register at a time to be loaded from the internal bus. Both bytes are transferred to
the CE simultaneously.CLK n, GATE n, and OUT n are all connected to the outside world through the Control Logic.
Control word Register
Programming of 82548254 can be programmed in various type of output through
write operation.Write operation=>
Write the control word in the control registerLoad the lower byteLoad the higher byte
A clock and an appropriate gate signal to one of the counter
Read operations1) A simple READ operation:
Select the Counter with the A1,A0 inputs. Inhibit(stop) the counter to be read via controlling the GATE input or CLK of the selected counter.
2). Counter Latch Command (does not disturb the count in progress):
It is written to the Control Word Register like a Control Word, but two bits (D5,D4) distinguish this command from a Control Word.
The selected Counter's OL latches the count at the time the Counter Latch Command is received.
The count is held in the latch until it is read by the CPU. The count is then unlatched automatically and the OL returns to "following"
the CE.3) Read-Back Command:This command allows the user to check the count value, programmed Mode,
and current states of the OUT pin and Null Count flag of the selected counter(s).
This command is similar to several Counter Latch Commands, one for each counter latched.
8254 System InterfaceThe select inputs A0,A1 connect to the A0,A1 address bus signals of theCPU. The CS can be derived directly from the address bus using a linear select method Or it can be connected to the output of a decoder
Mode 0 Interrupt on terminal
Mode 1 hardware retrigger able(programmable) one shot
Mode 2 Rate Generator
Mode 3 Square wave generator
Mode 4 software triggered strobe
Mode 5 hardware triggered strobe
Write program to generate a pulse every 50 us from counter 0
=>14H
Frequency of 8254 is 2MHz; Time period is 0.5 us
count = (50 us) / (0.5 us) = 100 = 64H
MVI A,14H
OUT 83H----8254 CONTROL WORD REGISTER
MVI A, 64H
OUT 80H-----LOAD COUNTER 0
HALT
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 1 0 1 0 0
Write program to generate a 1KHz square wave from counter 1
Square wave in mode 3
Control word=>
Frequency of 8254 2MHz ; Time period 0.5 us
Square wave frequency 1 KHz; Time period 1 ms
Count= (1 ms) / (0.5 us) = 2000 = 07D0 H
MVI A,76H
OUT 83H------CWR
MVI A,D0H
OUT 81H-----LOAD LOWER BYTE
MVI A,07H
OUT 81H----LOAD HIGHER BYTE
HALT
D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 1 0 1 1 0
I/O mapped I/O interfacing
Memory mapped memory interfacing
8254 interfacing with 8086 I/O mapping
8254 interfacing with 8086 memory mapping
20 address lines to identify an I/O device, an I/O device is connected as if it is a memory register
8279 Keyboard & DisplayIntel’s 8279 is a general purpose keyboard display controller
It simultaneously drives the display of a system and interfaces a keyboard with the CPU.
The keyboard display controller chip 8279 provides:1) A set of four scan lines and eight return lines for interfacing keyboards
2) A set of eight output lines for interfacing display
8279 are divided into 4 functional group
CPU data
Key data
Scan data
Display data
Block Diagram
I/O Control and Data Buffers : The I/O control section controls the flow of data to/from the 8279. The data buffers interface the external bus of the system with internal bus of 8279. The I/O section is enabled only if CS is low. The pins A0, RD and WR select the command, status or data read/write operations carried out by the CPU with 8279
Control and Timing Register and Timing Control : These registers store the keyboard and display modes and other operating conditions programmed by CPU. The Timing and control unit controls the basic timings for the operation of the circuit. Scan counter divide down the operating frequency of 8279 to derive scan keyboard and scan display frequencies.
Scan Counter : The scan counter has two modes to scan the key matrix and refresh the display.
In the encoded mode, the counter provides binary count 0000 to 1111 that is to be externally decoded to provide the scan lines SL0-SL3 for keyboard and display. Binary count must be externally decoded.
In the decode scan mode, the counter internally decodes the least significant 2 bits and provides 4 possible combination 1110,1101,1011,0111 on scan on SL0-SL3. The output of these line are active low
keyboard section This section consist of return buffer, keyboard debounce control, FIFO
sensor RAM and FIFO sensor RAM status. 3 keyboard input mode are (1) Scanned keyboard (2) Sensor matrix (3) Strobed Input
8 return lines RL0 - RL7 are buffered and latched by return buffer during each row scan in scanned keyboard and senspr matrix keyboard. In strobed input mode the content of return line are transferred to FIFO Ram
Keyboard debounce control looking for key clousres in that row. In scanned keyboard only if debounce circuit detect a close switch it wait for 10. After the debounce period, if the key continues to be detected. The code of key is directly transferred to the sensor RAM along with SHIFT and CONTROL key status.
FIFO RAM status keeps track the number of character in the FIFO and whether it is full or empty.
The two operating modes of keyboard section are 2-key lockout and N-key rollover.
In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is recognized.
In the N-key rollover mode simultaneous keys are recognized and their codes are stored in FIFO.
The format of key code entry in FIFO for scan keyboard mode
(SCAN) (RETURN)
Display Address Registers and Display RAM :
The display address register holds the address of the word currently being written or read by the CPU to or from the display RAM. The contents of the registers are automatically updated by 8279 to accept the next data entry by CPU. The display section has eight output lines divided into two groups A0-A3 and B0-B3.
The 8279 provides two basic output mode
left Entry (Typewriter)—Display character left to right
Right Entry (Calculator)—Display character right to left
If auto increment flag is set to1 after each write operation
Display RAM address is incremented by one.
CPU interface section: The CPU interface section takes care of data transfer between 8279 and the processor.
This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and CPU.
It requires two internal address A =0 for selecting data buffer and A = 1 for selecting control register of8279.
The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279.
It has an interrupt request line IRQ, for interrupt driven data transfer with processor.
The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the input clock by an internal prescaler.
The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard modes.
Pin Diagram
Interfacing Scheme
Signal Description DB0-DB7 : These are bidirectional data bus lines. The data and command
words to and from the CPU are transferred on these lines. CLK : This is a clock input used to generate internal timing required by
8279. RESET : This pin is used to reset 8279. A high on this line reset 8279.
After resetting 8279, its in sixteen 8-bit display, left entry encoded scan, 2-key lock out mode. The clock prescaler is set to 31.
CS : Chip Select – A low on this line enables 8279 for normal read or write operations. Other wise, this pin should remain high.
A0 : A high on this line indicates the transfer of a command or status information. A low on this line indicates the transfer of data. This is used to select one of the internal registers of 8279.
RD, WR (Input/output ) READ/WRITE – These input pins enable the data buffers to receive or send data over the data bus.
IRQ : This interrupt output lines goes high when there is a data in the FIFO sensor RAM. The interrupt lines goes low with each FIFO RAM read operation but if the FIFO RAM further contains any key-code entry to be read by the CPU, this pin again goes high to generate an interrupt to the CPU.
Vss, Vcc : These are the ground and power supply lines for the circuit.
SL0-SL3-Scan Lines : These lines are used to scan the key board matrix and display digits. These lines can be programmed as encoded or decoded, using the mode control register.
RL0 - RL7 - Return Lines : These are the input lines which are connected to one terminal of keys, while the other terminal of the keys are connected to the decoded scan lines. These are normally high, but pulled low when a key is pressed.
SHIFT : The status of the shift input lines is stored along with each key code in FIFO, in scanned keyboard mode. It is pulled up internally to keep it high, till it is pulled low with a key closure.
BD – Blank Display : This output pin is used to blank the display during digit switching or by a blanking closure.
OUT A0 – OUT A3 and OUT B0 – OUT B3 – These are the output ports for two 16*4 or 16*8 internal display refresh registers. The data from these lines is synchronized with the scan lines to scan the display and keyboard. The two 4-bit ports may also as one 8-bit port.
CNTL/STB- CONTROL/STROBED I/P Mode : In keyboard mode, this lines is used as a control input and stored in FIFO on a key closure. The line is a strobed lines that enters the data into FIFO RAM, in strobed input mode. It has an interrupt pull up. The lines is pulled down with a key closer.
Command Words of 8279All the command words or status words are written or read with A0 = 1 and
CS = 0 to or from 8279
(1) Keyboard / Display mode set command (000)
Programmable clock command(001) : The clock for operation of 8279 is obtained by dividing the external clock input signal by a programmable constant called prescaler. PPPPP is a 5-bit binary constant. The input frequency is divided by a decimal constant ranging from 2 to 31, decided by the bits of an internal prescaler PPPPP.
To give proper scan and key debounce the internal clock frequency should be 100KHz.
Hence
(3) Read FIFO / Sensor RAM command(010) : To read data from FIFO / Sensor RAM set 8279 in Read FIFO/Sensor RAM mode.
3 LSB “AAA” specify the address of the sensor.
D4 bit specify the auto increment mode. In scanned keyboard AAA and AI bit are irreverent.
Question :- write a command word to read data from FIFO RAM
In scanned keyboard mode
AAA and AI are irreverent
Question:- write a command word to read third location with auto increment in sensor RAM in sensor matrix mode
(4) Read display RAM command (011):- This command enables a programmer to read the display RAM data.
4 LSB “AAAA” specify the address of 16 bit display RAM. Auto increment mode(D4) bit set to 1 display RAM address is incremented after each read command.
Question:- write a command to read 4th location with auto increment in read display mode.
(5) Write Display RAM command (100):- To write data in display RAM 8279 set in write display mode.
4 LSB “AAAA” specify the address of 16 bit display RAM. Auto increment mode(D4) bit set to 1 display RAM address is incremented after each write command.
(5) Display Write Inhibit/Blanking command(101):-The IW ( inhibit write flag ) bits are used to mask the individual nibble. Once a nibble is masked by setting the corresponding IW bit to 1
(6) Clear Display RAM command (110) : The CD2, CD1, CD0 is a selectable blanking code to clear all the rows of the display RAM
CD2 must be 1 for enabling the clear display command. CA clear All . CF clear flag set to clear the status of FIFO.
Question:- write command word to set blanking code for common anode display and to clear FIFO status.
(8) End Interrupt / Error mode Set command (111):-For the sensor matrix mode, this command lowers the IRQ line and enables further writing into the RAM
Memory mapped I/O interfacing
8259-Programmable Interrupt Controller It is programmed to work with either 8085 or 8086 processor. It manage 8-interrupts according to the instructions written into its control
registers. If we save NMI for a power failure interrupt, this leaves only one interrupt
for all the other applications. For applications where we have interrupts from multiple source, we use an external device called a priority interrupt controller ( PIC ) to the interrupt signals into a single interrupt input on the processor.
The interrupts can be masked or unmasked individually. The 8259s can be cascaded to accept a maximum of 64
interrupts. All the interrupt can be prioritize Each interrupt request individually Set up to either edge trigger or level triggered interrupt Vector address of Interrupt assigned by user
Block Diagram
It has eight functional blocks. They are1) Control logic-- This block manages the interrupt and interrupt
acknowledge signals to be sent to the CPU for serving one of the eight interrupt requests.
2) Read Write logic--- This circuit accepts and decodes commands from the CPU. This block also allows the status of the 8259A to be transferred on to the data bus.
3) Data bus buffer4) Interrupt Request Register (IRR)—keeps information of incoming interrupt5) In-Service Register (ISR)—keeps information of interrupt currently executed6) Interrupt Mask Register (IMR)—keeps information of interrupt can be masked7) Priority Resolver (PR)—checks the priority of incoming interrupt8) Cascade buffer:---The data bus and its buffer are used for the following activities.
The processor sends control word to data bus buffer through D0-D7. The processor read status word from data bus buffer through D0-D7From the data bus buffer the 8259 send type number (in case of 8086) or the call opcode and address (in case of 8085) through D0-D7 to the processor.
Signal DescriptionCS: This is an active-low chip select signal for enabling RD and WR operations of 8259A.RD : This is an active-low read enable input to 8259A. A low on this line enables 8259A to release status onto the data bus of CPU.The processor uses the RD (low), WR (low) and A0 to read or write 8259.D0-D7 : These pins from a bidirectional data bus that carries 8-bit data either to control word or from status word registers. This also carries interrupt vector information.CAS0 – CAS2 Cascade Lines : A signal 8259A provides eight vectored interrupts. If more interrupts are required, the 8259A is used in cascade mode. In cascade mode, a master 8259A along with eight slaves 8259A can provide up to 64 vectored interrupt lines. These three lines act as select lines for addressing the slave 8259A.SP/EN : (Slave program/ Enable Buffer)This pin is a dual purpose pin. When the chip is used in buffered mode, it can be used as buffered enable to control buffer transreceivers. If this is not used in buffered mode then the pin is used as input to designate whether the chip is used as a master (SP =1) or slave (EN = 0).INT : This pin goes high whenever a valid interrupt request is asserted. This is used to interrupt the CPU and is connected to the interrupt input of CPU.IR0 – IR7 (Interrupt requests) :These pins act as inputs to accept interrupt request to the CPU A0- Command Select Address
Command Words of 82598259 initialized by writing control word in the control register.
The command words of 8259A are classified in two groups
1. Initialization command words (ICW)
2. Operation command words (OCW).
ICW are used to set up the proper condition and specify the vector address.
OCW use to perform specific function (masking)
8259 initialed with 4 ICW first two are essential. Other 2 are operational and based on mode being used.
Control Word
ICW 2
ICW 3
Initialization SequenceAfter 8259 initialized following sequence of event occur1) IRR store the request2) PR checks 3 register IRR, IMR and ISR it resolves the priority and set the
INT high3) MPU acknowledge the interrupt by sending INTA4) On receiving INTA appropriate bit in ISR set to indicate which interrupt is
being served and corresponding bit in IRR reset to indicate interrupt is accepted. Opcode of CALL instruction is placed on the data bus.
5) When MPU decodes the CALL instruction, it places the 2 more INTA signal on the data bus
6) When 8259 receive second INTA it place lower order byte of CALL address on the data bus. At the third INTA it places the higher order byte on the data bus.
7) During third INTA pulse ISR bit is reset automatically or by command word that must be issued at the end of service routine.
8) Program sequence is transferred to memory location specified by CALL instruction
Initialization Instruction
DIMVI A,76H—ICW1OUT 80HMVI A,20H---ICW2OUT 81H
I/O Mapped I/O interfacing
Cascading of 8259 8259 cascaded to get multiple interrupts. In cascaded mode one 8259 configured as master mode while other slave
mode 8259-1 acts as master while other acts as slave Master INT pin is connected directly to 8085 INTR pin Slave INT is connected to IR pin of master’s 8259 INTA pin is connected to both master and slave CAS0 to CAS2 pin are connected from master to corresponding slave pin.
For master CAS pin functions as output & for slave these acts as input SP/EN pin tied high for master and ground for slave
8086 interfacing with 8259 I/O mapping
LOWER BANK HEX ADDRESS
FFFO
FFF2
Interfacing of DAC with 8255IC 1408 consist of a reference current amplifier, R-2R ladder resistor network and 8
high speed current switches.
8 input data line controls the position of current switches.
DAC interfacing is done via 8255
8255 used to send serial digital data to DAC
Control Word to initialize all port as output port (mode 0)1 0 0 0 0 0 0 0 8 0 H
Pin Diagram
ADC converts analog input to the corresponding digital output.ADC designed to operate from microprocessor control bus and data bus.ADC 0808 has 8 input channel
Interfacing of ADC with 8085 can be done with 8255
To select 8 input channel 3 input address needed on inpit pin ADC,ADB and ADA. The address of desired channel is send through PB0-PB2 After 50 ns this address latched, A LE pin signal through PB3 After 25 ns SoC (start of conversion) send through PB4 The EoC (end of conversion) is detected through PC0 8-bit data line is connected through PA0-PA7 Zener diode produces reference voltage 5.12 V With this reference voltage ADC have 256 steps of 20 mv
PA,PB,PC of 8255 used in mode 0