microkernels and l4 - cse.unsw.edu.aucs9242/05/lectures/01-l4.pdf · • applications communicate...
TRANSCRIPT
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Microkernels and L4
Introduction
COMP9242 2005/S2 Week 1
cse/UNSW/NICTA
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WHY MICROKERNELS ?
MONOLITHIC KERNEL
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WHY MICROKERNELS ?
MONOLITHIC KERNEL :
• Kernel has access to everything
➜ all optimisations possible➜ all techniques/mechanisms/concepts
implementable
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WHY MICROKERNELS ?
MONOLITHIC KERNEL :
• Kernel has access to everything
➜ all optimisations possible➜ all techniques/mechanisms/concepts
implementable
• Can be extended by simplyadding code
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WHY MICROKERNELS ?
MONOLITHIC KERNEL :
• Kernel has access to everything
➜ all optimisations possible➜ all techniques/mechanisms/concepts
implementable
• Can be extended by simplyadding code
• Cost: Complexity
➜ growing size➜ limited maintainability
cse/UNSW/NICTA COMP9242 2004/S2 W3 P1
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MICROKERNEL : IDEA
• Small kernel providing core functionality
➜ only code running in privileged mode
• Most OS services provided by user-level servers
• Applications communicate with servers via message-passing IPC
FileServer
MemoryServer
TaskServer
Application
Microkernel
IPC
cse/UNSW/NICTA COMP9242 2004/S2 W3 P2
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
Application
System: traditionalembedded
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
Application
System: traditionalembedded
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
Application
System: traditionalembedded
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
System: traditionalembedded
Linux/Windows
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
System: traditionalembedded
Linux/Windows
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
System: traditionalembedded
Linux/Windows
![Page 14: Microkernels and L4 - cse.unsw.edu.aucs9242/05/lectures/01-l4.pdf · • Applications communicate with servers via message-passing IPC File Server Memory Server Task Server Application](https://reader035.vdocuments.site/reader035/viewer/2022062505/5ee0e9b8ad6a402d666bfb28/html5/thumbnails/14.jpg)
TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
System: traditionalembedded
Linux/Windows
![Page 15: Microkernels and L4 - cse.unsw.edu.aucs9242/05/lectures/01-l4.pdf · • Applications communicate with servers via message-passing IPC File Server Memory Server Task Server Application](https://reader035.vdocuments.site/reader035/viewer/2022062505/5ee0e9b8ad6a402d666bfb28/html5/thumbnails/15.jpg)
TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
System: traditionalembedded
Linux/Windows
![Page 16: Microkernels and L4 - cse.unsw.edu.aucs9242/05/lectures/01-l4.pdf · • Applications communicate with servers via message-passing IPC File Server Memory Server Task Server Application](https://reader035.vdocuments.site/reader035/viewer/2022062505/5ee0e9b8ad6a402d666bfb28/html5/thumbnails/16.jpg)
TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
Application
Hardware
Microkernel
Service
System: traditionalembedded
Linux/Windows
Microkernel-based
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
Application
Hardware
Microkernel
Service
System: traditionalembedded
Linux/Windows
Microkernel-based
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
Application
Hardware
Microkernel
Service
System: traditionalembedded
Linux/Windows
Microkernel-based
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TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
Application
Hardware
Microkernel
Service
System: traditionalembedded
Linux/Windows
Microkernel-based
![Page 20: Microkernels and L4 - cse.unsw.edu.aucs9242/05/lectures/01-l4.pdf · • Applications communicate with servers via message-passing IPC File Server Memory Server Task Server Application](https://reader035.vdocuments.site/reader035/viewer/2022062505/5ee0e9b8ad6a402d666bfb28/html5/thumbnails/20.jpg)
TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
Application
Hardware
Microkernel
Service
System: traditionalembedded
Linux/Windows
Microkernel-based
![Page 21: Microkernels and L4 - cse.unsw.edu.aucs9242/05/lectures/01-l4.pdf · • Applications communicate with servers via message-passing IPC File Server Memory Server Task Server Application](https://reader035.vdocuments.site/reader035/viewer/2022062505/5ee0e9b8ad6a402d666bfb28/html5/thumbnails/21.jpg)
TRUSTED COMPUTING BASE
The part of the system which must be trusted to operate correctly
Hardware
Service
ApplicationApplication
Hardware
OS
Service
Application
Hardware
Microkernel
Service
System: traditionalembedded
Linux/Windows
Microkernel-based
TCB: all code 100,000’s loc 10,000’s loc
cse/UNSW/NICTA COMP9242 2004/S2 W3 P3
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MICROKERNEL PROMISES
• Combat kernel complexity, increase robustness, maintainability
➜ dramatic reduction of amount of privileged code➜ modularisation with hardware-enforced interfaces➜ normal resource management applicable to system services
• Flexibility, adaptability, extensibility
➜ policies defined at user level, easy to change➜ additional services provided by adding servers
• Hardware abstraction
➜ hardware-dependent part of system is small, easy to optimise
• Security, safety
➜ internal protection boundaries
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MICROKERNEL PROMISES
• Combat kernel complexity, increase robustness, maintainability
➜ dramatic reduction of amount of privileged code➜ modularisation with hardware-enforced interfaces➜ normal resource management applicable to system services
• Flexibility, adaptability, extensibility
➜ policies defined at user level, easy to change➜ additional services provided by adding servers
• Hardware abstraction
➜ hardware-dependent part of system is small, easy to optimise
• Security, safety
➜ internal protection boundaries
REALITY CHECK!
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MICROKERNEL PROMISES
• Combat kernel complexity, increase robustness, maintainability
➜ dramatic reduction of amount of privileged code➜ modularisation with hardware-enforced interfaces➜ normal resource management applicable to system services
• Flexibility, adaptability, extensibility
➜ policies defined at user level, easy to change➜ additional services provided by adding servers
• Hardware abstraction
➜ hardware-dependent part of system is small, easy to optimise
• Security, safety
➜ internal protection boundaries
REALITY CHECK!
slow, inflexible
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MICROKERNEL PROMISES
• Combat kernel complexity, increase robustness, maintainability
➜ dramatic reduction of amount of privileged code➜ modularisation with hardware-enforced interfaces➜ normal resource management applicable to system services
• Flexibility, adaptability, extensibility
➜ policies defined at user level, easy to change➜ additional services provided by adding servers
• Hardware abstraction
➜ hardware-dependent part of system is small, easy to optimise
• Security, safety
➜ internal protection boundaries
REALITY CHECK!
slow, inflexible
100µsec IPC
cse/UNSW/NICTA COMP9242 2004/S2 W3 P4
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IPC COSTS
• First-generation microkernels
➜ Mach, Chorus, Amoeba
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IPC COSTS
• First-generation microkernels
➜ Mach, Chorus, Amoeba
... were slow...
➜ 100µs IPC➜ almost independent of clock speed!
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IPC COSTS
• First-generation microkernels
➜ Mach, Chorus, Amoeba
... were slow...
➜ 100µs IPC➜ almost independent of clock speed!
• L4 does better
➜ close to hardware cost➜ 20 times faster than Mach
on identical hardware
cse/UNSW/NICTA COMP9242 2004/S2 W3 P5
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IPC COST IMPLICATIONS
cse/UNSW/NICTA COMP9242 2004/S2 W3 P6
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L4 IPC
cse/UNSW/NICTA COMP9242 2004/S2 W3 P7
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MICROKERNEL PERFORMANCE
FIRST-GENERATION MICROKERNELS WERE SLOW
• Reasons: Poor design [Liedtke SOSP 95]
➜ complex API➜ too many features➜ poor design and implementation
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MICROKERNEL PERFORMANCE
FIRST-GENERATION MICROKERNELS WERE SLOW
• Reasons: Poor design [Liedtke SOSP 95]
➜ complex API➜ too many features➜ poor design and implementation➜ large cache footprint : memory bandwidth limited
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MICROKERNEL PERFORMANCE
FIRST-GENERATION MICROKERNELS WERE SLOW
• Reasons: Poor design [Liedtke SOSP 95]
➜ complex API➜ too many features➜ poor design and implementation➜ large cache footprint : memory bandwidth limited
• L4 is fast due to small cache footprint
➜ 10–14 I-cache lines➜ 8 D-cache lines➜ small cache footprint : CPU limited
cse/UNSW/NICTA COMP9242 2004/S2 W3 P8
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WHAT MAKES A MICROKERNEL FAST?
• Small cache footprint, but how?
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WHAT MAKES A MICROKERNEL FAST?
• Small cache footprint, but how?
➜ minimality: no unnecessary features➜ orthogonality: complementary features➜ well-designed, and well implemented from scratch!
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WHAT MAKES A MICROKERNEL FAST?
• Small cache footprint, but how?
➜ minimality: no unnecessary features➜ orthogonality: complementary features➜ well-designed, and well implemented from scratch!
• Kernel provides mechanisms, not services
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WHAT MAKES A MICROKERNEL FAST?
• Small cache footprint, but how?
➜ minimality: no unnecessary features➜ orthogonality: complementary features➜ well-designed, and well implemented from scratch!
• Kernel provides mechanisms, not services
• Design principle (minimality):
A feature is only allowed in the kernel if this is required for theimplementation of a secure system.
cse/UNSW/NICTA COMP9242 2004/S2 W3 P9
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L4 H ISTORY
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L4 H ISTORY
• Original version by Jochen Liedtke (GMD) ≈ 93–95
➜ “Version 2” API➜ i486 assembler➜ IPC 20 times faster than Mach [SOSP 93, 95]
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L4 H ISTORY
• Original version by Jochen Liedtke (GMD) ≈ 93–95
➜ “Version 2” API➜ i486 assembler➜ IPC 20 times faster than Mach [SOSP 93, 95]
• Other L4 V2 implementations:
➜ L4/MIPS64: assembler + C (UNSW) 95–97➜ fastest kernel on single-issue CPU (100 cycles)
➜ L4/Alpha: PAL + C (Dresden/UNSW), 95–97➜ first released SMP version
➜ Fiasco (Pentium): C++ (Dresden), 97–99
cse/UNSW/NICTA COMP9242 2004/S2 W3 P10
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L4 H ISTORY
• Experimental “Version X” API
➜ improved hardware abstraction➜ various experimental features (performance, security, generality)➜ portability experiments
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L4 H ISTORY
• Experimental “Version X” API
➜ improved hardware abstraction➜ various experimental features (performance, security, generality)➜ portability experiments
• Implementations
➜ Pentium: assembler, Liedtke (IBM), 97-98➜ Hazelnut (Pentium+ARM), C, Liedtke et al (Karlsruhe), 98–99
cse/UNSW/NICTA COMP9242 2004/S2 W3 P11
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L4 H ISTORY
• “Version 4” (X.2) API, 02
➜ portability, API improvements
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L4 H ISTORY
• “Version 4” (X.2) API, 02
➜ portability, API improvements
• L4Ka::Pistachio, C++ (plus assembler “fast path”)
➜ x86, PPC-32, Itanium (Karlsruhe), 02–03➜ fastest ever kernel (36 cycles, NICTA/UNSW)
➜ MIPS64, Alpha (NICTA/UNSW) 03➜ same performance as V2 kernel (100 cycles single issue)
➜ ARM, PPC-64 (NICTA/UNSW), x86-64 (Karlsruhe), 03-04➜ UltraSPARC (NICTA/UNSW), 04–??
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L4 H ISTORY
• “Version 4” (X.2) API, 02
➜ portability, API improvements
• L4Ka::Pistachio, C++ (plus assembler “fast path”)
➜ x86, PPC-32, Itanium (Karlsruhe), 02–03➜ fastest ever kernel (36 cycles, NICTA/UNSW)
➜ MIPS64, Alpha (NICTA/UNSW) 03➜ same performance as V2 kernel (100 cycles single issue)
➜ ARM, PPC-64 (NICTA/UNSW), x86-64 (Karlsruhe), 03-04➜ UltraSPARC (NICTA/UNSW), 04–??
• Portable kernel:
➜ ≈ 3 person months for core functionality➜ 6–12 person months for full functionality & optimisation
cse/UNSW/NICTA COMP9242 2004/S2 W3 P12
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L4 FUTURE
• Security API
➜ in discussion/design stage (NICTA, Dresden)➜ to satisfy secure system requirements➜ kernel resource management➜ improved real-time features
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L4 FUTURE
• Security API
➜ in discussion/design stage (NICTA, Dresden)➜ to satisfy secure system requirements➜ kernel resource management➜ improved real-time features
• Time line:
➜ initial NICTA draft “seL4” expected for September 05➜ stable by February 06➜ possibly “executable spec” (Haskell) February 06➜ C version August 06
cse/UNSW/NICTA COMP9242 2004/S2 W3 P13
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L4K A ::P ISATCHIO : S IZE
• Source code:
➜ ≈ 10k loc architecture independent➜ ≈ 0.5–2k loc architecture specific
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L4K A ::P ISATCHIO : S IZE
• Source code:
➜ ≈ 10k loc architecture independent➜ ≈ 0.5–2k loc architecture specific
• Memory footprint kernel (no attempt to minimise yet):
➜ using gcc (poor code density on RISC/EPIC architectures)
Architecture Text Totalx86 52k 98kItanium 173k 417kARM 68k 180kPPC-32 41k 135kPPC-64 60k 205kMIPS-64 61k 100k
• Fast IPC cache footprint (typical):
➜ 10–14 I-cache lines➜ 8 D-cache lines
cse/UNSW/NICTA COMP9242 2004/S2 W3 P14
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SIZE COMPARISON
cse/UNSW/NICTA COMP9242 2004/S2 W3 P15
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PISTACHIO PERFORMANCE : IPC
port/ C++ optimisedArchitecture optimisation intra AS inter AS intra AS inter ASPentium-3 UKa 180 367 113 305
Small Spaces UKa 213Pentium-4 UKa 385 983 196 416Itanium 2 UKa/NICTA 508 508 36 36
cross CPU UKa 7419 7410 N/A N/AMIPS64 NICTA/UNSW 276 276 109 109
cross CPU NICTA/UNSW 3238 3238 690 690PowerPC-64 NICTA/UNSW 330 518 200‡ 200‡
Alpha 21264 NICTA/UNSW 440 642 ≈70† ≈70†
ARM/XScale NICTA/UNSW 250 11,400 120–140‡ 10,000‡
FASS NICTA/UNSW 340 340 120–140‡ 120–140‡
UltraSPARC NICTA/UNSW 100‡ 100‡
† “Version 2” assembler kernel‡ Guestimate!
cse/UNSW/NICTA COMP9242 2004/S2 W3 P16
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L4 A BSTRACTIONS AND MECHANISMS
THREE BASIC ABSTRACTIONS :
• Address spaces
• Threads
• Time
TWO BASIC MECHANISMS :
• Inter-process communication (IPC)
• Mapping
cse/UNSW/NICTA COMP9242 2004/S2 W3 P17
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L4 A BSTRACTIONS : A DDRESS SPACES
• Address space is unit of protection
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L4 A BSTRACTIONS : A DDRESS SPACES
• Address space is unit of protection
➜ initially empty➜ constructed recursively by mapping pages between address spaces
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L4 A BSTRACTIONS : A DDRESS SPACES
• Address space is unit of protection
➜ initially empty➜ constructed recursively by mapping pages between address spaces➜ ... staring from initial address space σ0
➜ σ0 is an identical map of physical memory
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L4 A BSTRACTIONS : A DDRESS SPACES
• Address space is unit of protection
➜ initially empty➜ constructed recursively by mapping pages between address spaces➜ ... staring from initial address space σ0
➜ σ0 is an identical map of physical memory
• Mechanism: 3 basic operations:
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L4 A BSTRACTIONS : A DDRESS SPACES
map
• Address space is unit of protection
➜ initially empty➜ constructed recursively by mapping pages between address spaces➜ ... staring from initial address space σ0
➜ σ0 is an identical map of physical memory
• Mechanism: 3 basic operations:
➜ map
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L4 A BSTRACTIONS : A DDRESS SPACES
map
• Address space is unit of protection
➜ initially empty➜ constructed recursively by mapping pages between address spaces➜ ... staring from initial address space σ0
➜ σ0 is an identical map of physical memory
• Mechanism: 3 basic operations:
➜ map
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L4 A BSTRACTIONS : A DDRESS SPACES
mapflush
• Address space is unit of protection
➜ initially empty➜ constructed recursively by mapping pages between address spaces➜ ... staring from initial address space σ0
➜ σ0 is an identical map of physical memory
• Mechanism: 3 basic operations:
➜ map➜ flush (unmap)
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L4 A BSTRACTIONS : A DDRESS SPACES
mapflush
• Address space is unit of protection
➜ initially empty➜ constructed recursively by mapping pages between address spaces➜ ... staring from initial address space σ0
➜ σ0 is an identical map of physical memory
• Mechanism: 3 basic operations:
➜ map➜ flush (unmap)
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L4 A BSTRACTIONS : A DDRESS SPACES
mapflushgrant
• Address space is unit of protection
➜ initially empty➜ constructed recursively by mapping pages between address spaces➜ ... staring from initial address space σ0
➜ σ0 is an identical map of physical memory
• Mechanism: 3 basic operations:
➜ map➜ flush (unmap)➜ grant
cse/UNSW/NICTA COMP9242 2004/S2 W3 P18
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L4 A BSTRACTIONS : A DDRESS SPACES
mapflushgrant
• Address space is unit of protection
➜ initially empty➜ constructed recursively by mapping pages between address spaces➜ ... staring from initial address space σ0
➜ σ0 is an identical map of physical memory
• Mechanism: 3 basic operations:
➜ map➜ flush (unmap)➜ grant
cse/UNSW/NICTA COMP9242 2004/S2 W3 P18
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L4 A BSTRACTIONS : THREADS
• Thread is unit of execution
➜ kernel-scheduled
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L4 A BSTRACTIONS : THREADS
• Thread is unit of execution
➜ kernel-scheduled
• Thread is addressable unit for IPC
➜ thread-ID is unique identifier
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L4 A BSTRACTIONS : THREADS
• Thread is unit of execution
➜ kernel-scheduled
• Thread is addressable unit for IPC
➜ thread-ID is unique identifier
• Threads managed by user-level servers
➜ creation, destruction, association with address space
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L4 A BSTRACTIONS : THREADS
• Thread is unit of execution
➜ kernel-scheduled
• Thread is addressable unit for IPC
➜ thread-ID is unique identifier
• Threads managed by user-level servers
➜ creation, destruction, association with address space
• Thread attributes:
➜ scheduling parameters (time slice, priority)➜ unique ID➜ address space➜ page-fault and exception handler
cse/UNSW/NICTA COMP9242 2004/S2 W3 P19
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L4 A BSTRACTIONS : T IME
• Used for IPC timeouts
➜ relative timeouts➜ absolute timeouts
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L4 A BSTRACTIONS : T IME
• Used for IPC timeouts
➜ relative timeouts➜ absolute timeouts
• Used for scheduling time slices
➜ thread has fixed-length time slice for preemption➜ time slices allocated from (finite or infinite) time quantum
➜ notification when exceeded
cse/UNSW/NICTA COMP9242 2004/S2 W3 P20
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L4 MECHANISM : IPC
• Synchronous (blocking) message-passing operation
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L4 MECHANISM : IPC
• Synchronous (blocking) message-passing operation
• Data copied directly from sender to receiver
➜ short messages passed in registers
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L4 MECHANISM : IPC
• Synchronous (blocking) message-passing operation
• Data copied directly from sender to receiver
➜ short messages passed in registers
• Optionally map or grant pages
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L4 MECHANISM : IPC
• Synchronous (blocking) message-passing operation
• Data copied directly from sender to receiver
➜ short messages passed in registers
• Optionally map or grant pages
• Timeouts to prevent indefinite blocking
➜ receive from nil thread used for timed sleep
cse/UNSW/NICTA COMP9242 2004/S2 W3 P21
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L4 CONCEPTS: ROOT TASK
• First task started at boot time
• Can perform privileged system calls
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L4 CONCEPTS: ROOT TASK
• First task started at boot time
• Can perform privileged system calls
• Controls access to resources
➜ threads➜ address spaces➜ physical memory
cse/UNSW/NICTA COMP9242 2004/S2 W3 P22
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L4 CONCEPTS: ROOT TASK
Physical Memory
Sigma 0
• First task started at boot time
• Can perform privileged system calls
• Controls access to resources
➜ threads➜ address spaces➜ physical memory
cse/UNSW/NICTA COMP9242 2004/S2 W3 P22
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L4 CONCEPTS: ROOT TASK
Physical Memory
Sigma 0
Root Task
• First task started at boot time
• Can perform privileged system calls
• Controls access to resources
➜ threads➜ address spaces➜ physical memory
cse/UNSW/NICTA COMP9242 2004/S2 W3 P22
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L4 CONCEPTS: ROOT TASK
Physical Memory
Sigma 0
Root Task Driver
• First task started at boot time
• Can perform privileged system calls
• Controls access to resources
➜ threads➜ address spaces➜ physical memory
cse/UNSW/NICTA COMP9242 2004/S2 W3 P22
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L4 CONCEPTS: ROOT TASK
Physical Memory
Sigma 0
Root Task Driver
Server Server Server Server
• First task started at boot time
• Can perform privileged system calls
• Controls access to resources
➜ threads➜ address spaces➜ physical memory
cse/UNSW/NICTA COMP9242 2004/S2 W3 P22
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L4 CONCEPTS: ROOT TASK
Physical Memory
Sigma 0
Root Task Driver
Server Server Server Server
Client Client
• First task started at boot time
• Can perform privileged system calls
• Controls access to resources
➜ threads➜ address spaces➜ physical memory
cse/UNSW/NICTA COMP9242 2004/S2 W3 P22
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L4 EXCEPTION HANDLING
• Interrupts
• Page faults
• Other exceptions
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L4 EXCEPTION HANDLING
• Interrupts
➜ modelled as hardware “thread” sending messages➜ received by registered (user-level) interrupt-handler thread➜ interrupt acknowledged when handler blocks on receive➜ timer interrupt handled in-kernel
• Page faults
• Other exceptions
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L4 EXCEPTION HANDLING
• Interrupts
➜ modelled as hardware “thread” sending messages➜ received by registered (user-level) interrupt-handler thread➜ interrupt acknowledged when handler blocks on receive➜ timer interrupt handled in-kernel
• Page faults
➜ kernel fakes IPC message from faulting thread to its pager➜ pager may reply with page mapping, intercepted by kernel
• Other exceptions
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L4 EXCEPTION HANDLING
• Interrupts
➜ modelled as hardware “thread” sending messages➜ received by registered (user-level) interrupt-handler thread➜ interrupt acknowledged when handler blocks on receive➜ timer interrupt handled in-kernel
• Page faults
➜ kernel fakes IPC message from faulting thread to its pager➜ pager may reply with page mapping, intercepted by kernel
• Other exceptions
➜ kernel fakes IPC message from exceptor thread to its exception handler➜ exception handler may reply with message specifying new IP, SP➜ can be signal handler, emulation code, stub for IPCing to server, ...
cse/UNSW/NICTA COMP9242 2004/S2 W3 P23
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FEATURES NOT IN KERNEL
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FEATURES NOT IN KERNEL
• System services (file system, network stack, ...)
➜ implemented by user-level servers
• VM management
➜ performed by (hierarchy) of user-level pagers
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FEATURES NOT IN KERNEL
• System services (file system, network stack, ...)
➜ implemented by user-level servers
• VM management
➜ performed by (hierarchy) of user-level pagers
• Device drivers
➜ user-level threads registered for interrupt IPC➜ map device registers
cse/UNSW/NICTA COMP9242 2004/S2 W3 P24
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REFERENCES
cse/UNSW/NICTA COMP9242 2004/S2 W3 P25