micro linear bicmos chip set - university of california...

Last edited by B. Nikolic, UC Berkeley August 30, 2005 1

Micro Linear/UC Berkeley Educational Lab Chip Set

Micro Linear BiCMOS Chip Setfor Undergraduate Laboratories in

Microelectronic Devices and Circuits

Roger T. HoweDept. of Electrical Engineering and Computer Sciences

University of California at Berkeley

Overview

A set of 6 chips has been designed at UC Berkeley in the Micro Linear 1.5 µm BiCMOS tile array technology. These chips contain individual devices and building-block analog and digital circuits in a modern BiCMOS process; they are the foundation for a one-semester junior-level laboratory at Berkeley. The laboratory supports a junior-level, core microelectronics course using the new text Microelectronics: An Integrated Approach, by R. T. Howe and C. G. Sodini (Prentice Hall, 1997). However, experiments based on the devices and circuits could be used in device physics courses or analog IC design courses. There are several circuits, such as two BiCMOS operational amplifiers on Lab Chip 6, which are not used in the Berkeley lab. The laboratory manual used at Berkeley is being placed in the public domain for the benefit of faculty, who are free to duplicate or build upon the experiments. The text of the experiments in various formats will be made available through the book’s web site at www.prenhall.com.

A brief history of this project is provided on p. 4, with acknowledgments to the many contributors at Micro Linear and at UC Berkeley since its inception in early 1992.

Description of the Lab Chips

All chips are packaged in 28-pin, 600 mil-wide DIP (Dual In-line Package) and have the same power (VCC - pin 28) and ground (VSS - pin 14) pins. For manufacturing purposes, Pins 1 and 2 on each chip are reserved for the die identification. The chip set has been carefully designed to meet customary electrostatic discharge (ESD) specifications; however, it is recommended to han-dle the chips with ground straps and proper precautions. The chips have proven to be robust over several semesters of use at UC Berkeley.



Lab Chip 1

The first chip supports experiments that introduce students to the concepts of IC fabrication tech-nology, layout, and sheet resistance. A common way to realize resistance on integrated circuit is to use the polysilicon layer. Two polysilicon resistors (RP1-RP2 and RP3-RP4) are included on this chip. RP1 corresponds to pin 21 on the pinout for Lab Chip 1 (see p. 12). Students are to measure the resistances of these two poly resistors and extract the sheet resistance. A diffused resistor is also included (RB1-RB2), with the well contact brought out as (RBW). The effect of the depletion width on the sheet resistance can be studied by varying the well voltage.

With the increasing size of silicon die, metal interconnects may contribute a significant amount of resistance. A long metal runner (pin 13 - pin 15) is included for students to gain an appreciation for the differences between metal and polysilicon sheet resistances. Capacitors are the other common IC passive component. In this technology, capacitors are realized by overlapping polysilicon and the diffusion layer, with gate oxide as the dielectric. A single capacitor (CP-CN) is designed in Lab Chip 1.

In order to support device characterization experiments, one or more devices of each transistor type (NMOS, PMOS, npn, and pnp) are included. These devices are located on Lab Chips 1 and 2. By placing transistors in series, three NMOS channel lengths are realized on Lab Chip 1 (1.5 µm for NMOS1, 3 µm for NMOS2, and 9 µm for NMOS3). Because the chip set is fabricated with 1.5 µm BiCMOS process, the shortest devices exhibit short-channel effect. Since this is an n-well pro-cess, the well for the NMOS transistors is connected to the substrate, which is hard-wired to ground. One lateral pnp is also included on the first chip for device characterization.

Lab Chip 2

Lab Chip 2 includes a diode and an RC delay line. There are three PMOS transistors (PMOS1,2, and 3 with channel lengths 1.5, 3, and 9 µm), which share a common n-well that is brought out as NWELL (pin 12). Two types of vertical npn transistors, one a medium power device, are included. CMOS inverters that exhibit different propagation delays are also designed in Lab Chip 2.

Lab Chip 3

A two-input NOR gate and two-input NAND gate are included in Lab Chip 3, along with a ring oscillator. The ring oscillator consists of 143 stages with buffers attached to the output to drive par-asitic and external capacitances. The free- running frequency is roughly 10-15 MHz. A a three-input dynamic logic gate is present on this chip, which is driven by an external clock.

Three single-stage amplifiers are included on this chip. The first two are common-emitter amplifi-ers (with and without emitter degeneration) that require an external resistor to supply collector cur-rent. By connecting a resistor between VCC and the CE-BIAS pin, the base-emitter voltage is set by an on-chip current mirror. In order to minimize the background required for this basic lab, stu-dents are not shown the details of the transistor bias. The third amplifier is a self-biased DC-cou-pled common-emitter with a current-source supply (active load). An external low-pass filter is needed to implement the feedback bias scheme.



Lab Chip 4

This chip has several MOS amplifiers. A self-biased common-source amplifier which is very simi-lar to the bipolar version on Lab Chip 3 is designed with MOS transistors. Due to the low transcon-ductance of the MOS transistors, we are able to place simple common-source amplifiers with current-source supplies (active loads) with both NMOS (CSAL pin labels) and PMOS (PCSAL pin labels) (both with NMOS and PMOS) on this chip. The gain can be found from the transfer func-tion using general lab test equipment.

Buffers are important in digital circuits for driving capacitive loads; they also play a key role in analog circuits. Lab Chip 4 includes both MOS (common drain/source follower) and bipolar (com-mon collector/emitter follower) forms with internal current mirror biasing. By connecting a bias resistor between VCC and the biasing pin (i.e., EF_BIAS or SF_BIAS), a bias current is set up for the amplifier. With properly chosen input DC value, the circuit can easily be biased in the linear range.

Cascoded amplifiers are very useful for their large gain-bandwidth product. A self-biased cascode amplifier (SBCASBJT pin labels) is implemented with bipolar devices on this chip. By applying the same low pass filter technique (connected between pins SBCASBJT_LP1 and _LP2) with DC feedback as used on Lab Chip 3, this circuit can be biased in the high-gain region.

In analog integrated-circuit design, currents sources based on mirrored devices play a central role. Several current sources are included in the Lab Chips, with SBSOURCE being a simple pnp cur-rent mirror implemented in Lab Chip 4.

Lab Chip 5

Two additional current sources are placed on this chip. CBSOURCE implements base-current compensation current source to demonstrate the effect of base current in pnp transistors. In order to achieve a high output resistance, a cascode PMOS current source (CASMSOURCE) is designed. An NMOS current sink (to VSS) and a cascoded npn current sink (CASBSINK) are included on Lab Chip 5. A “totem pole” voltage source (TOTEM) is included in this chip, which demonstrates that several voltages can be generated as a function of an external resistor.

A self-biased MOS cascode amplifier (SBCASMOS pin labels) complements the bipolar cascode on Lab Chip 4. This circuit requires an external low-pass filter to set a stable operating point using DC feedback.

Differential amplifiers are an essential component in analog IC design. A two-stage MOS differen-tial amplifier (MOSDP pins) using resistors to supply the drain currents is included in Lab Chip 5. An input can be applied either differentially or single-endedly to the input pads and outputs can be taken either at the output of the first stage or the second stage to observe the gain after each stage.

Lab Chip 6

This chip includes a bipolar differential amplifier with external resistor loads (BFTDPM) and a differential amplifier using emitter-degenerated bipolar input transistors (BJTDPE). Due to the high transconductance of the bipolar transistor, only a single-stage differential pair is designed for



the bipolar implementation. The differential amplifier affords an opportunity to measure the matching of nearby and distant npn bipolar transistors, by measuring the input offset voltage. BJTDM (M for matched=nearby input transistors) and BJTDU (U for unmatched=distant input transistor) are nominally identical circuits on Lab Chip 6 that designed to investigate this effect.

Two operational amplifiers that are designed for internal applications in VLSI systems are included on Lab Chip 6. OPAMP1 is a simple two-stage BiCMOS op amp that has a common-emitter second gain stage, in order to illustrate inter-stage loading effects. OPAMP2 has a com-mon-collector voltage buffer incorporated into the second gain stage in order to achieve higher gain. In order to minimize the systematic input offset voltage, the input-stage’s current mirror sup-ply is cascoded.

EE 105 Laboratory

This chip set is used in 13 one-week experiments in the laboratory accompanying EE 105 at UC Berkeley. The devices are characterized fully using HP 4155 A/B Parameter Analyzers. Not all of the circuits are measured due to time limitations. In particular, the op amps on Lab Chip 6 are not used in EE 105. The experience of using three revisions of the Lab Chips, starting in Fall 1993 has been positive. Students are able to study devices from a modern integrated circuit process. The Lab Chips include “bare,” accessible versions of the core IC analog and digital circuit building blocks that are introduced in the lectures. Therefore, the lab experiments serve to reinforce the lectures and vice versa.

A Brief History of the Project

EE 105 is intended to introduce the basic principles of device physics, and analog and digital inte-grated circuit design using both MOS and bipolar transistors. Since the focus in on chip-level rather than board- or system-level design, the laboratory experiments emphasize device and circuit phenomena and trade-offs that are encountered in the “internal” IC environment. It was clear in 1991 that the laboratory was not supporting the goals of the course. The experiments dated back to the 1970s and were typically focussed on board-level design using simple (and obsolete) ICs. Stu-dents were not impressed with the level of technology in the laboratory for this core course.

In order to achieve a more effective laboratory, it became clear that the only route was to design special ICs that contain MOSFET, bipolar transistor, and passive test devices, along with the inte-grated-circuit building-blocks that form the core of the circuit-design material in EE 105. In Janu-ary 1992, a meeting on this concept with Prof. Paul R. Gray, then the EECS Department Chairman at Berkeley, led to his initiating discussions with Dr. Jim McCreary, then Vice President of Engi-neering at Micro Linear, an IC company based in San Jose, California.

Micro Linear is a leader in high-performance mixed analog/digital ICs that achieve system-level integration for applications in the automotive, hard-disk drive, and telecommunications industries. One of Micro Linear’s innovations is the user-specified integrated circuit (USIC), which is based on “tile arrays” of uncommitted transistors and passive elements. By completing the fabrication process using two levels of metal interconnections, Micro Linear enables customers to design their own USICs with very rapid turn-around and very low risk of a design error. Micro Linear’s CA122 BiCMOS Tile Array chip was ideally suited for the kinds of experimental circuits needed for the



new EE 105 laboratory. Dr. McCreary authorized Micro Linear’s commitment of engineering and production resources to support the experimental project in April 1992.

During the summer of 1992, the EECS Department at Berkeley supported Chris Rudell, a graduate student in the IC group, in the development, design, simulation, and layout of the first generation of seven EE 105 lab chips. The Fall 1993 version of EE 105 was the first course using the new labo-ratory. After two semesters of experience with the first and second generations of the chip set, the laboratory manual was completely overhauled during the summer of 1994. George Chien, a Berke-ley IC group graduate student working at Micro Linear during that summer, designed the final set of 6 Lab Chips.

Acknowledgments

Many people have made significant contributions to the development of the Lab Chips. Micro Lin-ear’s corporate support for this project has been based on a commitment to improve undergraduate electrical engineering education. In addition to Jim McCreary, Dave Schwan provided major help with the layout of the initial version, Henry Young saw the second version through production and assembly, and Ken Fields was the contact and project advocate during the final revision. Carlos Laber supported the development and release of simplified SPICE models.At Berkeley, Chris Rudell spent countless hours --far beyond those paid by the Department -- on refining the concepts and implementing the designs for the first version of the chips. George Chien developed the final layout while spending a summer at Micro Linear.Over the past three years, several graduate and undergraduate students have helped to develop the experiments. The first lab manual was developed in 1993 by graduate students Chris Rudell and Srenik Mehta, along with undergraduates Albert Lo, Young Shin, Jim Young, Dennis Yee, and Wayne Yeung. During the summer of 1994, Wayne Yeung overhauled the lab manual to reflect the introduction of changes in the second version of the Lab Chips. The lab manual was contributed to by Frank Cheung, Rafael Cortina, Charles Hsiung, Ming Yang, Chi Yeung, and Wing Yeung during 1995-97. Frank Cheung also developed the simplified SPICE models for the active devices. During the 1998-99 academic year, Prof. W. G. Oldham introduced a lab on the HP 4155 and improved sev-eral of the experiments.



Micro Linear 1.5 µm BiCMOS Process

Micro Linear’s 1.5 µm, 5 Volt BiCMOS process is an advanced, state-of-the-art process technol-ogy optimized for exceptional analog and mixed signal performance. This technology is a 16 mask process with 62 total processing steps. It is currently a single polysilicon, double metal technology but has the capability for double polysilicon and triple metal interconnects.

This BiCMOS process is robust and reliable. It has a p+ buried layer to eliminate latch-up prob-lems common to CMOS, a DDD n+ source/drain to prevent hot electron formation, and 1st and 2nd metal planarization for high yield and reliability.

Precision passive components can be implemented easily in this process. Stable, low temperature-coefficient, low parasitic-capacitance resistors are made using a polysilicon deposition. Stable, low temperature-coefficient capacitors are made from a polysilicon gate/gate oxide/sinker collector sandwich. The npn transistors have low collector saturation resistance with the addition of a sinker and n+ buried layer. The MOS transistors exhibit good and repeatable performance due to the self-aligned polysilicon gate.

In order to minimize noise and leakage currents, the process has special enhancements over a con-ventional BiCMOS technology. It is capabile of implementing large-scale mixed-signal circuits in a space- and cost-efficient manner. The combination of high-performance bipolar and MOS devices allows for realization of a wide variety of analog and digital circuits. The npn bipolar tran-sistors have a transition frequency fT = 4 GHz. In combination with the L = 1.5 µm MOSFETs, mixed-signal circuits can be implemented with 300-500 MHz bandwidths. Switching speeds are less than 3 ns for CMOS logic and less than 500 ps for bipolar emitter-coupled logic.



SPICE Models

SPICE simulation is a very useful component of pre-lab exercises. The MOSFETs in the Micro Linear 1.5 µm BiCMOS technology exhibit short-channel effects that require higher-level SPICE models such as BSIM for accurate simulation. Reasonably accurate results can be obtained from the Level 1 SPICE model, if it is optimized for the operating conditions of the particular circuit. In the following list, each MOSFET has an “analog” and a “digital” model. Note that there are large discrepancies between the two for the NMOS transistor.

MOSFETs

NMOS Level 1 Analog SPICE Model (W/L) = (46.5 µm/1.5 µm)

VTO = 0.77 GAMMA = 0.80 KP = 86uPHI=0.74LAMBDA = 0.080RD = 0RS = 98CGDO = 4.1E-10 CGSO = 4.1E-10 CJ = 5.7E-4CJSW = 1.5E-10 MJ = 0.5 MJSW = 0.33 PB = 0.79

NMOS Level 1 Digital SPICE Model (W/L) = (46.5 µm/1.5 µm)

VTO = 3.2GAMMA = 0.22 KP = 230uPHI=0.62LAMBDA = 0.037RD = 7.5RS = 7.5CGDO = 4.1E-10 CGSO = 4.1E-10 CJ = 5.7E-4CJSW = 1.5E-10 MJ = 0.5 MJSW = 0.33 PB = 0.79



PMOS Level 1 Analog SPICE Model (W/L) = (46.5 µm/1.5 µm)

VTO = -0.66 GAMMA = 0.42 KP = 26uPHI=0.77LAMBDA = 0.13RD = 49RS = 100CGDO = 5.6E-10 CGSO = 5.6E-10 CJ = 3.9E-4CJSW = 1.2E-10 MJ = 0.5 MJSW = 0.33 PB = 0.87

PMOS Level 1 Digital SPICE Model (W/L) = (46.5 µm/1.5 µm)

VTO = -1.2GAMMA = 0.53 KP = 24uPHI=0.5LAMBDA = 0.12RD = 0RS = 26CGDO = 5.6E-10 CGSO = 5.6E-10 CJ = 3.9E-4CJSW = 1.2E-10 MJ = 0.5 MJSW = 0.33 PB = 0.87



Bipolar Transistors

3505S (similar to 3500, 3501) vertical npn

.model 3505S NPN IS=5.65E-17 RB=465 RE=0.495 RC=41.5 CJE=0.555p+CJC=0.155p CJS=0.205p BF=94.5 VAF=50.0 BR=0.720 VAR=4.40 VJE=0.960+MJE=0.330 VJC=0.730 MJC=0.520 VJS=0.450 MJS=0.330 TF=39.0p TR=1.00n

3505AS Medium Power npn

.model 3505AS NPN IS=3.10E=17 RB=64.0 RE=0.100 RC=27.4 CJE=2.65p+CJC=0.445p CJS=0.360p BF=98.0 VAF=50.0 BR=7.22 VAR=4.40 VJE=0.960+MJE=0.330 VJC=0.730 MJC=0.520 VJS=0.450 MJS=0.330 TF=39.0p TR=1.00n

3516S lateral pnp

.model 3516S PNP IS=1.54E-17 BF=12.5 VAF=29.5 BR=50.0 VAR=29.5+RB=220 RE=4.00 RC=800 CJE=0.133p VJE=0.900 MJE=0.200 CJC=0.043p+VJC=0.65 MJC=0.5 TF=0.5n



Lab Chip 1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

I.D. pin 1

I.D. pin 2

NMOS1D

NMOS1G

NMOS1S

NMOS2D

NMOS2G

NMOS2S

NMOS3D

NMOS3G

NMOS3S

no connection

Metal Runner I

VSS

VCC

PNPC

PNPB

PNPE

RP4

RP3

RP2

RP1

RBW

CN

CP

RB2

RB1

Metal Runner II



Lab Chip 2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

I.D. pin 1

I.D. pin 2

PMOS1D

PMOS1G

PMOS1S

PMOS2D

PMOS2G

PMOS2S

PMOS3D

PMOS3G

PMOS3S

NWELL

No connection

VSS

VCC

RC_OUT

RC_IN

DIODE

INV2_OUT

INV2_IN

INV1_OUT

INV1_IN

NPN1C

NPN1B

NPN1E

NPN2C

NPN2B

NPN2E



Lab Chip 3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

I.D. pin 1

I.D. pin 2

NOR_B

NOR_A

NOR_OUT

NAND_A

NAND_B

NAND_OUT

RINGOSC_OUT

RINGOSC_VCC

DYNAMIC_C

DYNAMIC_A

DYNAMIC_B

VSS

VCC

CE_BIAS

CE_IN

CE_OUT

CED_BIAS

CED_OUT

CED_IN

SBCE_LP2

SBCE_LP1

SBCE_OUT

SBCE_IN

SBCE_BIAS

DYNAMIC_OUT

DYNAMIC_PHI



Lab Chip 4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

I.D. pin 1

I.D. pin 2

SBCS_LP1

SBCS_LP2

SBCS_OUT

SBCS_BIAS

SBCS_IN

CSAL_IN

CSAL_OUT

CSAL_BIAS

PCSAL_BIAS

PCSAL_OUT

PCSAL_IN

VSS

VCC

SBSOURCE_BIAS

SBSOURCE_OUT

EF_BIAS

EF_OUT

EF_IN

SF_BIAS

SF_OUT

SF_IN

SBCASBJT_IN

SBCASBJT_LP1

SBCASBJT_OUT

SBCASBJT_BIAS

SBCASBJT_LP2



Lab Chip 5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

I.D. pin 1

I.D. pin 2

SBCASMOS_LP2

SBCASMOS_LP1

SBCASMOS_OUT

SBCASMOS_BIAS

SBCASMOS_IN

SMSINK_OUT

SMSINK_BIAS

CASMSOURCE_BIAS

CASMSOURCE_OUT

MOSDP_IN1

MOSDP_IN2

VSS

VCC

CBSOURCE_OUT

CBSOURCE_BIAS

CASBSINK_OUT

CASBSINK_BIAS

TOTEM1

TOTEM3

TOTEM2

MOSDP_OUT11

MOSDP_OUT21

MOSDP_OUT22

MOSDP_BIAS2

MOSDP_BIAS1

MOSDP_OUT12



Lab Chip 6

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

I.D. pin 1

I.D. pin 2

OPAMP2_BIAS

No connection

OPAMP2_OUT

OPAMP2_IN2

OPAMP2_IN1

OPAMP1_IN1

OPAMP1_IN2

OPAMP1_OUT

OPAMP1_BIAS

BJTDPDE_OUT1

BJTDPDE_IN2

VSS

VCC

BJTDPM_BIAS

BJTDPM_OUT2

BJTDPM_IN1

BJTDPM_IN2

BJTDPM_OUT1

BJTDPUM_BIAS

BJTDPUM_OUT2

BJTDPUM_IN2

BJTDPUM_OUT1

BJTDPUM_IN1

BJTDPDE_BIAS

BJTDPDE_OUT2

BJTDPDE_IN1



Component List

MicroLinear Lab Chips 1-6

Resistors (all 1/4 W)

100 Ω500 Ω1 kΩ (2)2 kΩ (2)2.5 kΩ (2)3 kΩ (2)5 kΩ10 kΩ (2)16 kΩ 20 kΩ (2)50 kΩ (2)90 kΩ 100 kΩ (2)112.5 kΩ (6)250 kΩ (2)1 MΩ (2)5 MΩ

Potentiometers

10 kΩ (4)

Capacitors

1 pF (5)3.6 pF1 nF10 nF100 nF1 µF10 µF (2)

Integrated Circuits

741 op amp

micro linear bicmos chip set - university of california...

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