micro controller m 8051

8/2/2019 Micro Controller m 8051

1/95

Microcontrollers

Specially designed microprocessors

It is small on chip computer

Highly integrated chipincludes all or most parts needed for controller

A typical microcontroller has:

bit manipulation

easy and direct access to I/O

quick and efficient interrupt processing

Microcontroller drastically reduces design cost


2/95

Worldwide Microcontroller shipments

- in millions of dollars -

'95 '96 '97 '98 '99 00

4-bit 1826 1849 1881 1856 1816 17578-bit 5634 6553 7529 8423 9219 9715

16-bit 1170 1628 2191 2969 3678 4405

Source

WSTS & ICE


3/95


- in millions -

WSTS & ICESource

'95 '96 '97 '98 '99 00

4-bit 1100 1100 1096 1064 1025 9708-bit 1803 2123 2374 2556 2681 2700

16-bit 157 227 313 419 501 585


4/95

Applications

Appliances(microwave oven, refrigerators, television and VCRs, stereos)

Computers and computer equipment

(laser printers, modems, disk drives) Automobiles

(engine control, diagnostics, climate control),

Environmental control(greenhouse, factory, home)

Instrumentation

Aerospace

Robotics, etc...


5/95

Flavors

4, 8, 16, or 32 bit microcontrollers

specialized processors include features specific for

communications,

keyboard handling,

signal processing,

video processing, and other tasks.


6/95

Popular Microcontrollers

8048 (Intel)

8051 (Intel and others)

80c196 (MCS-96)

80186,80188 (Intel)

80386 EX (Intel)

65C02/W65C816S/W65C134S (Western Design Center)

MC14500 (Motorola)

Part 1


7/95


68HC05 (Motorola)

68HC11 (Motorola and Toshiba)

683xx (Motorola)

PIC (MicroChip)

COP400 Family (National Semiconductor)

COP800 Family (National Semiconductor)

HPC Family (National Semiconductor)

Project Piranha (National Semiconductor)

Part 2


8/95


Z8 (Zilog)

HD64180 (Hitachi)

TMS370 (Texas Instruments)

1802 (RCA)

MuP21 (Forth chip)

F21 (Next generation Forth chip)

Part 3


9/95

Programming Microcontrollers

Machine/Assembly language

Interpreters (Java, ...)

Compilers (C, C++, ...)

Fuzzy Logic and Neural Networks

Part 1


10/95

Development Tools

Simulators

Resident Debuggers

Emulators

Part 1


11/95

Choosing microcontoller

Technical support

Development tools

Documentation

Purchasing more devices at one manufacturer(A/D, memory, etc.)

Additional features(EEPROM, FLASH, LCD driver, etc.)


12/95

Microcontrollers

Basic parts are:

Central Processing Unit

RAM

EPROM/PROM/ROM or

FLASH Memory

I/O serial or/and parallel

timers

interrupt controller

Optional parts are:

Watch Dog Timer

AD Converter

LCD driver

etc.

interruptcontrol

externalinerrupts

CPU

OSC

ROM

buscontrol

4 I/Oports

serialport

RAM

timer 0

timer 1 counterinputs

P0 P2 P1 P3

address/data

TxD RxD


13/95

Intel 8051

A typical 8051 contains:

CPU with Boolean processor

5 or 6 interrupts:

2 external, 2 priority levels 2 or 3 16-bit timer/counters

programmable full-duplexserial port

32 I/O lines (four 8-bit ports)

RAM

ROM/EPROM in some models

PCH

PCL DPL

DPH P2 LATCH

PORT2

TMP2 TMP1

AALUROM

RAMBUFFER

128x8

RAMRAR

SENSEAMPS

4Kx8

ROM

ALU

B

IR

PLA

CONTROLPSW SP

SCONP0 LATCH TCON IE P3 LATCH

PORT0 SBUF(REC)

SBUF(XMIT)

SERIALPORT

TMOD

TL0

TH0

TL1

TH1

IP

INTERRUPTCONTROL

PORT3

TIMERCONTROL

P2 LATCH

PORT2

P0 LATCH

INTERNAL

BUS


14/95

Intel 8051: Pin Description

VSS - Ground: 0V

VCC - Power Supply

P0.0-P0.7 - Port 0

Open drain,bi-directional I/O port

Pins that have 1s written tothem float and can be usedas high-impedance inputs

Multiplexed low-orderaddress and data bus duringaccesses to external programand data memory

Part 1

PORT0

PORT1

PORT2

ADDRESS ANDDATA BUS

ADDRESS BUS

PORT3

RxD

TxD

INT0

INT1

T0T1

WR

RD

XTAL1

XTAL2

VCC VSS

SECONDAR

YFUNCTIONS

RST

PSEN

ALE/PROG

EA/Vpp


15/95


P2.0-P2.7 - Port 2

Bi-directional I/O portwith internal pull-ups

Pins that have 1s written to

them float and can be usedas high-impedance inputs.

Port 2 emits high-orderaddress byte duringaccesses to external programand data memory

P3.0-P3.7 - Port 3 Bi-directional I/O port

with internal pull-ups

Pins that have 1s written tothem float and can be usedas high-impedance inputs.

Part 2

Port 3 serves thespecial features:

RxD - Serial input port

TxD - Serial output port

INT0 - External interrupt

INT1 - External interrupt

T0 - Timer 0 external input

T1 - Timer 1 external input

WR - External data memory

write strobe RD - External data memory

read strobe


16/95


RST - Reset

A high on this pinfor two machine cyclesresets the devices

ALE - Address Latch Enable Output pulse for latching

the low byte of addressduring an access to externalmemory

PSEN - Program Store Enable

Read strobe to externalprogram memory

Part 3

EA - External Access Enable

EA must be externally heldlow to enable device to fetchcode from external memory

locations. XTAL1 - Crystal 1

Input to the invertingoscillator amplifier andinput to internal clockgenerator circuits

XTAL2 - Crystal 2 Output from the inverting

oscillator amplifier


17/95

Part 1

Intel 8051: Pin Configurations

Dual In-Line Package

Plastic Lead Chip Carrier

Plastic Quad Flat Pack

2

1

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

39

40

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6P1.7

RST

RxD/P3.0TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4T1/P3.5

WR/P3.6

RD/P3.7

XTAL2

XTAL1

Vss

Vcc

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.5/AD5P0.6/AD6

P0.6/AD6

EA

ALE

PSEN

P2.7/A15

P2.6/A14P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P2.0/A8


18/95

Intel 8051: Pin Configurations

Part 2

PQFP

6 1 40

39

29

2818

17

7

1 NIC2 P1.0

3 P1.14 P1.2

5 P1.36 P1.47 P1.5

8 P1.69 P1.710 RST11 P3.0/RxD12 NIC13 P3.1/TxD14 P3.2/INT015 P3.3/INT1

16 P3.4/T017 P3.5/T1

18 P3.6/WR19 P3.4/RD

20 XTAL221 XTAL122 VSS

23 NIC24 P2.0/A825 P2.1/A926 P2.2/A1027 P2.3/A1128 P2.4/A1229 P2.5/A1330 P2.6/A14

31 P2.7/A1532 PSEN

33 ALE34 NIC

35 EA36 P0.7/AD737 P0.6/AD6

38 P0.5/AD539 P0.4/AD440 P0.3/AD341 P0.2/AD242 P0.1/AD143 P0.0/AD044 VCC

PLCC

44 34

33

23

2212

11

1

1 P1.52 P1.63 P1.74 RST

5 P3.0/RxD6 NIC7 P3.1/TxD8 P3.2/INT09 P3.3/INT110 P3.4/T011 P3.5/T112 P3.6/WR13 P3.4/RD14 XTAL2

15 XTAL1

16 VSS17 NIC18 P2.0/A819 P2.1/A9

20 P2.2/A1021 P2.3/A1122 P2.4/A1223 P2.5/A1324 P2.6/A1425 P2.7/A1526 PSEN27 ALE28 NIC29 EA

30 P0.7/AD7

31 P0.6/AD632 P0.5/AD533 P0.4/AD434 P0.3/AD3

35 P0.2/AD236 P0.1/AD137 P0.0/AD038 VCC39 NIC40 P1.041 P1.142 P1.243 P1.344 P1.4


19/95

Intel 8051: CPU

Primary elements are:

eight bit ALUwith associated registersA, B, PSW and SP

sixteen-bitProgram Counter (PC)

Data Pointer registers

Part 1

PCH

PCL DPL

DPH P2 LATCH

PORT2

TMP2 TMP1

AALU

ROM

RAM

BUFFER

128x8RAM

RAR

SENSE

AMPS

4Kx8ROM

ALU

B

IR

PLA

CONTROLPSW SP

SCONP0 LATCH TCON IE P3 LATCH

PORT0 SBUF(REC)

SBUF(XMIT)

SERIALPORT

TMOD

TL0

TH0

TL1

TH1

IP

INTERRUPTCONTROL

PORT3

TIMERCONTROL

P2 LATCH

PORT2

P0 LATCH

INTERN

ALBUS


20/95

Intel 8051: CPU

The ALU can manipulate one-bit as well as eight-bit data types

This features makes the 8051 especially well suitedfor controller-type applications

A total of 51 separated operations

move and manipulate three data types: Boolean (1-bit)

Byte (8-bit)

Address (16-bit)

Part 2


21/95

Intel 8051: CPU

Instruction types:

Arithmetic Operations

Logic Operations for Byte Variables

Data Transfer Instructions

Boolean Variable Manipulation

Program Branching and Machine Control

Part 3


22/95

Intel 8051: CPU

There are eleven addressing modes:

seven for data

four for program sequence control

Most operations allow several addressing modes,bringing total number of instructions to 111,encompassing 255 of the 256 possible 8-bit instruction opcodes

8051 instruction set fares well at bothreal-time control and data intensive algorithms

Part 4


23/95

Part 1

Intel 8051: Memory Organization

Program memory is separate distinct from data memory

Each memory type has a different addressing mechanism,different control signals, and a different functions

Architecture supports several distinct physical address spaces

functionally separated at the hardware level: On - chip program memory

On - chip data memory

Off - chip program memory

Off - chip data memory

On chip special function registers


24/95

Part 2


Program (Code) memory

Holds the actual 8051 program that is to be run

Limited to 64K may be found on-chipas ROM or EPROM may be stored completely off-chipin

an external ROM or an external EPROM

Flash RAM is also another popular method of storing a program

Various combinations of these memory types may be used(e.g. 4 K on-chip and 64 KB off-chip)


25/95

Part 3


External RAM

External RAM is any random access memory which is found off-chip

External RAM is slower

To increment an Internal RAM location by 1

requires only 1 instruction and 1 instruction cycle To increment a 1-byte value stored in External RAM

requires 4 instructions and 7 instruction cycles

While Internal RAM is limited to 128 bytes (256 bytes with an 8052),the 8051 supports External RAM up to 64K


26/95

Part 4


On-chip memory

Two types:

Internal RAM; and

Special Function Register (SFR) memory

Internal RAM is on-chipso it is the fastest RAM available Internal RAM is volatile, when the 8051 is reset this memory is cleared

Special Function Registers (SFRs) are areas of memory thatcontrol specific functionality of the 8051 processor


27/95

Part 1

Intel 8051: Memory Access

PORT 2 : High byte of addressheld for the duration ofread or write cycle

PORT 0 : time multiplexed

low byte of address with data byte

Signal ALE: used to capture theaddress byte into an external latch

8051

LATCH

AD0-AD7

PORT2

PORT0

PSENRDWR

A8-A15

A0-A7

A8-A15

A0-A7

D0-D7

A0-A7

A8-A15

ALECSOE

CSRDWRLE

"0""0"

StaticRAM

ROM

64 Kbytes - Program memory (external)64 Kbytes - Data Memory

EA


28/95

Part 2

Intel 8051: Memory Access

ALE

P0

P2A8-A15

A0-A7

A8-A15

datain

P1 P1 P1 P1 P1 P1 P2P2P2P2P2P2

STAGE 4 STAGE 5 STAGE 6 STAGE 1 STAGE 2 STAGE 3

XTAL1

RD

FLOAT FLOAT

P1 P1 P1 P1 P1 P1 P2P2P2P2P2P2

STAGE 1 STAGE 2 STAGE 3 STAGE 4 STAGE 5 STAGE 6

XTAL1

ALE

PSEN

P2A8-A15A8-A15

P0A0-A7 A0-A7

INS.IN

INS.IN

INS.IN


29/95

Part 1

Intel 8051: Program Memory

Up to 64K of Program Memory

PSEN: read strobefor all external program fetches

PSEN: not activated forinternal program fetches

Depending on EA pinlowest bytes can be eitherin the on-chip ROM or in an external ROM

EA = 0 EA = 1

PSEN

0x0000

EXTERNAL

EXTERNAL

0xFFFF

PROGRAM MEMORY

2


30/95

Part 2


Boot address - 0x0000

Each interrupt is assigneda fixed location in Program Memory

If interrupt is not going to used,its service location is available asgeneral purpose Program Memory

RESET 0x0000

0x0003

0x0008

0x0013

0x0018

0x0023

0x0028

INTERRPUTLOCATIONS

8 BYTES

LOWER PART OF PROGRAM MEMORY

P 3


31/95

Part 3


Port 0 and Port 2 are dedicatedto bus functions duringexternal Program Memory fetches

8051

LATCH

AD0-AD7

PORT0

PSEN

EROM

INSTR

A0-A7

ALE

OE

LE

EA

PORT2 A8-A15

ADDR

P 1


32/95

Part 1

Intel 8051: Data Memory

Up to 64K Data Memory

Access to Data memory useRD or WR to strobe the memory

0x0000

EXTERNAL

0xFFFF

INTERNAL

0xFF

0x00

EXTERNAL

0xFFFF

RD WR

DATA MEMORY

P 2


33/95

Part 2


Internal Memory Addressesare one byte wide -128 bytes address space(256 - Intel 8052)

Direct addressing higher then 0x7Faccess one memory space,indirect addressing higher then 0x7Faccess a different memory space

Upper 128 and SFR space

occupying same block of addresses,although they arephysically separate entities

INTERNAL

0xFF

0x00

0x7F

ACCESSIBLE

BY INDIRECTADDRESSING

ONLY

ACCESSIBLE

BY DIRECT

AND INDIRECT

ADDRESSING

ACCESSIBLE

BY DIRECTADDRESSING

ONLY

SPECIAL

FUNCTION

REGISTERS

PORTS

STATUS BITS

CONTOL BITSTIMER REGISTERS

STACK POINTER

ACCUMULATOR

(ETC.)

LOWER

128

UPPER128

P 3


34/95

Part 3


The lowest 32 bytes are groupedinto 4 banks of 8 registers

Program instructions call outthese registers R0 through R7

Two bits in the PSWselects register bank

Register instructions are shorter

The next 16 bytes form ablock of bit-addressable space

LOWER 128 BYTES OF

INTERNAL RAM

0x07

0x00

0x0F

0x08

0x17

0x10

0x1F

0x18

0x2F

0x20

0x7F

00

01

10

11

BANK SELECT BITS

IN PSW

4 BANKS OF8 REGISTERS

R0-R7

BIT ADDRESSABLE SPACE

(BIT ADDRESSES 0-7F)

RESET VALUE OF

STACK POINTER

P t 1


35/95

Part 1

Intel 8051: SFR

SFRs are accessed as if they were normal Internal RAM

SFR registers exist in the address range of 80h through FFh

Each SFR has an address and a name

P t 2


36/95

Part 2

Intel 8051: SFR

0 1 2 3 4 5 6 7

F8 FF

F0 B F7

E8 EF

E0 ACC E7

D8 DFD0 PSW D7

C8 CF

C0 C7

B8 IP BF

B0 P3 B7

A8 IE AF

A0 P2 A7

98 SCON SBUF 9F

90 T1 97

88 TCON TMOD TL0 TL1 TH0 TH1 8F

80 T0 SP DPL DPH PCON 87

P t 3


37/95

Part 3

Intel 8051: SFR

Accumulator (A)

Accumulator register

B Register (B)

Used during multiply anddivide operations

PSW

Contains program statusinformation

Stack Pointer (SP)

Eight bits wide Stack may reside anywhere

in on chip RAM

The Stack Pointer isinitialized on 0x07after a reset, and this causesstack to begin at location0x08

Data Pointer(DPTR) Consist high byte (DPH) and

low byte (DPL)

It may be manipulated as a16-bit register or as two

independent 8-bit registers

P t 4


38/95

Part 4

Intel 8051: SFR

Ports 0 to 3 (P0, P1, P2, P4) Latches of Port 0 to 3,

respectively

Serial Data Buffer (SDBF)

It is actually two separatedregisters: receive andtransmit buffer registers

When data is moved to SBUFit goes to the transmit buffer

When data is moved from

SBUF it comes from thereceive buffer

Timer Registers (T1, T0)

(TH1, TL1) (TH0, TL0)Counting Registers forTimer/Counter 1 and 0

Control Registers IP: Interrupt priority

IE: Interrupt enable

TMOD Timer/Counter mode

TCON Timer/Counter control

PCON Power control


39/95

Intel 8051: PSW

Auxiliary Carry flag is used for BCD operations

Flag 0 is available to user for general purposes

The contest of (RS1, RS2) enable working register banks as follows:00 - Bank 0 [0x00-0x07], 01 - Bank 1 [0x08-0x0f],10 - Bank 2 [ 0x10-0x17], 11 - Bank 3 [0x18-0x1F]

CY AC F0 RS1 RS0 OV - P

7 6 5 4 3 2 1 0

PSW

Carry flag

Auxiliary Carry flag

Flag 0Registar Bank

Select bit 1

Registar BankSelect bit 1

Ove rflow flag

Parity flag


40/95

Intel 8051: CPU Timing

The internal clock generator definesthe sequence of states that make up a machine cycle

A machine cycle consists of 6 states, numbered S1 through S6 Each state time lasts for two oscillator periods

Each state is then divided into a Phase 1 and Phase 2 half

S5 S6 S1 S2 S3 S4

ALE

S5 S6 S1 S2 S3 S4 S5

P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

Part 1


41/95

Part 1

Intel 8051: Port Structures

Pseudo bi-directionalI/O port structure

On Port0 R2 is disabledexcept during bus operations

(open-collector output) The address latch bit is updated by

direct addressing instructions

The value read is OR-tied functionof Q1 and the external device

To use a pin for inputlatch must be set

D

Q

QSET

CLR

ENB

ENB

R1 R2

I/O

PIN

+5V +5VREAD/MODIFY/

WRITE

READ

INPUTBUFFER

Q2

Q1

BUS CYCLE

TIMING

WRITE PULSE

INTERNAL BUS


42/95

Intel 8051: Port Interfacing

The output buffers of Ports 0, 1, 2 and 3can each drive 4 LS TTL inputs

Can be driven by open-collector and open-drain outputs

0-to-1 transitions will not be fast since

there is little current pulling the pin up

Port 0 output buffers can each drive 8 LS TTL inputs(external bus mode)

As port pins PORT 0 requires external pull-upsto be able to drive any inputs bit


43/95

Intel 8051: Special Peripheral Functions

There are few special needscommon among control-oriented computer systems:

keeping tracks of elapsed time

maintaining a count of signal transitions

measuring the precise width of input pulses

communicating with other systems

closely monitoring asynchronous external events

Part 1


44/95

Intel 8051: Timers/Counters

Two 16-bit Timer/Counter registers

Timer: Register is incremented every machine cycle(1 machine cycle = 12 oscillator periods)

Counter: Register is incremented in response to

1-to-0 transition at its corresponding external input pin (T0, T1)

External input is sampled at S5P2 of every machine cycle

When the samples show high in one cycle and low in the next,the count is incremented

The new count value is appears in S3P1of the following detection cycle

Max count rate is 1/24 of oscillator frequency

TMOD - Timer/Counter mode register

TCON - Timer/Counter control register

Part 1

Part 2


45/95


GATE: Gating control when set

C/T: Counter or Timer Selector

M1 M0:

00: 8-bit Timer/Counter with 5-bitprescaler

01: 16-bit Timer/Counter

10: 8-bit auto reloadTimer/Counter

11: (Timer0)

TL0 is 8-bit Timer/Countercontrolled by Timer0 control bitsTH0 is 8-bit timer only controlledby Timer1 control bits

11: (Timer1) Timer/Counter isstopped

Part 2

TIMER0

TIMER1

GATE

C/T

M1M0

Part 3


46/95


TF: Overflow flag

Set by hardware on Timer/Counter overflow

Cleared by hardware when processor vectors to interrupt routine

TR: Run control bit

Set/Cleared by software to turn Timer/Counter on/off

IE: Interrupt Edge flag

Set by hardware when external interrupt edge detected

Cleared when interrupt processed

IT: Interrupt Type control bit

Set/Cleared by software to specifyfalling edge/low level triggered external interrupts

Part 3

7 6 5 4 3 2 1 0

TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Part 4


47/95


Part 4

OSC 1/12

TL1(5 bits)

TH1(8 bits)

TF1

INT1 PIN

GATE

TR1

T1 PIN

INTERRUPT

MODE 0

Part 5


48/95


Part 5

OSC 1/12

TL1(8 bits)

TH1(8 bits)

TF1

INT1 PIN

GATE

TR1

T1 PIN

INTERRUPT

MODE 1

C/T=0

C/T=1

Part 6


49/95


Part 6

OSC 1/12

TL1(8 bits)

TH1(8 bits)

TF1

INT1 PIN

GATE

TR1

T1 PIN

INTERRUPT

MODE 2

RELOAD

Part 7


50/95


Part 7

OSC 1/12

TL0(8 bits)

TH0(8 bits)

TF0

INT0 PIN

GATE

TR0

T0 PIN

INTERRUPT

MODE 3

C/T=0

C/T=1

TF1 INTERRUPT1/12 fosc

TR1

Part 1


51/95

Intel 8051: Serial Port Interface

Full-duplex

Serial port receive and transmit registersare both accessed at Special Function Register SBUF

Writing to SBUF loads the transmit register

Reading from SBUF accesses a physically separated receive register

Four modes of operation

In all four modes transmission is initiated byany instruction that uses SBUF as destination register

Reception is initiated in Mode 0 by condition RI=0 and REN=1In other modes by the incoming start bit if REN=1

SCON - Serial Port Control Register

Part 1

Part 2


52/95


SM0 SM1: 00: Mode 0, Shift register, fosc//12

01: Mode 1, 8-bit UART, variable

10: Mode 2, 9-bit UART, fosc//32 or fosc//64

11: Mode 3, 9-bit UART, variable

SM2: Enables multiprocessor features in Mode 2 and Mode 3 When the stop bit is received,

the interrupt will be activated only if RB8=1 (9th bit =1)

REN: Enables serial reception

Set/Clear by software

Part 2

7 6 5 4 3 2 1 0

SCON SM0 SM1 SM0 REN TB8 RB8 TI RI

Part 3


53/95


TB8: 9th data bit that will be transmitted in Mode2 and Mode3 Set/Clear by software

RB8: 9th data bit that was received in Mode2 and Mode3In Mode 1, if SM2=0, is the stop bit that was received

TI: Transmit interrupt flag

Set by hardware. Must be cleared by software RI: Receive interrupt flag

Set by hardware. Must be cleared by software

Part 3

7 6 5 4 3 2 1 0

SCON SM0 SM1 SM0 REN TB8 RB8 TI RI

Part 4


54/95


MODE 0:

Serial data enters and exits through RXD

TXD outputs shift clock

8 bits are transmitted/received: 8 data bits (LSB first)

The baud rate is fixed at 1/12 oscillator frequency

MODE 1:

Serial data enters through RXD, exits through TXD

10 bits are transmitted/received:start bit(0), 8 data bits (LSB first), stop bit(1)

On receive the stop bit goes into RB8 in SCON register The baud rate is variable

Part 4

Part 5


55/95


MODE 2:

Serial data enters through RXD, exits through TXD

11 bits are transmitted/received:start bit(0), 8 data bits (LSB first), a programmable 9th bit, stop bit(1)

On transmit, the 9th bit is TB8 in SCON register On receive, the 9th bit goes into RB8 in SCON register

The baud rate is programmable to either1/32 or 1/64 the oscillator frequency

MODE 3:

Same as MODE 2 in all respects except baud rate

The baud rate is variable

Part 5

Part 6


56/95


Mode 0 Baud Rate = Oscillator frequency/12

Mode 2 Baud Rate =[(2SMOD)/64]*Oscillator frequency

SMOD is bit in Special Function Register PCON

Mode 1 and Mode3 baud rate is

determined by Timer 1 overflow rate

Mode 1,3 Baud Rate =[(2SMOD)/32]* Timer 1 Overflow Rate

Timer mode, auto-reload :Timer Overflow Rate=Oscillator frequency/[12*(256-TH1)]

Part 6

Part 7


57/95


Part 7

Timer1BaudRate

fosc SMOD

C/T ModeReloadValue

62.5 K 12 MHz 1 0 2 FF19.2 K 11.059 MHz 1 0 2 FD

9.6 K 11.059 MHz 0 0 2 FD

4.8 K 11.059 MHz 0 0 2 FA

2.4 K 11.059 MHz 0 0 2 F4

1.2 K 11.059 MHz 0 0 2 E8135.5 11.059 MHz 0 0 2 1D

110 6 MHz 0 0 2 72

110 12 MHz 0 0 1 FEEB

Part 1


58/95

Intel 8051: Interrupt Control

EA: Enable/Disable all interrupts If EA=0 no interrupts will be acknowledged

If EA=1 each interrupt source is individually enabled/disbled

ES: Serial Port interrupt enable bit

ET: Timer interrupt enabled bit

EX: External interrupt enable bit

7 6 5 4 3 2 1 0

IE EA - - ES ET! EX1 ET0 EX0

Part 2


59/95


5 interrupt sources

2 external(INT0, INT1)

2 timers(TF0, TF1)

Serial Port(RI or TI)

TF0

IE0

IT0=0

IT0=1

INT0

IE1

IT1=0

IT1=1

INT1

TF1

RI

TI

INTERRUPTSOURCE

Part 3


60/95


External interrupts

Level-activated or transition-activateddepending on bits IT0, IT1 in register TCON

The flags that generate these interrupts areIE0, IE1 in TCON

Cleared by hardware if the interrupt was transition-activated

if the interrupt was level-activated,external source controls request bits

If external interrupt is level-activated,the external source has to hold request active,until the requested interrupt is actually generated.

External source has to deactivate the request

before interrupt service is completed,or else another interrupt will be generated

IE0

IT0=0

IT0=1

INT0

Part 4


61/95


Timer interrupts

Interrupts are generated by TF0 and TF1 in register TCON

When a timer interrupt is generated, the flag that generated it iscleared by hardware when the service routine is vectored to

Serial Port interrupt generated by the logical OR of bits RI and TI in register SCON

TI

RI

Part 5


62/95


Priority bit=1: High Priority; Priority bit=0: Low Priority PS: Serial Port priority bit

PT: Timer priority bit

PX: External priority bit

7 6 5 4 3 2 1 0

IP - - - PS PT1 PX1 PT0 PX0

Part 6


63/95


A low-priority interrupt can be interrupted by a higher priorityinterrupt, but not by another low-priority interrupt

A high priority interruptcannot be interrupted by any other interrupt source

If two requests are received simultaneously,the request of higher priority level is serviced

If requests of the same priority level are received simultaneously,an internal polling sequence determines which request is serviced

``priority within level'' structure is only usedto resolve simultaneous requests of the same priority level.

Part 7


64/95


Interrupt Prioritywithin Level Polling Sequence

1 (Highest) External Interrupt 0

2 Timer 0

3 External Interrupt 1

4 Timer 1

5 (Lowest) Serial Port

Part 8


65/95


The INT0 and INT1 levels are inverted and latchedinto the Interrupt Flags IE0 and IE1 at S5P2 of every machine cycle

Serial Port flags RI and TI are set at S5P2

The Timer 0 and Timer 1 flags, TF0 and TF1,

are set at S5P2 of the cycle in which the timers overflow If a request is active and conditions are right,

a hardware subroutine call to the requested service routinewill be the next instruction to be executed

In a single-interrupt system, the response time is always

more than 3 cycles and less than 9 cycles

Part 1


66/95

Intel 8051: Reset

The reset input is the RST pin, which has a Schmitt Trigger input

Accomplished by holding the RST pin highfor at least two machine cycles (24 oscillator periods)while the oscillator is running

The RST pin is sampled during S5P2 of every machine cycle While the RST pin is high,

the port pins, ALE and PSEN are weakly pulled high

Driving the ALE and PSEN pins to 0 while reset is activecould cause the device to go into an indeterminate state

Part 2


67/95

Intel 8051: Reset

S5 S6 S1 S2 S3 S4

ALE

PSEN

S5 S6 S1 S2 S3 S4

A0-A7 A0-A7INS.

IN

S5 S6 S1

P0 INS.

IN

INS.

IN

A0-A7INS.

IN

INS.

IN

RSTINTERNAL RESET SIGNAL

A0-A7 A0-A7INS.

IN

INS.

IN

INS.

IN

SAMPLE

RST

SAMPLE

RST

S2 S3

11 OSC. PERIODS 19 OSC. PERIODS


68/95

Intel 8051: Power On Reset

RST pin must be held high long enough to allow the oscillator tostart up plus two machine cycles

The oscillator start-up time depend on the oscillator frequency

Port pins will be in a random state until the oscillator has started

and the internal reset algorithm has written 1s to them Powering up the device without a valid reset could cause the CPU

to start executing instructions from an indeterminate location


69/95

Intel 8051: EPROM Versions

Electrically programmable by user

Relative slow

Limited number of erase/write cycles


70/95

Intel 8051: OTP Versions

One Time Programmable

It is standard EPROM without erasing window

It is used for limited production


71/95

Intel 8051: FLASH Versions

Supports in-system and in-board code changes

Electrically erasable

Reduces code inventory and scrap

Simplifies the task of upgrading code and

reduces upgrade cycle time

Provides just-in-time system software downloads

Truly non-volatile


72/95

Intel 8051: The On-Chip Oscillator

Intel 8051microcontrollers havean on-chip oscillator

resonators are

connected betweenXTAL1 and XTAL2pins

external oscillators(HMOS or CMOS)

8051

XTAL2

XTAL1

VSS

C1

C2

QUARTZ CRYSTAL ORCERAMIC RESONATOR


73/95

Intel 8051: Power Management

Low power devices

Power saving

Voltage monitoring


74/95

Intel 8051: Power Reduction Modes

CHMOS versions provides power reduced modes of operations

There are two power reducing modes Idle and Power Down

In the Idle mode oscillator continues to ranInterrupt, Timer and Serial Port blocks continue to be clocked

clock signal is gated off to the CPU In the Power Down mode the oscillator is frozen

Part 1


75/95

Intel 8051: Instruction Set

Arithmetic OperationsADD Addition

ADDC Addition with Carry Flag

SUBB Subtraction

INC Increment

DEC Decrement

MUL Multiply

DIV DivideDA Decimal Adjust Accumulator

Part 2


76/95


Logical OperationsAND And

ORL Or

XRL Exclusive-Or

CLR A Clear (Accumulator)

CPL A Complement

RL A Rotate Left

RLC A Rotate Left through Carry FlagRR A Rotate Right

RLC A Rotate Right through Carry Flag

SWAP A Swap nibbles within Accumulator

Part 3


77/95


Data TransferMOV Move

MOVC Move Code byte

MOVX Move External RAM byte/word

PUSH Push direct byte on stack

POP Pop direct byte from stack

XCH Exchange

XCHD Exchange low order Digit

Part 4


78/95


Boolean Variable ManipulationCLR Clear bit/flag

SET Set bit/flag

CPL Complement bit/flag

ANL AND bit and flag

ORL OR bit and flag

MOV Move bit

Part 5


79/95


Program and Machine Control #1ACALL Absolute Subroutine Call

LCALL Long Subroutine Call

RET Return from Subroutine

RETI Return from interrupt

AJMP Absolute Jump

LJMP Long Jump

SJMP Short (Relative) JumpJMP @A+DPTR Jump indirect relative to the DPTR

Part 6


80/95


Program and Machine Control #2JZ Jump if Accumulator is Zero

JNZ Jump if Accumulator is Not Zero

JC Jump if Carry flag is set

JNC Jump if No Carry flag

JB Jump if Bit set

JNB Jump if Bit Not set

JBC Jump if Bit set & Clear bitCJNE Compare and Jump if Not Zero

DJNZ Decrement and Jump if Not Zero

NOP No Operation

Part 7


81/95


Instructions that affect Flag Settings #1C OV AC

ADD X X X

ADDC X X X

SUBB X X X

MUL 0 X

DIV 0 X

DA XRRC X

RLC X

Part 8


82/95


Instructions that affect Flag Settings #2C OV AC

SET C 1

CLR C 0

CPL C X

ANL X

ORL X

MOV C, bit XCJNE X

Operations on PSW X X X


83/95

Intel 8051: Addressing Modes

Immediate Addressing

Direct Addressing

Indirect Addressing

refers to Internal RAM, never to an SFR

External Direct

only two commands that use External Direct

DPTR holds the correctexternal memory address

External Indirect

Code Indirect

MOV A,#20h

MOV A,30h

MOV A,@R0

MOVX A,@DPTR

MOVX @DPTR,A

MOVX @R0,A

MOVC A,@A+DPTR


84/95


- in millions of dollars -

'95 '96 '97 '98 '99 00

4-bit 1826 1849 1881 1856 1816 1757

8-bit 5634 6553 7529 8423 9219 9715

16-bit 1170 1628 2191 2969 3678 4405

Source

WSTS & ICE


85/95

Intel 8051: Manufacturers

AMD

ARM Microcontrollers

ARC Cores

Atmel

Dallas

Hitachi semiconductors

Intel

ISSI

Matra

Microchip

OKI

Philips

Siemens

SMC SSI

Texas Instruments

ZiLog

etc.


86/95

Intel 8051: Additional Features

Watch Dog Timers

Clock Monitor

Resident Program Loader

Software protection

P Supervisory Circuit


87/95

Watch Dog Timers

Provides a means of graceful recovery from a system problem

If the program fails to reset the watchdog at some predeterminedinterval, a hardware reset will be initiated

Especially useful for unattended systems


88/95

Clock Monitor

If the input clock is too slow, a clock monitor can shut themicrocontroller down

Usually software controlled status (on/off)


89/95

Resident Program Loader

Loads a program by initializing program/data memory from either aserial or parallel port

Eliminates the erase/burn/program cycle (typical with EPROMs)

Allows system updating from an offsite location


90/95

Software protection

Protect unauthorized snooping (reverse engineering,modifications, piracy, etc.

Only OTPs and Windowed devices option

Part 1


91/95


Functions:

P reset (active low or high) Manual reset input

Two stage power fall warning

Backup-battery switchover

Write protection of RAM

2.275 threshold detector

Battery OK flag indicator

Watch Dog timer

2

1

3

4

5

6

7

8

15

16

14

13

12

11

10

9

MAXIMMAX807

PF1

PF0

Vcc

WDIGND

MR

LOW LINE

RESET

OUT

BATT OK

BATT

BATT ONCE IN

CE OUT

WDO

RESET

Part 2


92/95


PIN NAME FUNCTION

1 PFI Power-Fall Input

2 PFO Power-Fall Output

3 VCC Input Supply Voltage

4 WDI Watchdog Input

5 GND Ground

6 MR Manual-Reset Input7 LOW LINE Low-Line Comparator Input

8 RESET (H) Active-High Reset Output

Part 3


93/95


PIN NAME FUNCTION

9 RESET (L) Active-Low Reset Output

10 WDO Watchdog Output

11 CE OUT Chip-Enable Output

12 CE IN Chip-Enable Input

13 BATT ON Battery On Output

14 BATT Backup-Battery Input15 BATT OK Battery OK Signal Output (Vbatt>2.265)

16 OUT Output Supply Voltage to CMOS RAM

Part 4


94/95


MAXIM

MAX807

Vcc OUTBATT

ONBATT

0.1uF 0.1uF

CMOSRAM

REAL

TIMECLOCK

CE OUT

ADDRESS

DECODECE IN

uP

ADDRESS

I/ONMI(INT)

RESETINT

RESET

RESET

LOW LINEWDI

BATT OK

MR

WDOPFO

GND

PFI

+12V

+12V FAILUREWATCHDOG FAILURE

+5V

OTHERSYSTEM

RESET

SOURCES

PUSH

BUTTONSWITCH


95/95

Characteristics Comparisons

ManufacturerClock

[MHz]

V

[V]

ROM

[KB]

RAM

[bytes]I/O

Timers/

Counters

communi-

cation

Additional

Features

Atmel 242.7 to

62 to 8

128 to

25632 Up to 3

full duplex

serial port

Dallas 25 to 33 0 to 16256-byte

to 1.2

kbyte

3 two serialUSARTs

watchdog,

power monitor,address and

data encryption

Intel0.5 to

24

2.7 to

60 to 32

128 to

256

24 to

562 to 3 UART

4 to 8 channel 8-

bit ADC,

watchdog,

PWM

Matra 422.7 to

6

4 to 32128 to

256

32 2 to 3 UART, I2C

ROM

protection and

secret tag,watchdog

Oki 242.7 to

5.50 to 16

128 to

25632 2 to 3 UART

Siemens 18 to 40 8 to 32256-byte

to 2.2-

kbyte

56 3 to 4two serial

ports

two watchdog

timers, 16-bit

MPY/DIV unit

micro controller m 8051

Documents