MICHAEL W. SCRIBER27084 Grandview Ave, Hayward, CA 94542

Home: (512) 917-9850, E-mail: mscriber77@gmail.com

Career GoalsLead a successful team as an engineering director to design and implement creative products that amaze and delight the customer.

PROFESSIONAL HISTORY

SAMSUNG SEMICONDUCTOR, San Jose, CA Feb 2014 – Nov 2016Director, Systems EngineeringDirected the HW development for designs to increase Samsung components in the data center. Designed and developed the first 2U 40 NVMe SSD storage system. Designed and created a fully equipped development lab. Architected various NVMe storage systems. Transitioned to Stellus Technologies, a stealth startup spinout.

DELL, Round Rock, TX May 2003 – Feb 2014Development ManagerManaged all of the engineering disciplines for the development of the solution for rack and blade server programs. Created and launched 9 platforms over 5 generations: PE2850, PE2800, PE1850, PE1955,

PEM605, PEM805, PEM905, PEM910, and PEM420. Designed the FX2 converged server system. Developed our first AMD blade, full height blade, and quarter height blade. Integrated Wistron, our blade ODM, into the Dell development model and worked process

improvements with Wistron.

TOSHIBA AMERICA ELECTRONIC COMP, Beaverton OR Jul 2002 – Mar 2003ASIC Design Engineering ManagerDirected the synthesis, DFT insertion, floorplanning, place/route, and timing closure for back-end processing of customer ASIC designs into the Toshiba ASIC fab. Interfaced with the customer’s engineering staff and resolved technical and timing issues. Created the project schedule and directed the multiple site tactical execution to the schedule. Managed the Portland Design Center staff and improved their engineering skill capability.

IBM, Beaverton OR Apr 2000 – Jul 2002Senior Engineering ManagerLed multiple board development projects of large, scaleable 64 bit Intel Architecture (IA-64) server computer systems. This included: Technical leadership and direction for two simultaneous server products. Resource planning, budgeting, scheduling, and execution, which kept the projects on track. Interfaced with marketing, service, manufacturing, outside vendors, and partners. Responsible for all aspects of managing 19 direct reports including hiring (regular &

contractor), reviews, salaries, budgeting, staffing, development plans, coaching, and firing.

SEQUENT COMPUTER SYSTEMS, INC., Beaverton OR Oct 1996 – Apr 2000Engineering Manager

Michael W. Scriber Page 2

Directed the ASIC and board development and validation of a high performance, IA-32 server computer system. Project responsibility from architectural concept, through development, validation, release,

and speed upgrades, to end of life of the best computer ever developed by Sequent on time. Managed 11 engineers, technicians, and contractors. Led the validation and system hardware and software integration resulting in a successful, on

schedule launch of the Scorpion server system. Staff Systems EngineerTechnical Project Lead of a hardware development team responsible for the baseboard design and validation of a high performance IA-32 server computer system.

INTEL CORPORATION, Hillsboro OR Sep 1993 – Aug 1996Engineering ManagerManaged hardware development teams in the design and validation of high performance Intel Pentium and Pentium Pro microprocessor server computer systems. Led the verification and design release of a 4x and a 2x SMP Pentium microprocessor

server system. Drove the planning and design of a 2x Pentium Pro microprocessor-based server computer

system with advanced technology I/O. Led the efforts of all of the subsystems, including chassis, BIOS, test, and systems. Kept development on schedule.

Wrote the ISO 9001 procedures for board development and hardware design reviews used by the Server System Product Division.

ASIC Design EngineerSole developer of an interrupt control ASIC used in all of Intel’s server system products, at the time. The development included ASIC architecture, design, VHDL coding, simulation, synthesis, vendor selection, vendor signoff, and device validation. Developed a production worthy ASIC without revisions. Successfully synthesized at least six ASICs, as the Synopsys expert in our group. Pioneered, for our group, the use of iLogix as an ASIC development CAD tool.

EPSON PORTLAND, INC., Hillsboro OR Aug 1992 – Jul 1993ASIC Design Engineer - Design Group Assistant ManagerDesigned ASIC core sets for high performance Intel 486 and Pentium microprocessor personal computer (PC) systems. Led ten engineers in designing six PC system and component products, including needed strategic interfaces with marketing, sales and key technology vendors. Invented a new memory subsystem design, improving system memory access by 33%. Created a new PC video architecture, significantly improving graphics performance. Designed a memory controller ASIC for advanced DRAMs, allowing zero wait state access

without a secondary cache. The controller provides high performance at a low cost.

UNITED STATES AIR FORCE Oct 1985 – Oct 1992Computer EngineerTechnical interface managing contractors for the development of space-based computer hardware and software for the Space Shuttle, the Titan II space launch vehicle, and two Space Defense Initiative (Star Wars) programs.

EDUCATION

MS Computer Engineering (VLSI Design), Polk Award (best overall graduate)Air Force Institute of Tech., Dayton, OH.

BS Computer and Systems Engineering, Magna Cum LaudeRensselaer Polytechnic Institute, Troy, NY.

INVENTIONS

Carry Multiplexed Adder, patent # 5,227,662High Order Carry Multiplexed Adder, patent # 5,229,959

Method and apparatus for dynamically switching between asynchronous signals without generating glitches, patent # 5,483,185

Mechanism for dynamically determining and distributing computer system clocks, patent # 5,572,718

Interrupt steering for a computer system, patent # 5,640,571