menu navigation presented by: tzahi ezra advisors: moshe porian netanel yamin one semester project...
TRANSCRIPT
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Menu Navigation
Presented by: Tzahi Ezra
Advisors:
Moshe PorianNetanel Yamin
One semester project
Presented on: 20.10.2015
Project initiation: NOV 2014
PROJECT’S FINAL PRESENTATION
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Contents Abstract
Project Goals
Top Architecture
General flow
Micro architecture
Mechanism of use
Testability
Synthesis
Place & route
Problems and solutions
Summary
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Mobile-phones
Military Remote Diagnostic
Electronic Flight
Abstract
Nowadays, navigation between symbols (icons) in a menu on display screens is a very common operation.
Therefore, it is crucial to enable fast changes to the display.
Implementation using HW only, without SW use, is the common way, in order to minimize frame transmission time and save resources.
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Project’s goal
Navigation in a menu:
Implement blocks in FPGA, coded in Vhdl HDL, for Moving a cursor symbol right, left, up or down on display screen using HW only:
Receive direction signals from slide switches on the DE2 board
Apply to an internal navigator block, which saves the cursor symbol location
Use the symbol generator project platform with modifications to dispatch the cursor symbol onto the screen
Move the cursor symbol on the screen using the switches and only when the frame starts being drawn from upper left corner
The top level blocks communicate via Wishbone protocol
The project focuses on one of the top level blocks - added internal block and modifications into it
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Top Architecture reused
Navigator
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General flowRam initialization:
Navigat
or
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SDRAM initialization:
Navigat
or
General flow
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Navigat
or
General flowContinuous use:
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Micro architectureDisplay controller block
Navigator
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Micro architectureSG TOP: The “brain” block
Navigator
Inversion
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To manager
Navigator
x_y_location_top
Micro architectureNavigator block
x_y_location
update_ upon_ vsync
Debouncer
Debouncer
Debouncer
Debouncer
clk
reset
right
left
up
down
vsync
x_out
y_out
hor_loc
ver_loc
right_trig
left_trig
up_trig
down_trig
x_updated
y_updated
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Manager
Micro architectureManager block
select
0
1
sym_loc
sym_rowsym_col
resetclk
sdram_data[7:0]
ver_loc
hor_loc
inversion
sdram_mux_out[7:0]
Clk
ver_loc
hor_loc 1
10
0001010
sdram_mux_out[7:0]
0001010
1110101
sym_col
sym_row 10
10 … 2
0001010
FSM
FifoA
FifoB
…
…
…
… …
…
Comparator
select 0 1 … 0
1
sdram_data[7:0]
0001010
1110101
0001010
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Sdram read address = Bank(2) & Ram data out(13) & ‘0’/’1’ & inside row*16(8)/(inside row-16)*16(8)
RAM
Ram data out Symbol add. Ram rd add.
0000000000000 Add. Of symbol (0,0) in the SDRAM 0
0000000000010 Add. Of symbol (0,1) in the SDRAM 1
… … …
0111111111111 Add. Of symbol (0,19) in the SDRAM 19
… … …
0111111111111 Add. Of symbol (14,19) in the SDRAM 299
SDRAM
Symbol row 15 (32)
… Symbol row 1 (32)
Symbol row 0 (32)
31 16 1 0
0xCD
… 0xCD
0xCD
… 0xDF
0xFF
0xAB
… 0xBB
0xAB
0xCD
… 0xCD
0xCD
0xCD
0xCD
0xCD
0xCD
0xCD
0xCD
… 0xCD
0xCD
… 0xAB
0xCA
0xCD
… 0xCD
0xAC
0xCD
… 0xCD
0xCD
… 0xAB
0xCA
0xCD
… 0xCD
0xCD
… … …
… … …
0xCD
… 0xCD
0xCD
… 0xAB
0xCA
0xCD
… 0xCD
0x14
0x17
… 0xCD
0xCD
… 0xAB
0xCA
0xCD
… 0xCD
0xCD
14 … 0 …0 … 0 Symbol row(X)
19 …0 19 …1 … 0 Symbol column(Y)
31 …1 0 …0 … 0 Inside row
0 … 0 …0 … 0 Vertical location
… 1 …1 … 1 Horizontal location
… 1 …1 … 0 Ram read address
000111111111111111110000
… 000000000000000000100000
000111111111111000000000
…000000000000010000000000
… 000000000000000000000000
Sdram read address
0x17 …0xDF 0x14 …0x52 …0xBB0xAB Sdram_mux_out
Ram read address = 20*X+Y
Symbol 0
Symbol 1
Symbol 4095
…
Micro architectureMemories
Match occurs…
Selectedrow
Inversion occurs
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Mechanism of use Navigation:
down up left right
Next state Curr. state
Y X Y X Y X Y X Y X
1 0 14 1 14 19 0 1 0 0
1 19 14 0 0 18 1 0 0 19
0 18 13 19 14 18 0 0 14 19
0 19 13 0 13 19 14 1 14 0
1 X 14 X+1 0 X-1 0 X+1 0 1..18
19 Y+1 19 Y-1 Y-1 18 Y+1 0 1..13 19
0 X-1 13 X 14 X-1 14 X+1 14 1..18
Y+1 0 Y-1 0 Y-1 19 Y 1 1..13 0
Y+1 X Y-1 X Y X-1 Y X+1 1..13 1..18
Vsync arrives……
Indicates when the frame starts being drawn from upper left corner
Upper rowUpper right cornerLower left corner
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Simulation using ModelSim
Unit level and top level tests
Testing using randomization in different aspects:
Direction selection
Switching time
Interval time
Examine the results using assert statements, for a better control
Lab examination
Response of the cursor symbol to switches movements
Special scenario when located in edges of the frame
Response of the cursor symbol to reset button
Symbol inversion in cursor symbol coverage
TestabilityTest plan:
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TOP SYNTHESIS TB
TOP SYNTHESIS
Uart_tx_gen
global_nets_top
uart_serial_in
clkFpga_clk
resetFpga_rst
uart transmission file, MDS TOP
vesa clk, sdram clk, system clk and reset
RX path
TX path
SDRAM Controller
Mem management
Display Controller
SDRAM Model
RGB
debug purposes
TestabilityTop level test structure:
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Waveform example:
Testability
Navigation operation, Navigator block:
Time interval to trigger a change after switching begins, is set to 50 ns
vsync arrival, after 660 ns of
down switching
Down switching while cursor’s vertical location is 1
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I’ve used checkers in order to better control the simulation:
If the assert condition would have been FALSE (assert (dout = ‘1’)), than the report clause would have been transmitted to the console, with the mentioned severity:
TestabilityCheckers use:
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Waveform example:
Testability
Pixel inversion ,Top level block:
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Waveform example:
Testability
Pixel inversion ,Top level block
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TestabilityLab examination
downup
leftright
reset
System view:
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TestabilityLab examination
Symbol addition:
Cursor symbol
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TestabilityLab examination
Cursor navigation to symbol in location (12,3):
Cursor symbol inverts original symbol
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Synthesis Precision rtl view:
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Place & routeQuartus tool resources report:
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1. Problem: updating the cursor symbol's location after the frame has started being drawn, might cause pixel smearing.
Solution: updating the cursor symbol's location immediately after vsync arrival, action that is performed in the update_upon_vsync block, guarantees that the cursor symbol will not change its location in the middle of a frame.
Problems and solutions
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2. Problem: the system clock (100 MHz) did not appeared in the clock path, therefore caused timing problems.
Solution: using quartus Technology Map viewer, I've noticed that the fpga clock (50 MHZ) was mistakenly connected as the system clock.
Problems and solutions
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3. Problem: synchronization problem of the system clock(100 MHz) with the update_upon_vsync block. The rise of the system clock did not trigger the event of location update, but the vsync signal. That caused this block to be asynchronous and might cause timing problems.
Solution: the system clock was added to the architecture synchronous part so that the location would be updated when the vsync signal is set to ‘1’ only in the rising edge of the clock.
Problems and solutions
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The main goal of this project, navigating between symbols using a cursor symbol, adding blocks to the symbol generator project platform, while managing to fulfill the timing constrains, simulating and debugging VHDL code using ModelSim program, synthesizing using precision tool and P&R using Quartus program was done successfully
Moreover, goal had been achieved by:
Organized working methods using the SVN and google drive cloud storage, helped synchronizing with the project's supervisors.
Use of randomization while testing
Proper use of Precision and Quartus capabilities, such as Technology Map viewer.
Documentations – helped organization and eased the block design and the system understanding.
Summary
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The END
Lets continue to the lab