mentor plane noise effects 59483

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PLANE NOISE EFFECTSJuly 2010

ABSTRACT

High speed digital drivers need a good source of power to produce clean, fast signals. For a

driver to switch the state of a signal in tens or hundreds of picoseconds, the power plane

must be able to supply significant current over a wide bandwidth. The surge in current

creates voltage fluctuations in the power distribution network (PDN) that appear as noise at

the power pins of the drivers. This plane noise is then transferred through the driver to thesignal that is being driven onto a transmission line. Power integrity analysis tools can provide

an impedance profile of the PDN in the frequency domain, and a noise profile of the PDN in

the time domain, but it is also useful to see the effect that the noise at the power pin of an IC

has on the resulting output signal quality. By extracting a model of the power plane, a

simulation can be run using SPICE models for drivers and receivers, revealing the PDN noise

effects on the transmitted signal.

Author:Bruce Caryl

Mentor Graphics Corporation

8005 SW Boeckman Road

Wilsonville, OR 97070 USA

Phone: +1 800-592-2210 or +1 503-685-7000



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POWER PLANE PLANNING

The power distribution network should be designed and analyzed to meet performance goals

early in the design process. HyperLynx LineSim has a PDN editor that can be used to

experiment with plane size, spacing, and with the values and positions of decoupling

capacitors. For this example, we will use a four layer board with a thickness of approximately

31 mils. The internal layers are VCC and GND, and the outer layers are used for routing.Figure 1 shows the stackup for this simple design that will be analyzed.

Figure 1 – Example design stackup

EXAMPLE DESIGNS

Two versions of the board will be

analyzed: one with a single capacitor

located in the middle of the board, and

one with many capacitors distributed

around the board to provide good

decoupling between the planes. Figure

2 shows the 4 X 8 inch board, with the

source of the power located on the leftside at U1.1, and the IC that uses the

power located on the right side at U2.1.

A single decoupling capacitor with a

value of 1 uF is located in the center of

the board. Figure 2 – LineSim PDN design with one 1 uF capacitor



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Figure 3 shows the

same board with 19

decoupling capacitors

spread around the

board to provide a

low impedance path

between the VCC and

GND planes.

The values of the cap-

acitors are shown in

Table 1.

These are not

necessarily optimal

values, but they

provide good

decoupling over awide range of fre -

quencies. When the

IC (represented by

U2.1) draws current to switch at a certain

frequency, the noise from the PDN on the pin

should be significantly less on the board with

many capacitors than on the board with just

one.

THE IMPEDANCE PROFILE

The impedance profile for the first board is

indicated by the red or top line in Figure 4.

This shows the impedance that the power pin

U2.1 sees looking into the power plane. Itincludes the effects of the spreading induc-

tance of the planes, the capacitance of the

VCC and GND plane cavity, the mounting

inductance, and the value of the capacitor

and its intrinsic parasitics. The target

impedance is set at 330 mohms (indicated by

the green line), which is the value that will

allow 500 mA to flow through the PDN and

not allow more than 165 mV of voltage ripple

(5% of 3.3V). Note that the impedance

violates this value over a wide frequency

range where the IC will likely operate. The

first dip in the impedance plot occurs atapproximately 3.6 MHz and is due to the

effect of the single 1 uF capacitor. The

impedance profile for the second board is

shown by the purple line in Figure 4. It meets

the impedance goal up to approximately 200

MHz, which is a good result for this design.

The first trough in the single capacitor impe -

dance profile represents the series resonant

frequency of the capacitor with its ESL

(including the estimated mounting induc-tance). The following peak is caused by the

parallel resonance of the plane capacitance

with the ESL of the capacitor. Another trough

is caused by the series resonant frequency of

Figure 3 - LineSim PDN design with 19 capacitors

Quantity Value ESL ESR

1 1 µF 630 pH 12 mΩ9 0.1 µF 410 pH 19 mΩ

9 0.01 µF 470 pH 78 mΩ

Table 1 - Capacitor values



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the spreading

inductance of the

plane with the

capacitance of the

plane. Above this

frequency, modalresonances of the

plane dominate,

which are caused

when a multiple of a

half wavelength of a

given frequency

equals the distance

from the power pin

to the edge of the

plane, where thesignal is reflected.

The impedance

profile for the board

with many capaci-

tors is much more complex. It represents the

combination of the interactions of all the ca-

pacitors with each other and with the plane

capacitance and plane spreading inductance.

Note that there are two more troughs in this

impedance profile caused by the two ad -ditional capacitor values.

CREATING A PDN MODEL

In order to analyze the board with drivers and

receivers, a model must be created that rep-

resents the impedance an IC power pin sees

when looking back to the power supply pin.

The “Export->Model->PDN and Channel Mo-

del” menu command in LineSim will start awizard that will create a two-port

S-parameter model that includ -

es both pins. The interface is

shown in Figure 5, where the

power supply is port 1, and the

IC power pin is port 2.

These models will now be used

in time-domain simulations to

determine the affect that the

planes have on the outputsignal.

Figure 4 – Plane impedance profiles

Figure 5 – PDN S-parameter model export



SIMULATING WITH

SIMPLE DRIVER AND

RECEIVER MODELS

An analog schematic is now

created in DxDesigner and

simulated with HyperLynx Analog and the Eldo SPICE

simulator from Mentor. Note

that this same schematic and

simulation can be set up in

HyperLynx SI GHz. A model

for a generic driver is made

from SPICE switches that

have variable turn-on and

turn-off times and adjustable

“on” resistance. The switchesrepresent the typical CMOS

output drive transistors, and a

voltage pulse controls the the

switches, which open and

close in opposite phase. The

model is parameterized so

that all the values can be

controlled from the top level

symbol. The model is shown

in Figure 6.The top-level schematic (Figure 7)

that will be simulated has eight

instances of this driver, with each

instance driving a 50 ohm, 1 ns

transmission line into a 50 ohm

resistive load. This schematic

represents an IC which has 8

outputs and a single power pin.

For the first simulation, the drivers

switch at 77 MHz, with a nominal

rise and fall time of 1 ns, and an

output impedance of 5 ohms. Thisschematic could be modified to

simulate other configurations of

drivers and loads.


Figure 6 – Simple driver model

Figure 7 – Eight drivers with single power pin



The power pin to the IC pulls

current through the power plane

S-parameter model. The model

is located in the upper left corner

of the schematic, and an

additional resistor (R2) has beenadded to sense the current out of

the plane and to account for a

small pin resis tance. The Eldo

simulator can directly use S-

parameter models in time-domain

simulations. A detailed view of

the schematic component with the reference

to the S-parameter file is shown in Figure 8.

A time-domain simulation is run using the

one-capacitor plane model with a switchingspeed of about 77 MHz, which corresponds

to relatively high impedance for this PDN.

The waveforms at the first driver (vtx1) and

receiver (vrx1) are shown in Figure 9, along

with the noise voltage waveform at the power pin to the IC.


Figure 8 – S-parameter model of the PDN

Figure 9 – Waveforms and noise for one-cap plane



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The noise can be esti-

mated as the larger of

the maximum value

above or below the

nominal 3.3 V supply.

We can estimate thenoise Figure 10 to be

approximately 430 mV,

well above our goal of

165 mV (3.3 V X 5 %).

Now we will run the

same simulation using

the model of the board

with many decoupling

capacitors. The wave-

forms in Figure 11 showthe noise at the power

pin (top graph) and the

voltage at the trans-

mitter and receiver.

Note the smoother waveforms

at the transmitter and receiver,

and the reduced noise amp-

litude at the power pin. The

maximum amplitude of the

noise for this simulation is ap -proximately 90 mV below the

3.3 V input voltage. This is well

within the required 165 mV

tolerance. Figure 12, on the

following page, shows a direct

comparison of the noise wave-

forms from the two plane

models.

Figure 10 – IC power pin noise with one decoupling cap

Figure 11 – Waveforms and noise for many-cap plane



Since the performance

of the power plane is

frequency dependent,

it would be interesting

to see what the wave-

forms look like at a

lower driver frequency

of 10 MHz. This freq-

uency is in the region

of the impedance pro-

file where both boards

appear to pass, but if

the edge rates are still

the same, will the

noise voltage be be -

low the required noise

budget?

The parameterized

driver models arechanged so that they

switch at 10 MHz and

then re-simulated.

Figure 13 shows the

resulting noise at the power

pin along with the driver

and receiver waveforms for

the many-capacitor plane.

The results show that the

noise is created by theedge rate, not the switching

frequency, and is still

approximately 100 mV.

The voltage on the power

pin shows a significant

oscillation at 273 MHz,

which corresponds to the

second series resonant

trough in Figure 4. A

frequency analysis at thepower pin shows this res-

onant point as well, and

may be of concern if noise

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Figure 12 – Power pin noise comparison

Figure 13 – 10 MHz noise, receiver, and transmitter waveforms



at this frequency and

amplitude would interfere

with other parts of the

design. Figure 14 shows

the frequency response

of the power pin from 1MHz to 1 GHz, with the

resonant peak indicated

by the cursor position.

HyperLynx PI offers a

simpler way to determine

the noise amplitude

anywhere in a plane by

using the Plane-Noise

Simulation feature.

Since the current wave-form through a driver is

similar to a trapezoid or

triangle pattern, the pat-

tern can be entered into

the analysis and the resulting noise amplitude

across the plane displayed. The results are

shown in Figure 15 for the 77 MHz, one-

capacitor plane case. Note how the single

capacitor allows high frequency current to

flow between planes, and thus creates a low

amplitude noise point at its location near the

center of the plane. The maximum noise is

calculated to be 343 mV

near the edge of the plane,

which is close to the 430mV measured at the power

node with the simulated

driver.

SIMULATING WITH

COMMERCIAL SPICE

MODELS

Some IC vendors provide

SPICE models for their

drivers and receivers. ON

Semiconductor provides

SPICE models for their

PECL parts, and also

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Figure 14 – Frequency response at IC power pin

Figure 15 – Plane noise for one-capacitor plane



includes models for the package and ESD

effects. A schematic using these models is

partially shown in Figure 16.

An ideal power supply is typically connected

to the power pin, but in this example the

model for the many-capacitor power plane is

connected to the power supply for both thedriver and receiver. This will provide and

accurate view of how the power plane affects

the output waveform. The technology of the

driver and receiver is differential positive ECL

(PECL). An ideal, 500 ps, 50 ohm

transmission line is connected to the driver

and receiver and it is terminated differentially

with 100 ohms. The driver is switched at the

rate of 667 MHz. Since this is a differential

signal, eye diagrams are the most effective

way to evaluate the results. In this example,

the data oscillates but is not varied in any

particular pattern. Figure 17 shows the eye

diagram with the one-capacitor plane model,

and Figure 18 shows the eye diagram with

the many-capacitor model.

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Figure 16 – ON Semiconductor SPICE model circuit



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Figure 17 – PECL eye diagram with one-capacitor plane model

Figure 18 – PECL eye diagram with many-capacitor plane model



The main difference is in the eye width, where the

width is approximately 10 % wider when using the

better decoupled power plane. The narrower eye is

due primarily to the rise time degradation as a result of

the poor high frequency performance of the one-

capacitor power plane. This example points out the

importance of having a good power distribution

network when trying to get the maximum performance

out of high speed differential interfaces.

CONCLUSION

High-speed digital drivers need a good, low

impedance power distribution network to keep the

switching noise low enough so that they can operate

within their specified supply voltage range. When a

driver switches a voltage onto a transmission line, it

draws a significant amount of current in a short period

of time. By creating a low impedance path from the

power plane to ground, the high frequency noise

transients will be minimized. HyperLynx PI provides

the analysis necessary to design the PDN to meet the

performance goals of the design. If SPICE models of

the driver and receiver are available, a power plane

model can be created and used in a SPICE simulation

to provide even more detailed analysis.

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For more information, call us or visit: www.mentor.com/pcbCopyright © 2010 Mentor Graphics Corporation. The marks for the Mentor products and processes mentioned in this document are trademarks or registered trademarks of Mentor Graphics Corporation. All other trademarks mentioned in this document are trademarks or registered trademarks of their respective owners.

mentor plane noise effects 59483

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