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Timers

Timers are often used as support chips tomicroprocessors or as components insidemicrocontrollers.

Eg:8353/8254 as support chips for Intel 80xxx

Timers used in 8051 series microcontrollers

8254 Programmable Interval Timer

WR WRITE CONTROLRD READ CONTROLCS CHIP SELECT

CLK 0 Clock input of Counter 0OUT 0 Output of Counter 0GATE 0 Gate input of Counter 0

CLK 1 Clock input of Counter 1GATE 1 Gate input of Counter 1OUT 1 Output of Counter 1

CLK 2 Clock input of Counter 2OUT 2 Output of Counter 2GATE 2 Gate input of Counter 2

D7 D0 Bi-directional three state data bus lines

A1, A 0 ADDRESS

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The Intel 8254 is a counter/timerdevice

designed to solve the common timing control

problems in microcomputer system design.

It provides three independent 16-bit counters,

each capable of handling clock inputs up to

10 Mhz.

All modes are software programmable.8254Block Diagram

8254 Applications

Real time clock

Event Counter

Digital one-shot

Programmable rate generator

Square wave generator

Binary rate multiplier

Complex waveform generator

Complex motor controller

8254 Applications

In the original IBM PC, 8253 (the predecessorof 8254) was used to

generate the time-of-day clock tick (18.2 Hz)

refresh dynamic RAM (66.6 Hz) and

to drive the speaker

In PCs, I/O addresses 40 43 are assignedfor the timer

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Counter Modes

Mode 0: Interrupt on terminal count

Mode 1: Hardware retriggerable one-shot

Mode 2: Rate generator

Mode 3: Square wave mode

Mode 4: Software triggered strobe

Mode 5: Hardware triggered strobe


Sets the Output Bit when timer done

The output will start from zero. The count is loaded

and the timer will start to count down. When the

count has reached zero the output will be set high,

and remain high until the next count has been

reloaded.

Mode 1: Hardware retriggerableone-shot

Sets the Output Bit when timer done

The output will go low following the rising edge of

the gate input. The counter will count and the

output will go high once the counter has reached

zero.


The counter will continually count down, when the

count reaches zero, the output will pulse low and

the counter will be reloaded.

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This mode is similar to Mode 2 except the output

remains low for half of the timer period and high for

the other half of the period.


The output will remain high until the timer has

counted to zero, at which point the output will pulse

low and then go high again.


The counter will start counting once the gate input

goes high, when the counter reaches zero the

output will pulse low and then go high again.

System Interface

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Data Bus Buffer

This is a 3-state

bi-directional,

8-bit buffer

used to interface the

8254 to a system bus.

Read/Write Logic

The Read/Write Logicaccepts inputs from thesystem bus andgenerates controlsignals for the other

functional blocks of the8254.

Read/Write Logic

RD = low: CPU reading one of

the counters

WR = low: CPU writing an initial

count or a Control

Word

CS = low: Chip selected for reading

or writing

Read/Write Logic

A1 & A0 selects one of the threecounters or the Control WordRegister.

A1 A00 0 Counter 00 1 Counter 11 0 Counter 21 1 Control Word Register

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Control Word Register

Control register is selected

when A1,A0 = 11.

The control word written

to the control register

determines the mode of

operation of the counters.

This is a read-only

register.

Counters

The three counters areidentical andfully independent

in operation.

The contents of theControl Word register

determine how the countersoperate.

Internal Block Diagram of a Counter Internal Block Diagram of a Counter

Counting Element CE

(the actual counter) is a

presettable,

synchronousdown counter.

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Internal Block Diagram of a Counter

Status register, when latched, contains the current

contents of the Control Word Register, status of the

output and null count flag.

Counting Element CE

(the actual counter) is a

presettable,

synchronous

down counter.


If a Counter Latch command is sent, OLM and OLL latchthe present count, until read by the CPU and thenreturns to following CE.

OLM and OLL (OutputLatches) are two

8-bit latches.M and L stand for most

and least significant bytes

OLM and OLL normally

contain the present value of

the counter CE.


One latch at a time canbe selected for readingthrough the internal bus.

CE cannot be read

directly. Only the OLscan be read.


CRM and CRL (CountRegisters) are two

8-bit registers.

When a count is written

to the Counter, the countis stored in CR and latertransferred to CE (bothbytes simultaneously)

CRM and CRL are cleared when the Counter isprogrammed

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Operational Description

After power up, the state of the 8254 isundefined.

Each counter must be programmed before

it can be used.

Unused counters need not be programmed.

Counters are programmed by writing a

control word and then an initial count.

Control Word Format

Control Word Format Control Word Format

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Control Word Format Write Operations

For each Counter, the Control Word must be written

before the initial count is written.

The initial count must follow the count format

specified in the Control Word

(i.e. LSB only, MSB only, or, first LSB and then MSB)

A new initial count may be written to a counter at any

time, without affecting the current Mode.

Read Operations

Counter values can be read without disturbing the

count in progress.

There are three methods for reading counters:Simple read operation

Counter Latch Command

Read-Back Command

Simple Read Operation

Select the counter (0, 1 or 2) using A1,A0 inputs and

perform a read operation.

CLK input must be inhibited by using either the GATEor external logic. Otherwise, at the moment of

reading, the count may be changing and an incorrect

result may be read.

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Counter Latch Command is a command written to the

Control Word Register (A1,A0 = 11).

SC1,SC0 specify the counter to be latched.


When Counter Latch Command causes the 8254 to

latch the count value of the selected Counter at the

time the command is received.

The output latch (OL) keep the count until it is read

by the CPU or until the counter is reprogrammed.

After reading, OL returns to follow the CE.

This method allows reading the counter without

disturbing the count in progress.


Counter must be read according to the way it is

programmed.

(LSB, MSB or first LSB and them MSB)

Read-Back Command

Using this command, it is possible to read:

the count value

programmed mode

current status of OUT pin, and

Null Count flag

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Read-Back Command

This allows latching multiple counters with one command

Read-Back Command

Each counter's latch count will be held until it is read.

When the count is read, the OL is automatically unlatched.

By setting D4=0, it is possible to latch status information

Status Byte

After latching status, the status byte can be read by

reading the Counter.

Null Count

This can be used to find out whether the last count

written to the counter register has been loaded to CE

After writing to control word register, Null Countbecomes 1

When the new count is loaded to CE from countregister, Null Count becomes 0

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Example Application - 1Tone generator circuit

Design an 8054 based circuit for

generating a 1 kHz tone using a speaker and

for blinking an LED at 1 Hz

Assume that the available clock is 1 MHz

Tone generator circuit

Tone generator circuitCounter Modes


Mode 1: Hardware retriggerable one-shot





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Example Application - 2


generating a hardware alarm signal at timeintervals ranging from microseconds to severaldays.

Example Application - 2


generating an alarm signal at time intervalsranging from microseconds to days.

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