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July 2013 Altera Corporation MegaCore IP LibraryRelease Notes

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July 2013 Altera Corporation

Contents

About These Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiTrademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–viiSystem Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–viiChapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–viii

Chapter 1. 10-Gbps Ethernet MACProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Chapter 2. 10GBASE-R PHYProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Chapter 3. 1G/10GbE and Backplane Ethernet 10GBASE-KR PHYRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Chapter 4. 50G InterlakenProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Chapter 5. 100G InterlakenProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Chapter 6. 40- and 100-Gbps Ethernet MAC and PHYProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

Chapter 7. 8B10B Encoder/DecoderProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1Obsolescence Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1

Chapter 8. Arria V GZ Hard IP for PCI ExpressProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1

Chapter 9. Arria V Hard IP for PCI ExpressProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1

Chapter 10. ASIProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1

Chapter 11. CIC

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Product Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1

Chapter 12. CPRIProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1

Chapter 13. CRC CompilerProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1Obsolescence Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1

Chapter 14. Cyclone V Hard IP for PCI ExpressProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–2

Chapter 15. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IPProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–1Obsolescence Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–1

Chapter 16. DDR3 SDRAM Controller with ALTMEMPHY IPProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–1Obsolescence Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–1

Chapter 17. DDR2, DDR3, and LPDDR2 SDRAM Controller with UniPHYProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–1

Chapter 18. DisplayPortProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–1

Chapter 19. FFTProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–1

Chapter 20. FIR CompilerRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20–1

Chapter 21. FIR Compiler IIProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21–1

Chapter 22. InterlakenProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22–1

Chapter 23. Interlaken PHYRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23–1

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Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23–1

Chapter 24. IP Compiler for PCI ExpressProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24–1

Chapter 25. NCOProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25–1

Chapter 26. Nios II ProcessorProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26–1

Chapter 27. PCI CompilerProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27–1Obsolescence Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27–1

Chapter 28. POS-PHY Level 4Product Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28–1

Chapter 29. QDR II and QDR II+ SRAM Controller with UniPHYProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29–1

Chapter 30. RapidIOProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30–1

Chapter 31. RapidIO IIProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31–1

Chapter 32. Reed-Solomon CompilerProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32–1

Chapter 33. Reed-Solomon IIProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33–1

Chapter 34. RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IPProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34–1

Chapter 35. SDIProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35–1

Chapter 36. SDI IIProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36–1


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Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36–1

Chapter 37. SerialLite IIProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37–1

Chapter 38. SerialLite III StreamingProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38–1

Chapter 39. Stratix V Hard IP for PCI ExpressProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39–2

Chapter 40. Triple Speed EthernetProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40–1

Chapter 41. Video and Image Processing SuiteProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41–1Obsolescence Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41–1

Chapter 42. Viterbi CompilerRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42–1

Chapter 43. XAUI PHYProduct Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43–1Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43–1

Additional InformationHow to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1



About These Release Notes

These release notes cover versions 12.0 through 13.0 SP1 of the Altera® MegaCore® IP Library. The chapters in these release notes describe the revision history for each product in the MegaCore IP Library.

1 From v8.0 onwards, this document replaces all individual IP product release notes and errata sheets that Altera previously published.

1 From v11.1 onwards, for full information on errata and the versions affected by errata, refer to the Knowledge Base page of the Altera website.

Errata are functional defects or errors, which may cause the product to deviate from published specifications. Documentation issues include errors, unclear descriptions, or omissions from current published specifications or product documents.

f For more information about Quartus® II issues, refer to the Knowledge Base page of the Altera website.

TrademarksThese release notes use the following Altera trademarks:

■ Arria® devices

■ Avalon® interface

■ Cyclone® devices

■ HardCopy® devices

■ MegaCore function

■ MegaWizard™ Plug-In

■ ModelSim® simulator

■ Nios® II processor

■ Quartus II software

■ SignalTap® II logic analyzer

■ Stratix® devices

System RequirementsThe MegaCore IP Library is distributed with the Quartus II software and downloadable from the Altera website, www.altera.com.

f For system requirements and installation instructions, refer to Altera Software Installation and Licensing.


http://www.altera.com/support/kdb/kdb-search.jsp

http://www.altera.com/support/kdb/kdb-search.jsp

http://www.altera.com

http://www.altera.com/literature/manual/quartus_install.pdf

http://www.altera.com/literature/manual/quartus_install.pdf

viii About These Release NotesChapter Revision Dates

Chapter Revision DatesThe chapters in this document, MegaCore IP Library, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed.

Chapter 1. 10-Gbps Ethernet MACRevised: 15 May 2013

Chapter 2. 10GBASE-R PHYRevised: 1 July 2013

Chapter 3. 1G/10GbE and Backplane Ethernet 10GBASE-KR PHYRevised: 1 July 2013

Chapter 4. 50G InterlakenRevised: 15 May 2013

Chapter 5. 100G InterlakenRevised: 15 May 2013

Chapter 6. 40- and 100-Gbps Ethernet MAC and PHYRevised: 15 May 2013

Chapter 7. 8B10B Encoder/DecoderRevised: 15 May 2013

Chapter 8. Arria V GZ Hard IP for PCI ExpressRevised: 1 July 2013

Chapter 9. Arria V Hard IP for PCI ExpressRevised: 1 July 2013

Chapter 10. ASIRevised: 15 May 2013

Chapter 11. CICRevised: 15 May 2013

Chapter 12. CPRIRevised: 15 May 2013

Chapter 13. CRC CompilerRevised: 15 May 2013

Chapter 14. Cyclone V Hard IP for PCI ExpressRevised: 1 July 2013

Chapter 15. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IPRevised: 15 May 2013

Chapter 16. DDR3 SDRAM Controller with ALTMEMPHY IPRevised: 15 May 2013


About These Release Notes ixChapter Revision Dates

Chapter 17. DDR2, DDR3, and LPDDR2 SDRAM Controller with UniPHYRevised: 15 May 2013

Chapter 18. DisplayPortRevised: 15 May 2013

Chapter 19. FFTRevised: 15 May 2013

Chapter 20. FIR CompilerRevised: 15 May 2013

Chapter 21. FIR Compiler IIRevised: 15 May 2013

Chapter 22. InterlakenRevised: 15 May 2013

Chapter 23. Interlaken PHYRevised: 1 July 2013

Chapter 24. IP Compiler for PCI ExpressRevised: 15 May 2013

Chapter 25. NCORevised: 15 May 2013

Chapter 26. Nios II ProcessorRevised: 15 May 2013

Chapter 27. PCI CompilerRevised: 15 May 2013

Chapter 28. POS-PHY Level 4Revised: 15 May 2013

Chapter 29. QDR II and QDR II+ SRAM Controller with UniPHYRevised: 15 May 2013

Chapter 30. RapidIORevised: 15 May 2013

Chapter 31. RapidIO IIRevised: 15 May 2013

Chapter 32. Reed-Solomon CompilerRevised: 15 May 2013

Chapter 33. Reed-Solomon IIRevised: 15 May 2013

Chapter 34. RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IPRevised: 15 May 2013


x About These Release NotesChapter Revision Dates

Chapter 35. SDIRevised: 15 May 2013

Chapter 36. SDI IIRevised: 1 July 2013

Chapter 37. SerialLite IIRevised: 15 May 2013

Chapter 38. SerialLite III StreamingRevised: 15 May 2013

Chapter 39. Stratix V Hard IP for PCI ExpressRevised: 1 July 2013

Chapter 40. Triple Speed EthernetRevised: 01 July 2013

Chapter 41. Video and Image Processing SuiteRevised: 15 May 2013

Chapter 42. Viterbi CompilerRevised: 15 May 2013

Chapter 43. XAUI PHYRevised: 1 July 2013


MegaCore IP Library Release Notes and Errata15 May 2013

15 May 2013

1. 10-Gbps Ethernet MAC

Product Revision HistoryTable 1–1 shows the revision history for the 10-Gbps Ethernet (10GbE) MAC MegaCore function.

f For more information about the new features, refer to the 10-Gbps Ethernet MAC MegaCore Function User Guide.

ErrataFor the most recent list of errata for the 10-Gbps Ethernet (10GbE) MAC MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the 10-Gbps Ethernet (10GbE) MAC MegaCore functions.

Table 1–1. 10-Gbps Ethernet MAC MegaCore Function Revision History

Version Date Description

13.0 May 2013

■ Added device support for Arria SoC and Cyclone SoC.

■ Added new 10/100M/1G/10G Ethernet (10M-10GbE) option for Arria V GZ and Stratix V FPGA devices.

■ Added ToD synchronizer feature.

■ Changed the 1G/10GbE MAC with IEEE 1588v2 design example to 10M-10GbE MAC with IEEE 1588v2 design example.

12.1 November 2012

■ Added 1G/10GbE option for Arria V GZ and Stratix V devices.

■ Added IEEE 1588v2 time synchronization option.

■ Added design examples for 10GbE MAC with IEEE 1588v2 and 1G/10GbE MAC with IEEE 1588v2.

12.0 July 2012 Preliminary support for Arria V GT devices.

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=10g_mac_ki

http://www.altera.com/literature/ug/10Gbps_MAC.pdf

http://www.altera.com/literature/ug/10Gbps_MAC.pdf

MegaCore IP Library Release Notes and Errata1 July 2013

1 July 2013

2. 10GBASE-R PHY

Product Revision HistoryTable 2–1 shows the revision history for the 10GBASE-R PHY IP core.

f For more information about the new features, refer to the “10GBASE-R PHY IP Core” chapter in the Altera Transceiver PHY IP Core User Guide.

Table 2–1. 10GBASE-R PHY Revision History

Data Version Description

July 2013 13.0 SP1 Verified in the Quartus II software v13.0 SP1.

May 2013 13.0 Verified in the Quartus II software v13.0.

November 2012 12.1

Added the following new features:

■ Added support for IEEE 1588 Precision Time Protocol.

■ Added Arria V GZ support.

■ The RCLR_BER_COUNT (0x81, bit 3) and HI_BER (0x82, bit 1) register bits for Arria V GZ and Stratix V devices.

June 2012 12.0

■ Added Arria V device support.

■ Added the following QSF settings to all transceiver PHY:

■ XCVR_TX_PRE_EMP_PRE_TAP_USER

■ XCVR_TX_PRE_EMP_2ND_POST_TAP_USER

■ Added 11 new settings for GT transceivers.

■ Added optional pll_locked status signal for Arria V and Stratix V devices.

■ Added optional rx_coreclkin port.

February 2012 11.1 SP2 Verified with the Quartus II software v11.1 SP2.

December 2011 11.1 SP1 Verified with the Quartus II software v11.1 SP1.

November 2011 11.1 Added support for Stratix V devices.

May 2011 11.0 Verified with the Quartus II software v11.0.

December 2010 10.1 Added Stratix V support.

September 2010 10.0 SP1 Added simulation support.

July 2010 10.0 First release.

http://www.altera.com/literature/ug/xcvr_user_guide.pdf

Chapter 2: 10GBASE-R PHY 2–2Errata

Errata

f For a recent list of errata and affected versions of the 10GBASE-R PHY IP Core IP core, refer to the Altera Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 July 2013 Altera Corporation MegaCore IP Library Release Notes and Errata

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=10g_phy_ki


1 July 2013

3. 1G/10GbE and Backplane Ethernet10GBASE-KR PHY

Revision HistoryTable 3–1 shows the revision history for the 1G/10GbE and Backplane Ethernet 10GBASE-KR PHY IP core.

f For more information about the new features, refer to the G1/10 Gbps Ethernet PHY IP Core and Backplane Ethernet 10GBASE-KR PHY IP Core chapters in the Altera Transceiver PHY IP Core User Guide.

ErrataFor the most recent list of errata for the1G/10GbE and 10GBASE-KR PHY IP cores, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

Table 3–1. 10GBASE-KR PHY Revision History

Date Version Description

July 2013 13.0 SP1


■ Forward error correction (FEC)

■ Sync-E support

■ RX equalization

May 2013 13.0

■ Added registers for UNH-IOL testing.

■ Removed reset_ch_bitmask (0x41), reset_control and reset status (0x42) registers.

■ Updated definition of VMAXRULE parameter and updated ber_time default to accommodate this change.

■ Added seq_lt_timeout status bit (0xB0, bit[2].

February 2013 12.1 SP1 ■ Removed Enable SGMII bridge logic parameter. This logic is always enabled.

December 2012 12.0 ■ Initial release.



http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=10gbase_kr_phy_ki


15 May 2013

4. 50G Interlaken

Product Revision HistoryTable 4–1 shows the revision history for the 50G Interlaken MegaCore function.

f For information about the new features, refer to the 50G Interlaken MegaCore Function User Guide.

Errata

1 For the most recent list of errata for the 50G Interlaken MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the 50G Interlaken MegaCore function. Altera recommends upgrading to the latest available version of the MegaCore IP Library.

Table 4–1. 50G Interlaken MegaCore Function Revision History


13.0 May 2013 Initial release.

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=50g_ilaken_ki

http://www.altera.com/literature/ug/ug_50g_interlaken.pdf



15 May 2013

5. 100G Interlaken

Product Revision HistoryTable 5–1 shows the revision history for the 100G Interlaken MegaCore function.

f For information about the new features, refer to the 100G Interlaken MegaCore Function User Guide.

ErrataFor the most recent list of errata for the 100G Interlaken MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the 100G Interlaken MegaCore function.

Table 5–1. 100G Interlaken MegaCore Function Revision History


13.0 May 2013

■ Added dual segment mode.

■ Added packet mode option in parameter editor.

■ Improved error handling.

■ Added PRBS capability.

■ Added CRC-32 error injection capability.

12.1 November 2012 Initial release.




http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=100g_ilaken_ki


15 May 2013

6. 40- and 100-Gbps Ethernet MAC andPHY

Product Revision HistoryTable 6–1 shows the revision history for the 40- and 100-Gbps Ethernet MAC and PHY.

f For more information about the new features, refer to the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide.

ErrataFor the most recent list of errata for the 40- and 100-Gbps Ethernet MAC and PHY MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

Table 6–1. 40- and 100-Gbps Ethernet MAC and PHY Revision History


May 2013 13.0■ Added preamble pass-through option

■ Added transmitter average inter-packet gap (IPG) adjustment option

December 2012 12.1 Maintenance release.

June 2012 12.0 First release.

http://www.altera.com/literature/ug/ug_40_100gbe.pdf

http://www.altera.com/literature/ug/ug_40_100gbe.pdf

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=40_100gbe_mac_phy_ki


15 May 2013

7. 8B10B Encoder/Decoder

Product Revision HistoryTable 7–1 shows the revision history for the 8B10B Encoder/Decoder MegaCore function.

f For more information about the new features, refer to the 8B10B Encoder/Decoder MegaCore Function User Guide.

Obsolescence Notice

c The 8B10B Encoder/Decoder MegaCore function is scheduled for product obsolescence and discontinued support as described in PDN1304. Therefore, Altera does not recommend use of this IP in new designs. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

ErrataFor the most recent list of errata for the 8B10B Encoder/Decoder MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the 8B10B Encoder/Decoder MegaCore function.

Table 7–1. 8B10B Encoder/Decoder MegaCore Function Revision History


13.0 Maya 2013 Verified in the Quartus II software v13.0.

12.1 November 2012 Verified in the Quartus II software v12.1.

12.0 July 2011 Verified in the Quartus II software v12.0.

http://www.altera.com/literature/ug/ug_ed8b10b.pdf

http://www.altera.com/literature/ug/ug_ed8b10b.pdf

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=rio_ki

http://www.altera.com/literature/pcn/pdn1304.pdf

http://www.altera.com/products/ip/ipm-index.html


1 July 2013

8. Arria V GZ Hard IP for PCI Express

Product Revision HistoryTable 8–1 shows the revision history for the Arria V GZ Hard IP for PCI Express.

f For more information about the new features, refer to the Arria V GZ Hard IP for PCI Express User Guide.

Errata

f For a recent list of errata and affected versions of the Arria V Hard IP for PCI Express IP core, refer to the Altera Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

Table 8–1. Arria V GZ Hard IP for PCI Express Revision History



May 2013 13.0


■ Support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Space and support multiple functions

■ Preliminary support for a Avalon-MM 256-Bit Hard IP for PCI Express that is capable of running at the Gen3 ×8 data rate.

■ Support for 64-bit address in the Avalon-MM Hard IP for PCI Express IP Core,

February 2013 12.1 SP1 Added Gen3 PIPE simulation support.

November 2012 12.1 Initial release.

http://www.altera.com/literature/ug/ug_a5gz_pcie.pdf

http://www.altera.com/literature/ug/ug_a5gz_pcie.pdf

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=pcie_av_gz_ki


1 July 2013

9. Arria V Hard IP for PCI Express

Product Revision HistoryTable 9–1 shows the revision history for the Arria V Hard IP for PCI Express.

f For more information about the new features, refer to the Arria V Hard IP for PCI Express User Guide.

ErrataFor a recent list of errata and affected versions of the Arria V Hard IP for PCI Express IP core, refer to the Altera Knowledge Base web page.

Table 9–1. Arria V Hard IP for PCI Express Revision History



May 2013 13.0 Added ×2 support.

November 2012 12.1


■ Root Port support for Avalon-MM Hard IP for PCI Express.

■ Multiple MSI and MSI-X messages for the Avalon-MM Hard IP for PCI Express.

■ Revised example design including the Transceiver Reconfiguration Controller Qsys component and a driver for this component.

Additional changes in the 12.1 release:

■ busy_xcvr_reconfig is no longer a top-level signal of the IP core.

■ You must include the Transceiver Reconfiguration Controller IP Core in your design to compensate for variations due to process, voltage, and temperature (PVT) in 28-nm devices.

■ When opening an existing 12.0 Qsys design using the Avalon-MM interface, all base address registers (BARs) will be disabled in 12.1. You should re-enable each used BAR before regenerating in 12.1.

For more information, refer to the important Changes in the 12.1 Release in the Arria V Hard IP for PCI Express User Guide.

Although the user guide describes CvP as an optional feature, CvP is not available in the 12.1 release.

June 2012 12.0

■ Added ×1, ×4, and ×8 Gen1 support for Endpoints using the Avalon-MM interface

■ Added ×1 and ×4 Gen2 support for Endpoints using the Avalon-MM interface

■ Added support for dynamic reconfiguration of transceiver settings

■ Added support for VHDL simulation



November 2011 11.1 First release.

http://www.altera.com/literature/ug/ug_a5_pcie.pdf


http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=pcie_a5_ki




15 May 2013

10. ASI

Product Revision HistoryTable 10–1 shows the revision history for the ASI MegaCore function.

f For more information about the new features, refer to the ASI MegaCore Function User Guide.

ErrataFor the most recent list of errata for the ASI MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the ASI MegaCore function.

Table 10–1. ASI MegaCore Function Revision History


13.0 May 2013 Verified in the Quartus II software v13.0.



11.1 November 2011 Maintenance release.

http://www.altera.com/literature/ug/ug_asi.pdf

http://www.altera.com/literature/ug/ug_asi.pdf

www.altera.com/support/kdb/kdb-browse.jsp?keyword=asi_ki

www.altera.com/support/kdb/kdb-browse.jsp?keyword=asi_ki


15 May 2013

11. CIC

Product Revision HistoryTable 11–1 shows the revision history for the CIC MegaCore function.

f For information about the new features, refer to the CIC MegaCore Function User Guide.

ErrataFor the most recent list of errata for the CIC MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

Table 11–1. CIC MegaCore Function Revision History





http://www.altera.com/literature/ug/ug_cic.pdf

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=cic_ki

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=cic_ki


15 May 2013

12. CPRI

Product Revision HistoryTable 12–1 shows the revision history for the CPRI MegaCore function.

f For information about the new features, refer to the CPRI MegaCore Function User Guide.

Errata

1 For the most recent list of errata for the CPRI MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the CPRI MegaCore function. Altera recommends upgrading to the latest available version of the MegaCore IP Library.

Table 12–1. CPRI MegaCore Function Revision History


13.0 May 2013

■ Added new parameter for user control of inclusion or exclusion of software interface to full control words.

■ Added new parameter for user control of inclusion or exclusion of round-trip delay calibration feature.

■ Reduced resource utilization in 28-nm devices.

12.1 SP1 February 2013■ Added support for CPRI line rate and autorate negotiation up to 9.8304 Gbps in Arria V GZ

devices.

■ Added support for autorate negotiation up to 9.8304 Gbps in Arria V GT devices.

12,1 November 2012

■ Added support for CPRI line rates and autorate negotiation up to 3.072 Gbps in Cyclone V GX devices.

■ Added support for CPRI line rates and autorate negotiation up to 6.144 Gbps in Arria V GZ devices.

■ Added dynamic switching between slave and master operation modes. Support includes new field in CPRI_CONFIG register.

■ Added support for slave operation mode self-bringup with no connection to CPRI master, to support link synchronization testing in slave operation mode.

■ Added access to full control words through software interface at all CPRI line rates. Support includes modifications to the CPRI_CTRL_INDEX, CPRI_RX_CTRL, and CPRI_TX_CTRL registers.

12.0 June 2012

■ Added CPRI line rate of 9.8304 Gbps in Arria V GT and Stratix V devices.

■ Added support for autorate negotiation up to 6.144 Gbps in Arria V devices.

■ Added support for autorate negotiation up to 9.8 Gbps in Stratix V devices.

■ Added new parameter to specify inclusion or exclusion of an HDLC block.

■ Added new parameter to specify the MAP interface mapping mode.

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=cpri_ki

http://www.altera.com/literature/ug/ug_cpri.pdf

http://www.altera.com/literature/ug/ug_cpri.pdf


15 May 2013

13. CRC Compiler

Product Revision HistoryTable 13–1 shows the revision history for the CRC Compiler.

f For more information about the new features, refer to the CRC Compiler User Guide.

Obsolescence Notice

c The CRC Compiler is scheduled for product obsolescence and discontinued support as described in PDN1304. Therefore, Altera does not recommend use of this IP in new designs. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

ErrataFor the most recent list of errata for the CRC Compiler, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the CRC Compiler.

Table 13–1. CRC Compiler Revision History





http://www.altera.com/literature/ug/ug_crc.pdf

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=crc_ki




1 July 2013

14. Cyclone V Hard IP for PCI Express

Product Revision HistoryTable 14–1 shows the revision history for the Cyclone V Hard IP for PCI Express.

f For more information about the new features, refer to the Cyclone V Hard IP for PCI Express User Guide.

Table 14–1. Cyclone V Hard IP for PCI Express Revision History



May 2013 13.0 Added ×2 support.

November 2012 12.1









For more information, refer to the important Changes in the 12.1 Release in the Cyclone V Hard IP for PCI Express User Guide.

Although the user guide describes CvP as an optional feature, CvP is not available in the 12.1 release.

June 2012 12.0

■ Added ×1, ×4, and ×8 Gen1 support for Endpoints using the Avalon-MM interface

■ Added ×1 and ×4 Gen2 support for Endpoints using the Avalon-MM interface

■ Added support for dynamic reconfiguration of transceiver settings

■ Added support for VHDL simulation



November 2011 11.1 First release.

http://www.altera.com/literature/ug/ug_c5_pcie.pdf

http://www.altera.com/literature/ug/ug_c5_pcie.pdf

http://www.altera.com/literature/ug/ug_s5_pcie.pdf


Chapter 14: Cyclone V Hard IP for PCI Express 14–2Errata

Errata

f For a recent list of errata and affected versions of the Cyclone V Hard IP for PCI Express IP core, refer to the Altera Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.


http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=pcie_cv_ki


15 May 2013

15. DDR and DDR2 SDRAM Controllerswith ALTMEMPHY IP

Product Revision HistoryTable 15–1 shows the revision history for the DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP MegaCore function.

f For more information about the new features, refer to the External Memory Interface Handbook.

Obsolescence Notice

c The DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP for Stratix III and Stratix IV devices is scheduled for product obsolescence and discontinued support, with last ship date the Quartus II software 13.0 release. Therefore, Altera does not recommend use of this IP in new designs. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

ErrataFor the most recent list of errata for the DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP MegaCore function.

Table 15–1. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP MegaCore Function Revision History


13.0 May 2013 Verified with the Quartus II software v13.0

12.1 November 2012 Verified with the Quartus II software v12.1

12.0 June 2012 Verified with the Quartus II software v12.0

11.1 SP2 February 2012 Verified with the Quartus II software v11.1 SP2

http://www.altera.com/literature/hb/external-memory/emi.pdf


http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=ddr2_alt_ki


15 May 2013

16. DDR3 SDRAM Controller withALTMEMPHY IP

Product Revision HistoryTable 16–1 shows the revision history for the DDR3 SDRAM Controller with ALTMEMPHY IP MegaCore function.


Obsolescence Notice

c The DDR3 SDRAM Controller with ALTMEMPHY IP for Stratix III and Stratix IV devices is scheduled for product obsolescence and discontinued support, with last ship date the Quartus II software 13.0 release. Therefore, Altera does not recommend use of this IP in new designs. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

ErrataFor the most recent list of errata for the DDR3 SDRAM Controller with ALTMEMPHY IP MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the DDR3 SDRAM Controller with ALTMEMPHY IP MegaCore function.

Table 16–1. DDR3 SDRAM Controller with ALTMEMPHY IP MegaCore Function Revision History



12.1 November 2012 Verified with the Quartus II software v12.1


11.1 SP2 February 2012 Verified with the Quartus II software v11.1 SP2


http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=ddr3_alt_ki



15 May 2013

17. DDR2, DDR3, and LPDDR2 SDRAMController with UniPHY

Product Revision HistoryTable 17–1 shows the revision history for the DDR2 and DDR3 SDRAM Controller with UniPHY IP core.


ErrataFor the most recent list of errata for the DDR2, DDR3, and LPDDR2 SDRAM Controller with UniPHY IP core, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

Table 17–1. DDR2 and DDR3 SDRAM Controller with UniPHY Revision History



12.1 November 2012

■ Added EMIF On-Chip Debug Toolkit for 28 nm families with Nios II-based sequencer

■ Added Arria V GZ support for DDR2 and DDR3

■ Added Ping Pong PHY for quarter-rate DDR3 designs on Stratix V and Arria V GZ devices

■ Added 933 MHz DDR3 support for selected Stratix V C1 and C2 devices

■ Added simulation and compilation support for soft interfaces on Arria V SoC devices for DDR2 and DDR3

■ Added simulation support for HPS interfaces on Arria V SoC devices for DDR3 and LPDDR2

■ Added simulation, compilation, and timing closure support for soft interfaces on Cyclone V SoC devices, for DDR2 and DDR3

■ Added simulation, compilation, and timing closure support for hard interfaces on Cyclone V SoC devices, for DDR3

■ Added simulation and compilation support for HPS interfaces on Cyclone V devices, for DDR2, DDR3, and LPDDR2

12.0 June 2012

■ Added LPDDR2 support

■ Added shadow register support

■ Added new EMIF Toolkit

■ Added compilation support for Arria V soft interfaces

■ Added compilation support for Cyclone V soft and hard interfaces

11.1 SP2 February 2012

■ Added POF support for Stratix V 800MHz DDR3

■ Added EMIF Toolkit support for Stratix V

■ Added automatic dynamic tracking for frequencies above 533MHz

■ Added compilation support for Cyclone V hard memory interface



http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=ddr2_uni_ki

Chapter 17: DDR2, DDR3, and LPDDR2 SDRAM Controller with UniPHY 17–2Errata

1 Not all issues affect all versions of the DDR2, DDR3, and LPDDR2 SDRAM Controller with UniPHY IP core.

15 May 2013 Altera Corporation MegaCore IP Library Release Notes and Errata


15 May 2013

18. DisplayPort

Product Revision HistoryTable 18–1 shows the revision history for the DisplayPort MegaCore function.

f For information about the new features, refer to the DisplayPort MegaCore Function User Guide.

Errata

1 For the most recent list of errata for the DisplayPort MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the DisplayPort MegaCore function. Altera recommends upgrading to the latest available version of the MegaCore IP Library.

Table 18–1. DisplayPort MegaCore Function Revision History


13.0 May 2013 Initial release.

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=dp_ki

http://www.altera.com/literature/ug/ug_displayport.pdf

http://www.altera.com/literature/ug/ug_displayport.pdf


15 May 2013

19. FFT

Product Revision HistoryTable 19–1 shows the revision history for the FFT MegaCore function.

f For more information about the new features, refer to the FFT MegaCore Function User Guide.

ErrataFor the most recent list of errata for the FFT MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the FFT MegaCore function.

Table 19–1. FFT MegaCore Function Revision History


13.0 May 2013 Updated bit-accurate model to work with both 32-bit and 64-bit versions of MATLAB software.

12.1 November 2012 Support for Arria V GZ devices.


http://www.altera.com/search?q=fft_ki&output=xml_no_dtd&sort=date%3AD%3AL%3Ad1&client=www_frontend&proxystylesheet=www_frontend&ie=UTF-8&oe=UTF-8&mode=production&entqr=3&entsp=a&ud=1&site=www_spt_kdb

www.altera.com/literature/ug/ug_fft.pdf

www.altera.com/literature/ug/ug_fft.pdf


15 May 2013

20. FIR Compiler

Revision HistoryTable 20–1 shows the revision history for the FIR Compiler.

f For information about the new features, refer to the FIR Compiler User Guide.

ErrataFor the most recent list of errata for the FIR Compiler, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the FIR Compiler.

Table 20–1. FIR Compiler Revision History





http://www.altera.com/literature/ug/fircompiler_ug.pdf

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=fir_ki


15 May 2013

21. FIR Compiler II

Product Revision HistoryTable 21–1 shows the revision history for the FIR Compiler II.

f For information about the new features, refer to the FIR Compiler II User Guide.

Errata

f For the most recent list of errata for the FIR Compiler II, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the FIR Compiler II.

Table 21–1. FIR Compiler II Revision History





http://www.altera.com/literature/ug/ug_fir_compiler_ii.pdf

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=fir_ii_ki


15 May 2013

22. Interlaken

Product Revision HistoryTable 22–1 shows the revision history for the Interlaken MegaCore function.

f For information about the new features, refer to the Interlaken MegaCore Function User Guide.

Errata

f For a current list of errata that affect the Interlaken MegaCore function, refer to the Knowledge Base web page.

1 Not all issues affect all versions of the Interlaken MegaCore function.

f For Qsys errata, which might affect the Interlaken MegaCore function and other IP cores, refer to the Quartus II Software Release Notes.

Table 22–1. Interlaken MegaCore Function Revision History




12.0 June 2012 Maintenance release.

http://www.altera.com/literature/ug/ug_interlaken.pdf

http://www.altera.com/literature/ug/ug_interlaken.pdf

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=ilaken_ki

http://www.altera.com/literature/rn/rn_qts.pdf


1 July 2013

23. Interlaken PHY

Revision HistoryTable 23–1 shows the revision history for the Interlaken PHY IP core.

f For more information about the new features, refer to the “Interlaken PHY IP Core” chapter in the Altera Transceiver PHY IP Core User Guide.

ErrataFor the most recent list of errata for the Interlaken PHY IP core, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

Table 23–1. Interlaken PHY Revision History



May 2013 13.0 ■ Changed RX equalization registers from read only to read and write.

November 2012 12.1

■ Added Arria V GZ support.

■ Added 12500 Mbps lane rate.

■ Removed recommendation to use /40 for tx_user_clkout and rx_coreclkin. Data rates between /40 and /67 all work reliably.

June 2012 12.0

■ Added support for custom, user-defined, data rates.

■ Added the following QSF settings for all transceivers:






http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=ilaken_phy_ki

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=ilaken_phy_ki


15 May 2013

24. IP Compiler for PCI Express

Product Revision HistoryTable 24–1 shows the revision history for the IP Compiler for PCI Express.

f For complete information about the new features, refer to the IP Compiler for PCI Express User Guide.

ErrataFor the most recent list of errata for the IP Compiler for PCI Express, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the IP Compiler for PCI Express.

Table 24–1. IP Compiler for PCI Express Revision History




12.0 June 2012 Maintenance release.

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=pcie_ki

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=pcie_ki

http://www.altera.com/literature/ug/ug_pci_express.pdf




https://www.altera.com/servlets/subscriptions/alert?id=UG-00000


15 May 2013

25. NCO

Product Revision HistoryTable 25–1 shows the revision history for the NCO MegaCore function.

f For information about the new features, refer to the NCO MegaCore Function User Guide.

ErrataFor the most recent list of errata for the NCO MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the NCO MegaCore function.

Table 25–1. NCO MegaCore Function Revision History





http://www.altera.com/literature/ug/ug_nco.pdf

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=nco_ki

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=nco_ki


15 May 2013

26. Nios II Processor

f For the most recent list of errata for the Nios® II processor core, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

Product Revision HistoryTable 26–1 shows the revision history for the Nios II Processor MegaCore function.

f For more information about the new features, refer to the Nios II Processor Reference Handbook. For information about new features and errata in the Nios II Embedded Design Suite, refer to the Nios II Embedded Design Suite Release Notes.

Table 26–1. Nios II Processor Revision History



12.1 December 2012 Verified with the Quartus II software v12.1


http://www.altera.com/literature/hb/nios2/n2cpu_nii5v1.pdf

http://www.altera.com/literature/hb/nios2/n2cpu_nii5v1.pdf

http://www.altera.com/search?output=xml_no_dtd&filter=0&sort=date%3AD%3AL%3Ad1&client=www_frontend&proxystylesheet=www_frontend&ie=UTF-8&oe=UTF-8&site=www_spt_kdb&mode=production&q=nios_ii_ki

http://www.altera.com/literature/rn/rn_nios2eds.pdf


15 May 2013

27. PCI Compiler

Product Revision HistoryTable 27–1 shows the revision history for the PCI Compiler.

f For more information about the new features, refer to the PCI Compiler User Guide.

Obsolescence Notice

c The PCI Compiler MegaCore functions pci_mt64 and pci_t64 are scheduled for product obsolescence and discontinued support as described in PDN1304. Therefore, Altera does not recommend use of this IP in new designs. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

ErrataFor the most recent list of errata for the PCI Compiler, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the PCI Compiler.

Table 27–1. PCI Compiler Revision History






http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=pci_ki

http://www.altera.com/literature/ug/ug_pci.pdf



15 May 2013

28. POS-PHY Level 4

Product Revision HistoryTable 28–1 shows the revision history for the POS-PHY Level 4 MegaCore function.

f For more information about the new features, refer to the POS-PHY Level 4 MegaCore Function User Guide.

ErrataFor the most recent list of errata for the POS-PHY Level 4 MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

The following sections addresses known errata and documentation issues for the POS-PHY Level 4 MegaCore function. Errata are functional defects or errors, which may cause the POS-PHY Level 4 MegaCore function to deviate from published specifications. Documentation issues include errors, unclear descriptions, or omissions from current published specifications or product documents.

1 Not all issues affect all versions of the POS-PHY Level MegaCore function.

Table 28–1. POS-PHY Level 4 MegaCore Function Revision History



December 2012 12.1 Verified with the Quartus II software v12.1.

June 2012 12.0 Verified with the Quartus II software v12.0.

www,altera.com/literature/ug/ug_posphy4.pdf

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=pl4_ki


15 May 2013

29. QDR II and QDR II+ SRAM Controllerwith UniPHY

Product Revision HistoryTable 29–1 shows the revision history for the QDR II and QDR II+ SRAM Controller with UniPHY.


ErrataFor the most recent list of errata for the QDR II and QDR II+ SRAM Controller with UniPHY IP core, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the QDR II and QDR II+ SRAM Controller with UniPHY IP core.

Table 29–1. QDR II and QDR II+ SRAM Controller with UniPHY Revision History



12.1 November 2012■ Added EMIF On-Chip Debug Toolkit for 28 nm families with Nios II-based sequencer

■ Added simulation and compilation support for soft interfaces on Arria V SoC devices

12.0 June 2012 Added new EMIF Toolkit

11.1 SP2 February 2012 Added EMIF Toolkit support for Stratix V



http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=qdrii_uni_ki


15 May 2013

30. RapidIO

Product Revision HistoryTable 30–1 shows the revision history for the RapidIO MegaCore function.

f For more information about the new features, refer to the RapidIO MegaCore Function User Guide.

ErrataFor the most recent list of errata for the RapidIO MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the RapidIO MegaCore function. Altera recommends upgrading to the latest available version of the MegaCore IP Library.

Table 30–1. RapidIO MegaCore Function Revision History


13.0 May 2013 ■ Added 2x mode for Arria V, Cyclone V, and Stratix V devices.

12.1 November 2012 ■ Added support for Arria V GZ, Arria V SoC, and Cyclone V SoC devices.

12.0 June 2012 ■ Added support for Cyclone V GT x1 variation at 5.0 Gbaud.

www.altera.com/literature/ug/ug_rapidio.pdf

www.altera.com/literature/ug/ug_rapidio.pdf

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=rio_ki


15 May 2013

31. RapidIO II

Product Revision HistoryTable 31–1 shows the revision history for the RapidIO II MegaCore function.

f For information about the new features, refer to the RapidIO II MegaCore Function User Guide.

ErrataFor the most recent list of errata for the RapidIO II MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the RapidIO II MegaCore function.

Table 31–1. RapidIO II MegaCore Function Revision History



12.1 SP1 February 2013

■ Added device programming support for Arria V devices.

■ Added support for Arria V GZ devices.

■ Added support for Cyclone V devices. Cyclone V GT devices support rates up to 5.0 Gbaud, and other Cyclone V devices support rates up to 3.125 Gbaud.

12.1 November 2012 Initial release.

http://www.altera.com/literature/ug/ug_rapidio2.pdf




http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=rio2_ki

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=rio2_ki


15 May 2013

32. Reed-Solomon Compiler

Product Revision HistoryTable 32–1 shows the revision history for the Reed-Solomon Compiler.

f For more information about the new features, refer to the Reed-Solomon Compiler User Guide.

ErrataFor the most recent list of errata for the Reed-Solomon Compiler, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the Reed-Solomon Compiler.

Table 32–1. Reed-Solomon Compiler Revision History





www.altera.com/literature/ug/rs-compiler_ug.pdf

www.altera.com/literature/ug/rs-compiler_ug.pdf

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=rs_ki

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=rs_ki


15 May 2013

33. Reed-Solomon II

Product Revision HistoryTable 33–1 shows the revision history for Reed-Solomon II.

f For information about the new features, refer to the Reed-Solomon II MegaCore Function User Guide.

ErrataFor the most recent list of errata for the Reed-Solomon II, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the Reed-Solomon II.

Table 33–1. Reed-Solomon II Revision History





http://www.altera.com/literature/ug/ug_rsii.pdf

http://www.altera.com/literature/ug/ug_rsii.pdf

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=rs_ii_ki


15 May 2013

34. RLDRAM II Controller with UniPHYand RLDRAM 3 PHY-Only IP

Product Revision HistoryTable 34–1 shows the revision history for the RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP.


ErrataFor the most recent list of errata for the RLDRAM II Controller with UniPHY IP and the RLDRAM 3 PHY-Only IP, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the RLDRAM II Controller with UniPHY IP and RLDRAM 3 PHY-Only IP.

Table 34–1. RLDRAM II Controller with UniPHY Revision History



12.1 November 2012

■ Added RLDRAM 3 PHY-Only IP

■ Added EMIF On-Chip Debug Toolkit for 28 nm families with Nios II-based sequencer

■ Added simulation and compilation support for soft interfaces on Arria V SoC devices for RLDRAM II

12.0 June 2012 Added new EMIF Toolkit

11.1 SP2 February 2012 Added EMIF Toolkit support for Stratix V



http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=rldram_ii_uni_ki


15 May 2013

35. SDI

Product Revision HistoryTable 35–1 shows the revision history for the SDI MegaCore function.

f For more information about the new features, refer to the SDI MegaCore Function User Guide.

ErrataFor the most recent list of errata for the SDI MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the SDI MegaCore function.

Table 35–1. SDI MegaCore Function Revision History




12.0 July 2011 Preliminary support for multiple-rate SDI in Arria V devices.

www.altera.com/literature/ug/ug_sdi.pdf

www.altera.com/literature/ug/ug_sdi.pdf

http://www.altera.com/search?output=xml_no_dtd&filter=0&sort=date%3AD%3AL%3Ad1&client=www_frontend&proxystylesheet=www_frontend&ie=UTF-8&oe=UTF-8&site=www_spt_kdb&mode=production&q=sdi_ki


1 July 2013

36. SDI II

Product Revision HistoryTable 36–1 shows the revision history for the SDI II MegaCore function.

f For more information about the new features, refer to the SDI II MegaCore Function User Guide.

ErrataFor the most recent list of errata for the SDI II MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the SDI II MegaCore function.

Table 36–1. SDI II MegaCore Function Revision History


13.0 SP1 July 2013■ Added Tx PLL dynamic switching feature.

■ Added SD Interface Bit Width parameter.

13.0 May 2013

■ Preliminary support for Cyclone V devices.

■ Added 20-bit interface for SD-SDI standard.

■ Added RP168 switching feature.

12.1 November 2012 Preliminary support for Arria V and Stratix V devices.

http://www.altera.com/literature/ug/ug_sdi_ii.pdf

http://www.altera.com/literature/ug/ug_sdi_ii.pdf

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=sdi_ii_ki


15 May 2013

37. SerialLite II

Product Revision HistoryTable 37–1 shows the revision history for the SerialLite II MegaCore function.

f For more information about the new features, refer to the SerialLite II MegaCore Function User Guide.

ErrataFor the most recent list of errata for the SerialLite II MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the SerialLite II MegaCore function.

Table 37–1. SerialLite II MegaCore Function Revision History


13.0 May 2013 Added support for Arria V GZ and Cyclone V devices.

12.1 November 2012 Verified in the Quartus II software v12.1

http://www.altera.com/literature/ug/ug_slite2.pdf

http://www.altera.com/literature/ug/ug_slite2.pdf

www.altera.com/support/kdb/kdb-browse.jsp?keyword=sl_ii_ki


15 May 2013

38. SerialLite III Streaming

Product Revision HistoryTable 38–1 shows the revision history for the SerialLite III Streaming MegaCore function.

f For information about the new features, refer to the SerialLite III Streaming MegaCore Function User Guide.

Errata

1 For the most recent list of errata for the SerialLite III Streaming MegaCore function, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the SerialLite III Streaming MegaCore function. Altera recommends upgrading to the latest available version of the MegaCore IP Library.

Table 38–1. SerialLite III Streaming MegaCore Function Revision History


13.0 May 2013 First release.

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=sl_iii_streaming_ki

http://www.altera.com/literature/ug/ug_slite3_streaming.pdf

http://www.altera.com/literature/ug/ug_slite3_streaming.pdf


1 July 2013

39. Stratix V Hard IP for PCI Express

Product Revision HistoryTable 39–1 shows the revision history for the Stratix V Hard IP for PCI Express.

f For more information about the new features, refer to the Stratix V Hard IP for PCI Express User Guide.

Table 39–1. Stratix V Hard IP for PCI Express Revision History



May 2013 13.0


■ Support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Space and support multiple functions

■ Preliminary support for a Avalon-MM 256-Bit Hard IP for PCI Express that is capable of running at the Gen3 ×8 data rate.

■ Support for 64-bit address in the Avalon-MM Hard IP for PCI Express IP Core,

February 2013 12.1 SP1 Added Gen3 PIPE simulation support.

November 2012 12.1



■ Native ×2 support.





■ rxfc_cplbuf_ovf is a new optional status signal.



For more information, refer to the important Changes in the 12.1 Release in the Stratix V Hard IP for PCI Express User Guide.

July 2012 12.0


■ Avalon-MM single dword variant.

■ Programmer Object File (.pof) support for Stratix V devices.

■ Gen3 ×1 and ×4 support for Avalon-MM Endpoints.

■ C4 speed grade for all variants except Gen3 ×8 and Gen3 ×4 with 128-bit interface.

■ C1 speed grade is available for all variants.






Chapter 39: Stratix V Hard IP for PCI Express 39–2Errata

Errata

f For a recent list of errata and affected versions of the Stratix V Hard IP for PCI Express IP core, refer to the Altera Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.


November 11.1


■ Support for x1, x4, and x8 Gen3 variants with the Avalon-ST interface

■ Support for x1, x4, and x8 Gen1 and Gen2 variants with the Avalon-MM interface

■ Support for multiple packets per cycle when using the 256-bit interface

■ Added .pof support for Stratix V ES devices for Gen1 and Gen2

July 2011 11.0 SP1 Verified with the Quartus II software v11.0 SP1.

May 2011 11.0 First release

Table 39–1. Stratix V Hard IP for PCI Express Revision History



http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=pcie_sv_ki


01 July 2013

40. Triple Speed Ethernet

Product Revision HistoryTable 40–1 shows the revision history for the Triple Speed Ethernet MegaCore function.

f For more information about the new features, refer to the Triple Speed Ethernet MegaCore Function User Guide.

ErrataFor a recent list of errata for the Triple Speed Ethernet MegaCore function, refer to the AlteraKnowledge Base web page. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the Triple Speed Ethernet MegaCore function.

Table 40–1. Triple Speed Ethernet MegaCore Function Revision History


13.0 SP1 July 2013 Added TX PLL clock network option for Arria V and Cyclone V devices.

13.0 May 2013

■ Added a new testbench flow.

■ Created a unified model for Qsys and standalone flow.

■ Enhanced the timing constraint files (.sdc).

■ Enhanced the simulation model—generated using IEEE simulation encryption.

■ Reorganized the core configuration and FIFO option parameters in the parameter editor.

12.1 November 2012 Added IEEE 1588v2 time synchronization option.

12.0 June 2012 Preliminary support for Cyclone V devices.

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=tse_ki

http://www.altera.com/literature/ug/ug_ethernet.pdf

http://www.altera.com/literature/ug/ug_ethernet.pdf


15 May 2013

41. Video and Image Processing Suite

Product Revision HistoryTable 41–1 shows the revision history of the Video and Image Processing Suite MegaCore functions.

f For information about the new features, refer to the Video and Image Processing Suite User Guide.

Obsolescence Notice

c The Clipper MegaCore function is scheduled for product obsolescence and discontinued support, with last ship date the Quartus II software 13.0 release. Therefore, Altera does not recommend use of this IP in new designs. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

Errata

f For the most recent list of errata for the Video and Image Processing Suite MegaCore functions, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the Video and Image Processing Suite MegaCore functions.

Table 41–1. Video and Image Processing Suite Revision History


13.0 May 2013■ Added two new MegaCore functions: Broadcast Deinterlacer and Clipper II.

■ Removed and discontinued support for the Scaler MegaCore function.

12.1 November 2012■ Rewritten Deinterlacer II MegaCore Function IP core’s High Quality mode with a new

Sobel edge detection-based algorithm

■ Added figure of Deinterlacer II MegaCore Function HQ mode Zoneplate 12.0 and 12.1.

12.0 July 2012■ Added Avalon® Streaming (Avalon-ST) Video Monitor MegaCore Function.

■ Added Trace System MegaCore Function.

http://www.altera.com/literature/ug/ug_vip.pdf


http://www.altera.com/search?q=vip_ki&output=xml_no_dtd&sort=date%3AD%3AL%3Ad1&client=www_frontend&proxystylesheet=www_frontend&ie=UTF-8&oe=UTF-8&mode=production&site=www_spt_kdb&entqr=3&entsp=a&ud=1


15 May 2013

42. Viterbi Compiler

Revision HistoryTable 42–1 shows the revision history for the Viterbi Compiler.

f For more information about the new features, refer to the Viterbi Compiler User Guide.

ErrataFor the most recent list of errata for the Viterbi Compiler, refer to the Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

1 Not all issues affect all versions of the Viterbi Compiler.

Table 42–1. Viterbi Compiler Revision History





www.altera.com/literature/ug/ug_viterbi-compiler.pdf

http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=vit_ip_ki


1 July 2013

43. XAUI PHY

Product Revision HistoryTable 43–1 shows the revision history for the XAUI PHY IP core.

f For more information about the new features, refer to the “XAUI PHY IP Core” chapter in the Altera Transceiver PHY IP Core User Guide.

Errata

f For a recent list of errata and affected versions of the XAUI PHY IP Core IP core, refer to the Altera Knowledge Base page of the Altera website. Also, you can use the Knowledge Base to search for errata based on the product version affected and other criteria.

Table 43–1. XAUI PHY Revision History



May 2013 13.0 Verified in the Quartus II software v13.0.

November 2012 12.1■ Added Arria V GZ support.

■ Added constraint for tx_digitalreset when TX PCS uses bonded clocks.

June 2012 12.0

Added the following QSF settings to all transceiver PHY:




November 2011 11.1 Added base data rate, lane rate, input clock frequency, and PLL type parameters.

May 2011 11.0 Added support for DXAUI. Added support for Arria II GZ and HardCopy IV.


http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=xaui_phy_ki


Additional Information

This chapter provides additional information about the document and Altera.

How to Contact AlteraTo locate the most up-to-date information about Altera products, refer to the following table.

Typographic ConventionsThe following table shows the typographic conventions this document uses.

Contact (1) Contact Method Address

Technical support Website www.altera.com/support

Technical trainingWebsite www.altera.com/training

Email [email protected]

Product literature Website www.altera.com/literature

Nontechnical support (general) Email [email protected]

(software licensing) Email [email protected]

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.

Visual Cue Meaning

Bold Type with Initial Capital Letters

Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI.

bold typeIndicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file.

Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.

italic typeIndicates variables. For example, n + 1.

Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file.

Initial Capital Letters Indicate keyboard keys and menu names. For example, the Delete key and the Options menu.

“Subheading Title” Quotation marks indicate references to sections in a document and titles of Quartus II Help topics. For example, “Typographic Conventions.”


http://www.altera.com/support

http://www.altera.com/training

mailto:[email protected]

http://www.altera.com/literature/



Info–2 Additional InformationTypographic Conventions

Courier type

Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. The suffix n denotes an active-low signal. For example, resetn.

Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.

Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI).

r An angled arrow instructs you to press the Enter key.

1., 2., 3., anda., b., c., and so on

Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.

■ ■ ■ Bullets indicate a list of items when the sequence of the items is not important.

1 The hand points to information that requires special attention.

h The question mark directs you to a software help system with related information.

f The feet direct you to another document or website with related information.

m The multimedia icon directs you to a related multimedia presentation.

c A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.

w A warning calls attention to a condition or possible situation that can cause you injury.

The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents.

Visual Cue Meaning


https://www.altera.com/subscriptions/email/signup/eml-index.jsp

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