meeting 1 - electrical engineering and computer science · computing and displaying spectra in real...

Meeting 1

Summer 2009 Doing DSP Workshop

Coordinators: Kurt Metzger (metzger), EECS 4236

Chih-Wei Wang (wangcw), EECS 4107.

Focus: Doing DSP using TI MSP430 and Piccolo MCUs and

the Xilinx Spartan FPGAs.

Today: ◮ discuss workshop content,◮ introduce the FPGAs and MCUs to be used.

One must learn by doing the thing; for though you think you know it, you have no certainty,until you try. — Sophocles

Doing DSP Workshop – Summer 2009 Meeting 1 – /46 Tuesday – May 5, 2009

The Workshop

◮ A major goal is to put theory into practice.

◮ Intended to provide a structured environment for gaining

experience in devising and implementing digital signal

processing hardware and software.

◮ Will focus on the use of low cost evaluation boards,

associated development tools and software. Items that an

individual could reasonably purchase and use for self study.

◮ The first part of the workshop will focus on the selected

MCUs and FPGA and their associated development tools.

The second part of the workshop will be devoted to doing

one or more projects.

◮ Having an entrepreneurial outlook is encouraged.

◮ Open to all comers. Having taken EECS 216 and/or EECS

280 will be helpful.


Required background

None.

Having programming skills would be useful.

Knowing basic linear systems would be helpful.

Hopefully you will have more background after the workshop

than you had prior to the workshop.


Finding a purpose

To learn, to hone skills, to accomplish.

Sometimes it’s not clear what the purpose of a particular course it.

There is one. The resources needed have been justified. Each brick in a

wall helps form the wall.

Challenges and contests are great motivators.

On the following slide I’ve suggested a purpose. Hopefully you will

help shape this.


DSP is US

Goal is to develop low cost microcomputer based equipment

and tutorials for use by students in lab and/or at home to

investigate Doing DSP using real hardware.

This might include actual hardware development, or

repackaging of existing hardware, development of study

exercises, a text, etc.

◮ Digital Signal processing

◮ Communications

◮ Control

◮ Energy/electromechanical

◮ Bioengineering


Comments

This is intended to be a framework. Something to provide a

structure that will allow a wide range of potential projects.

This summer is what you make it to be.


Initial plan of attack

◮ Get some experience – i.e., do lab exercises.

◮ Think.

◮ Talk to faculty.

◮ Start a plan.

◮ Contact the Center for Entrepreneurship.

◮ Decide what to do next

Constraints:

◮ Use real hardware.

◮ Largely PC independent.

◮ Class interest.

◮ Time available.


Digital Signal Processing

Foundational. Enables other technologies.

Develop modular test equipment:

◮ Waveform generation.

◮ Digital oscilloscope.

◮ Measure transfer function.

◮ Real time spectra.

Educational modules:

◮ filter design and implementation (analog and/or digital),

◮ waveform generation,

◮ DFT/FFT,

◮ other?


Communications


◮ Bandpass spectrum analyzer.

◮ Oscilloscope.


◮ OFDM using ultrasonics. Key concepts: synchronization,

tracking, communicating.

◮ Networking, i.e., ZigBee sensor nets, etc.

◮ ?


Control


◮ DC motor/generator


◮ PID control of motor speed.

◮ ?

Strong interest exists in being to use this in a EECS 216 lab

exercise or demonstration.


Energy/Electromechcanical


◮ ?


◮ Solar energy.

◮ Wind energy.

◮ Energy harvesting.

◮ Alternate methods of energy storage.

◮ ?


Bioengineering

◮ Ultrasonic vision aide for the blind.

◮ ?


Comments selecting a focus

Follow an interest.

Try to add scope. For example if there is an interest in studying

speech compression consider proposing a portable intercom

system based on ZigBee wireless.

◮ Relatively low ZigBee throughput encourages use of

compression.

◮ Might make a good wearable baby monitor.

◮ Might morph into senior citizen help caller.

◮ Low cost ZigBee units can are available, for example the TI

Z-Accel kit (we have some).

◮ Can lead into how to network units.

◮ There is a reasonable possibility of an actual product.


Reality often rears its ugly head

Lots of things are easy to verbalize but not necessarily all that

all easy to do.

However within any large problem there should be some

interesting and very doable subproblems.

Experience helps one to avoid making mistakes. Making

mistakes provides experience.


Doing DSP – how?

◮ Representing numbers,

◮ doing arithmetic,

◮ waveform generation,

◮ finite impulse response (FIR) filter implementation,

◮ infinite impulse response (IIR) filter implementation,

◮ measuring filter transfer functions,

◮ computing and displaying spectra in real time.

◮ Implementing a DSP based project.

Discussions will be needed to introduce the relevant theory.


Doing DSP – using what?

Field Programable Gate Array (FPGA):

◮ Digilent/Xilinx Spartan-3 Starter Board. ($169).

Low cost 16/32-bit micro-computer-unit (MCU) processors:

◮ TI 16-bit eZ430 ($20) plus T2012 (3 for $10).

◮ 16/32-bit TI F28027 Piccolo ($39).

The tumbling teapot demo illustrates:

◮ A “real time” application (advertising).

◮ Using the S3SB and the Piccolo as coprocessors. The Piccolo

computes the teapot rotations (code is shown on the

display). The FPGA implements the graphics display

support. Uses about 8% of the FGPA fabric.


Why these?

All three share low cost and ready availability.

The S3SB is used in EECS 273 and EECS 452. More and more DSP is

being done in FPGAs. EECS 452 has a number of useful modules that

we can make use of.

The MSP430 is targeted at ultra low power applications, such as

battery operation. There is a significant amount of material for the

MPS430 on the web. One particulary useful site’s URL is

http://cnx.org/lenses/TexasInstruments/MSP430 .

The TI C2000 line targeted at energy and motor control applications.

The Piccolo is a 32-bit fixed point processor and includes a number of

internally implemented peripherals. Of particular interest is its 4.6

MPS 12-bit, multichannel A/D converter.

These processors complement the DSP processor used in EECS 452.


http://cnx.org/lenses/TexasInstruments/MSP430

Fees, volunteers and hardware budgets

◮ No tuition.

◮ Staff are volunteers.

◮ Spartan-3 Starter Boards belong to EECS 452.

◮ Purchase of MSP430 and Piccolo units is being worked on.

◮ Presently have not sought out $ sources for project needs.


Carrots and sticks

You can do this all on your own. Simply search the web, find application notesand books to read, think and try things out. However, doing this in a workshopsetting adds structure and allows interactions otherwise not easily had.

Carrots:

◮ Worthwhile learning experience.

◮ Knowledgeable staff.

◮ Access to lab and MCU systems.

◮ Work with peers.

◮ Can list on resume.

◮ Reference letters.

Sticks:

◮ Virtually none.

If the shoe doesn’t fit then find a different shoe store.


Schedule and hours

The following are tentative.

Discussion: Tuesday and Thursday 1 pm-2:30 pm

Lab: Tuesday and Thursday 2:30 pm-5 pm

Office: MWF 1 pm - 3pm (otherwise available anyway)

Also available by appointment.

Lab: 4341 EECS


Caveat

The coordinators have not

worked much with either the

Piccolo or the MSP430. There

will be a measure of the blind

leading the blind.

Feel free (be encouraged) to take the initiative in setting your

own direction.


The lab and hardware

◮ Will make use of the EECS 452 lab, 4341 EECS.

◮ Keylock will provides 24/7 access.

◮ Dell PCs, printer, network connection.

◮ Oscilloscope, signal generator.

◮ Spartan-3 Starter Board for FPGA work.

◮ TI eZ430 and F28027 Piccolo USB based tools.

◮ Various other FPGA boards are available.

◮ There exist two student project labs that can be used.


The lab PCs

The lab computers are networked locally.

Internet access is supported.

Back up your files after each session!

We have had disk failures!

We have had computer power supplies fail@

We have had accidental file deletions!.

We have had virus infections!

Disks may be erased at any time if deemed necessary!

Report problems in the lab.


Software tools to be used

◮ MATLAB

◮ TI C/C++

◮ TI MSP430 and Piccolo assembly languages

◮ Texas Instruments Code Composer Essentials (CSE) and

Code Composer Studio (CCS)

◮ Windows XP (intra-lab networked)

◮ Xilinx WebPACK Integrated System Environment, ISE 10.1.

◮ Digilent Export.

VHDL will be used to program the FPGAs. This is a somewhat

C like hardware description language. Hardware design has be-

come a programming task. In addition to down loading new code

into a device one can now also download a new hardware archi-

tecture.


Lab Exercises

Each exercise is nominally of one week duration. Recommend individ-

ual work or two person teams.

First exercise: Introduction to the S3SB.

Second exercise: Working with the S3SB.

Third exercise: Introduction to the F28027 controlSTICK.

Fourth exercise: Working with the controlSTICK

Fifth exercise: Introduction to the eZ430.

Sixth exercise: Working with the eZ430.

Will exploit manufacturer and EECS 452 materials as much as feasible.

“Really strange — as soon as you do it correctly it works.” — anon


Focus suggestions

◮ transfer function measurement unit

◮ real time spectrum display unit

◮ oscilloscope unit

◮ signal generator unit

◮ ultrasonic vision aide for the blind

◮ bit-serial FFT on the FPGA

◮ bit-serial VHDL compiler

◮ DSP filter implementation study

◮ DTMF tone generation and decoding

◮ speech compression study

◮ WWVB based precision time/frequency standard/calibrator

◮ implement display support on NEXYS2 (not really DSP)

◮ your turn to suggest


Consider


About FPGAs

FPGA: Field Programmable Gate Array.

Amorphous logic, ≥ 5× 105 gate devices commonplace.

More and more being used to augment DSP processors.

More and more being used to replace DSP processors.

Advantages:

High parallelism, high speeds, low cost.

Can tailor the hardware to a given application.

Disadvantages:

Generally need to work at a level below assembly language.

Need to understand how things really work.

Have to supply/create the hardware (software?) structure.


FPGAs and EECS

◮ Field Programmable Gate Arrays are finding increasing use in

DSP applications, sometimes replacing DSP processors.

◮ FPGA design is being/has been taught at the freshman level.

Engin 100 taught by Peter Chen. The students design

microcomputer and use it to implement a music synthesizer.

Use Verilog and the Altera DE2 board. The Altera DE2 is also

used in EECS 270. EECS 373 and EECS 452 make use of the

Digilent/Xilinx Spartan-3 Starter Board.

◮ One goal in the workshop is to implement digital filters using

an FPGA. At least at a basic level.


Xilinx and VHDL

◮ The two largest FPGA manufacturers are Xilinx and Altera.

◮ The two dominant hardware design languages are:

VHDL — very high design language

Verilog

◮ I primarily have experience with Xilinx using VHDL hence . . . .

◮ Xilinx makes available a free WebPACKtm version of their

design tools. This is full featured but limited to the smaller

FPGA chips, which are not all that small. Version 10.1 is

available for downloading (service pack two should be

applied).

◮ Digilent Inc. manufactures the Xilinx Spartan-3 starter board.

Also sells various peripherals such as dual channel 1 MHz

A/D and D/A converters, ethernet interface, USB interface,

H-bridges, etc. These are VERY affordable.


The Spartan-3 starter board

Basic unit (200K gates) sold by Xilinx

for $119. EECS 373 and EECS 452

use the 1000K version ($169).

Manufactured by Digilent. Sells

boards using 200K, 400K or 1M gate

Spartan-3. Also sells auxiliary

boards such as ethernet interface, 1

MHz dual A/D and D/A, etc.

Well supported by Xilinx’s free

WebPack version of its ISE 10.1

development software.

Uses 50 MHz clock (can use on-chip

clock multiplier to increase).

Photo and diagram from the Digilent web site.


The Spartan-3 1000K starter board features

◮ Xilinx Spartan-3 FPGA with 24 18-bit multipliers, 432 Kbits

of block RAM, and up to 500MHz internal clock speeds

◮ On-board 2Mbit Platform Flash (XCF02S)

◮ 8 slide switches, 4 pushbuttons, 9 LEDs, and 4-digit

seven-segment display

◮ Serial port, VGA port, and PS/2 mouse/keyboard port

◮ Three 40-pin expansion connectors

◮ Three high-current voltage regulators (3.3V, 2.5V, and 1.2V)

◮ Works with JTAG3 programming cable, and P4 & MultiPRO

cables from Xilinx

◮ 1Mbyte on-board 10ns SRAM (256Kb x 32)

◮ Has lots of connector pins .

Modified from the Digilent web site.


A VHDL self-study ladder

DSP Integrated Circuits, L. Wanhammar, ($102)Digital Signal Processing with Field Programmable Gate Arrays, Meyer-Baese ($99)RTL Hardware Design Using VHDL, P. Chu, ($105)The Designer’s Guide to VHDL, 2nd, P. Ashenden ($70)Circuit Design with VHDL, V. Pedroni ($42)Digital Design, F. Vahid ($112)

An excellent text focusing on the overall system is: Dedicated Digital Processors,F. Mayer-Lindenberg ($110). Very terse but very thorough. Strap yourself inbefore starting to read.

Prices are approximate list values.


6

F28027 (Piccolo) controlSTICK

From TI pdf file.


Basic TMS320F28027 characteristics◮ 60 MHz (16.67-ns cycle time)

◮ 16× 16 and 32× 32 MAC operations

◮ 16× 16 dual MAC

◮ Harvard bus architecture

◮ 6K 16-bit SRAM, 32K 16-bit flash rom

◮ single 3.3 Volt supply

◮ serial port peripherals (SCI, SPI, I2S)

◮ three 32-bit CPU timers

◮ 22 individually programmable GPIO pins

◮ 2 internal zero pin oscillators

◮ multichannel 12-bit A/D converter

◮ on-chip temperature sensor

◮ pulse width modulators

◮ 38 and 48 pin’d packages

◮ single quantity price, $5.90Doing DSP Workshop – Summer 2009 Meeting 1 – /46 Tuesday – May 5, 2009

F28027 Block Diagram

3 External Interrupts

M0

SARAM 1K x 16

(0-wait)

16-bit Peripheral Bus

M1

SARAM 1K x 16

(0-wait)

SCI

(4L FIFO)

ePWMSPI

(4L FIFO)

I2C

(4L FIFO)HRPWM

eCAP

32-Bit Peripheral Bus

CodeSecurityModule

GPIO MUX

C28x32-bit CPU

A7:0

B7:0

PIE

CPU Timer 0

CPU Timer 1

CPU Timer 2

TCK

TDITMS

TDO

TRST

OSC1,

OSC2,

Ext,

PLL,

LPM,

WD

XCLKIN

X2

XRS

32-bit Peripheral Bus

EC

AP

x

EP

WM

xA

ES

YN

CI

SD

Ax

SP

IST

Ex

SC

Lx

SP

ISIM

Ox

SP

ICL

Kx

COMP1OUTS

CIR

XD

x

GPIOMux

LPM Wakeup

AIO

MUX

ADC

PSWD

FLASH16K/32K x 16

Secure

OTP 1K x 16Secure

OTP/Flash

Wrapper

Boot-ROM

8K x 16

(0-wait)

SARAM

1K/3K/4K x 16

(0-wait)

Secure

COMP

32

-bit

pe

rip

he

ral

bu

s

COMP1A

COMP1BCOMP2A

COMP2B

COMP2OUT

X1

GPIO

MUX

VREG

FromCOMP1OUT,COMP2OUT

POR/BOR

Mem

ory

Bu

s

Memory Bus

Memory Bus

TZ

x

SC

ITX

Dx

SP

ISO

MIx

EP

WM

xB

ES

YN

CO


Feel the Music contest 2nd place winner

The Piccolo was used by a team of three EECS sophomores for

their entry in the Winter 2009 term Feel the Music contest.

The team won second prize, $3000.


eZ430-F2013 and the t2012

From TI web site.


Basic TMS320F2012/2013 characteristics

◮ 16 MHz (62.5-ns cycle time)

◮ no multiplier

◮ Harvard bus architecture

◮ 64 16-bit SRAM, 1K 16-bit flash rom

◮ single 1.8 to 3.3 Volt supply

◮ serial port peripherals (SPI, I2S)

◮ one 16-bit timers

◮ 10 programmable GPIO pins

◮ internal zero pin oscillators

◮ 16-bit A/D converter (33 kHz max?) (2013)

◮ 10-bit A/D converter (200 kHz max) (2012)

◮ on-chip temperature sensor

◮ 100 qty quantity price, about $1.50


Is that a typo?

64 16-bit words of SRAM is NOT a typo.

TI sells lots of these chips.

The vendors seem to have good stock.

These chips must find use somehow, somewhere.

How creative are we?


2012 Block diagram

Basic ClockSystem+

RAM

128B128B

BrownoutProtection

RST/NMI

VCC VSS

MCLK

SMCLK

WatchdogWDT+

15/16--Bit

Timer_A2

2 CCRegisters

16MHzCPUincl. 16Registers

Emulation(2BP)

XOUT

JTAGInterface

Flash

2kB1kB

ACLK

XIN

Port P1

8 I/OInterruptcapability,

pull--up/downresistors

ADC10

10--bit8 ChannelsAutoscanDTC

P1.x & JTAG

8 2

Port P2

2 I/OInterruptcapability,

pull--up/downresistors

MDB

MAB

USI

UniversalSerial

InterfaceSPI, I2C

Spy--Bi Wire

P2.x &XIN/XOUT

NOTE: See port schematics section for detailed I/O information.

From data sheet.Doing DSP Workshop – Summer 2009 Meeting 1 – /46 Tuesday – May 5, 2009

Example of use

Quarter Sized Temperature Recorder

Texas Instruments MSP430-F2013

Robert J. WilsonSeptember 29, 2006


Can make use of upscale MSP430 units

In particular the MSP430F5438.

◮ 18 MHz cycle clock

◮ 8K 16-bit SRAM, 128 K 16-bit flash

◮ 87 GIPO pins

◮ 16 channel 12 bit A/D

◮ 4 of UART, IrDA, SPI, I2C

◮ hardware multiplier

◮ real time clock

◮ DMA

◮ two timers

◮ leaded packages..can use with socket

◮ single qty price $9.70


5438 block diagram

UnifiedClock

System

256KB192KB128KB

Flash

16KB

RAMMCLK

ACLK

SMCLK

I/O PortsP1/P2

2×8 I/OsInterrupt

Capability

PA1×16 I/Os

CPUXV2and

WorkingRegisters

EEM(L: 8+2)

XIN XOUT

JTAG/

InterfaceSBW

PA PB PC PD

DMA

3 Channel

XT2IN

XT OUT2

PE

PowerManagement

LDOSVM/Brownout

SVS

SYS

Watchdog

PF

I/O PortsP3/P4

2×8 I/Os

PB1×16 I/Os

I/O PortsP5/P6

2×8 I/Os

PC1×16 I/Os

I/O PortsP7/P8

2×8 I/Os

PD1×16 I/Os

I/O PortsP9/P10

2×8 I/Os

PE1×16 I/Os

I/O PortsP11

1×3 I/Os

PF1×3 I/Os

MPY32

Timer0_A5

5 CCRegisters

Timer1_A3

3 CCRegisters

Timer_B7

7 CCRegisters

RTC_A CRC16

USCI0,1,2,3

Ax: UART,IrDA, SPI

Bx: SPI, I2C

ADC12_A

200 KSPS

16 Channels(12 ext/4 int)

Autoscan

12 Bit

DVCC DVSS AVCC AVSS

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x P10.x P11.xRST/NMI

MAB

MDB

From data sheet.


MSP430F5438 100 pin socket system

From TI web site.


A more advanced hardware

From TI web site.


meeting 1 - electrical engineering and computer science · computing and displaying spectra in real...

Documents