REVIEW OF SCIENTIFIC INSTRUMENTS VOLUME 70, NUMBER 8 AUGUST 1999

A high precision method for measuring very small capacitance changesAshkan Ashrafi and Hossein GolnabiInstitute of Water and Energy, Sharif University of Technology, 8639 Tehran, Iran

~Received 26 January 1999; accepted for publication 5 May 1999!

A novel method for measuring very small capacitance changes based on capacitance-to-phase angleconversion is introduced in this article. This new method is the improved or linearized version of thenonlinear capacitance-to-phase angle conversion method. The main features of this scheme are thevery good linearity, extremely high stray immunity and a very high resolution. The experimentalresults of the prototype version of this scheme have also been reported. By using this prototype anda simple capacitive transducer, a minimum detectable distance of about 16 nm can be achieved. Thismeans that a capacitance change of about 0.7 fF (0.7310215F) in a capacitance of 22 pF can beresolved, so the minimum resolvable relative capacitance is about 32 ppm. By the theory it can beseen that the minimum resolvable relative capacitance of 2 ppm could be achieved by this method.© 1999 American Institute of Physics.@S0034-6748~99!03808-3#

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I. INTRODUCTION

During the past years capacitive transducers have fomany applications. For measuring a very small capacitachange there is a demand for a reliable high precision reout circuit. In principle, measuring small capacitance chais not a new problem. Several attempts have been madorder to achieve high resolution measurement. Thesetempts are generally based on: the ac bridge meth1

capacitance-to-frequency conversion,1,2 and charge and discharge methods.3,4 Also, recently the new methods basedthe switched-capacitor technique5,6 and capacitance-to-phasangle conversion7 have been reported.

In this article a new method based on a linecapacitance-to-phase angle conversion is introduced.main idea has been described previously,7 but the techniquethat has been developed has several limitations and divantages. At first, we make some comments on these divantages and then describe the modifications that have lethe new method. By this method very small capacitanchanges can be measured with the extremely high immuto grounded stray capacitances. In the following sectiofirst the theoretical description of the proposed methodpresented. Then, the experimental results of a prototypesion are given in order to demonstrate the practical impmentation of the new method. Ultimately, we discusspractical limitations that can somehow restrict the perfmance of the readout circuit.

II. THEORETICAL ANALYSIS

A. Comments on the previous scheme

Figure 1 shows the scheme offered in the previowork.7 This scheme has three major drawbacks, whichdescribed as follows:

~1! The relationship between the output phase andinput capacitance changes is nonlinear. This relationshipthe form of tan21 as given in Ref. 7.

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~2! The input impedance of the charge amplifier usedRef. 7 is not low enough for high stray-immune measuments. By assumingRfCfv@1 andv@a the input imped-ance of the charge amplifier shown in Fig. 1 can be writas

Zin51

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1

G

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'1

GCf, ~1!

where a is the first pole of the op-amp,G is the gain-bandwidth product of the op-amp, andRf and Cf are thefeedback resistor and capacitor, respectively. In order tocreaseZin , according to Eq.~1! we need to increase thproduct value ofGCf , which can be done by increasineitherG or Cf . But any increase in the value ofCf causes adecrease in the output signal level. On the other handincreaseG we are forced to use a high frequency op-amp

~3! The reported charge amplifier, as it is shown in F1, produces a constant phase shift in the output signalcauses an extra nonlinear relation between the generatedput phase angle tangent and the input capacitance chanThis phase shift depends on the frequency characteristithe op-amp and its value only can be reduced by using a hfrequency op-amp.

B. The new scheme

For overcoming the second and the third problems ofpervious scheme, a simple parallelR–C circuit in front of abuffer amplifier is suggested@Fig. 2~a!#. The buffer amplifiermust produce no phase shift.8 In order to achieve such acharacteristic the active feedback scheme shown in Fig.~b!is used to design a buffer amplifier.9 Calculations show thaif the two op-amps used for constructing the buffer amplifiare closely matched, the resulting phase shift could be wten as9

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3484 Rev. Sci. Instrum., Vol. 70, No. 8, August 1999 A. Ashrafi and H. Golnabi

where by choosing low frequency signal, the disturbiphase shift could be considerably decreased.

By assumingvRTCT@1, according to Fig. 2~a!, we canwrite

V05C0B

CT1C01CX•sin~vt1p2c!

1CXA

CT1C01CX•sin~vt !, ~3!

whereC0 is the reference capacitor,CX is the measured capacitor,CT is the voltage dividing capacitor, andA,B are theamplitudes of the two sinusoidal signals. By using the geral formula for the summation of two sinusoidal functionEq. ~3! can be simplified as

V05C0B•sinc

~CT1C01CX!•sinw•sin~vt1w! ~4!

and

cot~w!5CXA

C0B•sin~c!2cot~c!. ~5!

Figure 2~a! shows the possible stray capacitance,CS2 ,appearing between plate 2 of the measurand capacitorground that is added toCT . On the other hand, it is apparefrom Eqs.~4! and ~5! that the value ofCT has no effect onthe phase of the output signal and it only changes the am

FIG. 1. The schematic diagram of a capacitance-to-phase angle convreported in Ref. 7.

FIG. 2. The proposed scheme for the capacitance-to-phase angle cosion. ~a! The modified capacitance-to-phase angle converter (CS1 and CS2

show the possible stray capacitances!. ~b! The buffer amplifier.~c! Thecircuit design for producing the two signals with an appropriate phaseference (p2c).

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tude of the output signal. Therefore, we can argue thatscheme has an extreme stray immunity from side 2 ofCX .

For producing two input signals,A sin(vt) andB sin(vt1p2c), the circuit which is shown in Fig. 2~c! is used. Inthis circuit, first a sinusoidal signal is produced by an osclator. This sinusoidal signal is used for generating two banced signals with 180° phase difference. This is accoplished by employing two matched op-amps.10 Then thephase of one of the signals is shifted byR1 and C1 by theamount ofc@c5tan21(R1C1v)#. At the end, we get two sig-nals defined asA sin(vt) andB sin(vt1p2c), whereA andB are the signal’s amplitudes.

In spite of the mentioned advantages, the nonlinearhavior is still present in the new scheme. This problem cbe overcome by using a conventional quadrature phasesitive detector~PSD! that provides the cotangent of the ouput phase. By this configuration one can construct a linrelationship between the input capacitance and the outputhe PSD. The overall block diagram of this design is shoin Fig. 3. By using switching multipliers11,12 the two dc out-puts become

VC52KC0B•sin~c!

pCS•cot~w! ~6!

and

VS52KC0B•sin~c!

pCS, ~7!

where CS is defined as a total capacitance (CS5CT1C0

1CX), andK is the gain of arbitrary ac amplifier which mabe used for increasing the amplitude ofVO ~the output of thecapacitance-to-phase angle converter!. The two referencesignals for the quadrature switching PSD have been proviby converting sin(vt) and cos(vt) to square waves. This conversion is accomplished by using two voltage comparatorshown in Fig. 3. By dividing Eq.~6! by Eq. ~7! it is evidentthat

cot~w!5VC

VS. ~8!

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3485Rev. Sci. Instrum., Vol. 70, No. 8, August 1999 Small capacitance changes

For dividing VC by VS , first, two analog-to-digital con-verters~ADCs! convert these signals to digital numbers athen they are conveyed to a microcomputer, where the dsion process is performed.

The reference voltages used for the ADCs areVRC andVRS corresponding toVC andVS , respectively. If the ADCshavem-bit outputs, it can be written

DC52mVC

VRC, ~9!

DS52mVS

VRS, ~10!

whereDC and DS are the digital outputs of the convertecorresponding toVC and VS , respectively. From these assumptions and using Eqs.~5!, ~8!, ~9!, and ~10! a linear re-lationship can be derived between the measurand capaCX andDC /DS . Equation~5! then becomes

cot~w!5DC

DS•

VRC

VRS5

CXA

C0B•sin~c!2cot~c!. ~11!

It can be seen from Eq.~11! thatA,B,c andC0 are the onlyparameters contributing to the output results.

Let CX0 be a reference value forCX and consider themeasurand of interest to be the deviation from this referevalue, namedCX1 , so that

CX5CX01CX1 . ~12!

By substituting Eq.~12! into Eq. ~11!, the linear relationshipconverted to

cot~w!5DC

DS•

1

n

5CX0•A

C0B•sin~c!2cot~c!1

CX1A

C0B•sin~c!, ~13!

wheren5VRS/VRC . By adjustingA, so that it satisfies thefollowing relationship:

CX0A5C0B•cos~c!, ~14!

Eq. ~13! can be written as

DC

DS•

1

n5

CX1

CX0•cot~c!. ~15!

By defining CX1 /CX0 ~the normalized capacitance ratio! asthe output (DOUT), it can be written

DOUT5CX1

CX05

tan~c!

n•

DC

DS. ~16!

Equation~16! is the main relationship between the normized capacitance ratio and the output numberDOUT, which iscomputed by a microcomputer via a proper program. Unthe condition given in Eq.~14! the effects ofA, B, andC0

can be eliminated. Equation~14! also establishes the calibration condition for the measurements. When Eq.~14! is satis-fied, the related outputDOUT for CX150 will be zero, so thisrelation is referred to as the ‘‘zero adjustment condition.’

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C. Calculation of resolution

Because of the normalized output, it is more approprito develop the resolving formula for the relative capacitanmeasurements. The resolvable relative capacitance coulthen derived from Eq.~16!. As it can be inferred from Eq~16!, variations of the parametersc, n, and the resolution ofthe ADC’s outputs (DC /DS) could affect the overall resolvable relative capacitance. Thec variations could be mini-mized by using a stable phase shifter, and its variationsbe corrected by recordingc for each measuring step. Bchoosing a single temperature compensated voltage referfor both DACs, the variations ofVRS and VRC due to thetemperature changes is extremely low and can be ignoBy considering the mentioned descriptions the resolvarelative capacitance can be derived by differentiating E~16!, which results in:

DDOUT5tan~c!

n•DS DC

DSD . ~17!

The only parameter that remains effective on the resolvarelative capacitance is the resolution of the ADCs. If eaADC generates an error of61 least significant bit, thenDDC5DDS51, and for the worst caseDC5DS we have

DS DC

DSD5

2

DS. ~18!

For achieving the highest possible resolution,DS must be aslarge as possible. Therefore, our program is arranged in sa way thatDS becomes the maximum achievable valuecontrollingVRS via digital to-analog converter~DAC!1 ~Fig.3!, such as an autoranged ADC. For the ADC’s with thembit resolution, the maximum value ofDS equal to 2m thencan be written as

DS DC

DSD5

1

2m21 . ~19!

If we consider 12-bit ADCs, then the achievable resolutiof dividing VC by VS is 1000 ppm~full scale DC /DS51)according to Eq.~19!. By substituting Eq.~19! into Eq. ~17!we will have

DCX1

CX05DDOUT5

tan~c!

n•2m21 . ~20!

Although the maximum achievable resolution from ADCsthe dividing process is 1000 ppm, according to Eq.~20! theoverall resolution of the system can be further improvedconsideringc andn. On the other hand, increasing the reslution will decrease the dynamic range. In order to achiethe optimum performance one has to compromise betwthe resolvable relative capacitance and the dynamic rang

D. Noise analysis

The main internal noise source is the buffer amplifiConsidering the input referred noise voltages and currentthe two matched op-ampsEn and I n , the rms value of theoutput noise can be calculated as

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3486 Rev. Sci. Instrum., Vol. 70, No. 8, August 1999 A. Ashrafi and H. Golnabi

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v2CS2RT

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2RT2

~RTCSv11!2G•D f . ~21!

By using LF353, according to its data sheet the noise voltand current of this op-amp is 25 nV/AHz and 0.01 pA/AHz,respectively. By choosing the values:RT522 MV, CS

525 pF,v52p 10 000 rad/s, at room temperature and atbandwidth of 1.5 Hz~corresponding to the bandwidth of thlow pass filters used in synchronous detector! the rms valueof the output noise will be 48 nV.

III. EXPERIMENTAL RESULTS

A prototype version of the described scheme has bconstructed by using commercial components such asLF353 as op-amp, ICL7109 as ADCs, and the 4053 anaswitch as switching multipliers. The operating frequency wchosen at 10 kHz.

For testing the prototype circuit, we constructed a simcapacitive transducer with a Kelvin guard ring.13 It is de-signed so that the distance between its plates~X! is muchsmaller than the radius of the plates. In this configurationwell known relationship of the parallel plates capacitorvalid:

C5e•Ae

X, ~22!

whereAe is the effective area of the two plates, ande is thepermeability of the dielectric material between the two pla~air!.

To control the distanceX precisely and to scan this tranducer smoothly a high resolution stepping motor~800 stepsper revolution! was coupled to a microscrew that was drivinone of the capacitor’s plates. The microscrew has a pitch2 turns/mm, which results a displacement of 0.625mm for asingle step of the motor.

In order to obtain a linear relationship betweenDOUT

andX, we need to exchange the position ofCX andC0 in thecircuit depicted in Fig. 2~a!. It is assumed thatX5X01X1 ,whereX0 is the distance in which zero adjustment has bemade andX1 is the deviation fromX0 . Therefore Eq.~16!becomes

DOUT5X1

X0. ~23!

As mentioned, Eq.~23! represents the calibration curvof the transducer that can be obtained experimentallychanging X1 from the initial value of X0 and recordingDOUT. The result of such measurements has been showFig. 4. This curve has been obtained by settingX0

50.5 mm. The slope of this line has been calculated byleast square method which is 2.0631023/mm. For a com-parison the slope is also obtained by the theory (1/X0) that is231023/mm. As can be seen there is a very good agreembetween the theory and the experiment. However, a ldifference between the theoretical and experimental resmay be due to the existence of the stray capacitancestween the two plates of the capacitive sensor. This effec

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probably caused by the type of connections arranged forjunctions of the plates of the capacitive sensor and the friing effect near the edges of the sensor.

In this computations we set:c53.7°, n51 andm512~number of bits of the ADCs!. By substituting these valueinto Eq.~20! the minimum resolvable relative capacitance32 ppm is calculated. According to the resolvable relatcapacitance of about 32 ppm, the minimum detectableplacement is about 16 nm.

The nonlinearity of the curve shown in Fig. 4 is less th0.5%, which mainly depends on the fluctuations of the mchanical scanning system.

The minimum measurable displacement in the capacisensor is the displacement which results from a voltachange equal to the rms noise voltage in the bandwidth ofelectronic circuit. By choosingB510 V, C0512 pF, CS

525 pF andc53.7° according to Eq.~6!, ~16! and ~21!,D cotg~w! will be 48 nV/0.2 V52.431027. Considering Eqs.~16! and ~23! it can be seen thatDX1 /X15tan(c)3D cotg(w)51.531028 or the minimum measurable displacement is 7.7310212m. This value is much less than thminimum resolvable relative displacement achievable bysystematic error of the system. The lower limit of the minmum resolvable relative capacitance is achieved by choon515 so that it will be 2 ppm. The low noise performancethe readout circuit permits high precision in such measuments.

IV. DISCUSSION

In Sec. II the systematic error for the readout circuit hbeen described. Along with systematic error, there are sopractical limitations that may affect the performance of treadout system. However, the overall performance oftransducer is controlled in part by the measuring circuit aby the sensor as well. Therefore, some limitations are dusensor characteristics and some are due to the readout ciIn our case, the resolution and the overall performance oftransducer were mainly limited by the mechanical drive s

FIG. 4. ~Top! Shows the variation of the normalized capacitance ofconstructed transducer as a function of positive displacements betweeplates (X1). ~Bottom! Shows the percentage of nonlinearity of the relatdisplacements.

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3487Rev. Sci. Instrum., Vol. 70, No. 8, August 1999 Small capacitance changes

tem of the capacitive sensor. Practically, to meet and msure such a high resolutions one has to take advantage osmall value of capacitance changes in the integrated cirsensors. The resolution of the readout circuit was estimato be about 0.044 fF~2 ppm!, however for the present system, our resolution is limited to only 0.7 fF~32 ppm!. Thepractical limitations of the reported readout system andways to minimize those can be classified as follows:

~1! Amplitude variations of the main oscillator cause tsame variations on the two output voltages of the PSDsVC

andVS). Since these two voltages are divided by each oththe amplitude variations of he main oscillator do not affethe output.

~2! Phase jitters of the main oscillator degrade the sbility of the output. This effect can be decreased primarilyusing a very stable oscillator. Besides, output oversampleads to a very stable output.

~3! Since the measurand quantity converts to the phangle difference between the two signals, the effects ofplitude noise and disturbances will be very small on the oput signal of the capacitance-to-phase angle converter. Awith this intrinsic behavior, the phase-sensitive detecteliminate the noise significantly. This elimination is duePSD’s narrow pass bands around the main~fundamental! fre-quency and its odd harmonics.12 The nonfundamental pasbands may cause an error due to the odd harmonics oinput sinewave but, by designing a low distortion oscillathis effect can be minimized.

~4! The only stage which can increase the output noand unstability is ADC, since it has a dc gain. This effecauses a limitation onn. This limitation strongly depends othe ADC performance and the PCB design.14,15 For furtherdecrease of the output noise, special program is prepareoversample the outputs of the ADCs and averaging thThis method can improve the signal-to-noise ratio but, sldown the speed of the measurements. Noise reductiontained by this method is proportional to the square root ofnumber of oversamplings. For achieving a good performaone has to compromise between the output noise reducand the response time of the scheme.

~5! The dielectric absorption of the capacitor may caua phase error.16 This phenomena causes a nonlinear relatbetween the output and the capacitance changes. For mmizing this effect capacitances with low dielectric absorptmust be used asCT andC0 . The sensing capacitor must hava low dielectric absorption as well; therefore using thedielectric for the sensor is the best choice.

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~6! In spite of the good stray immunity of the readocircuit, the stray capacities between the plates of the seand the ground may affect the performance. For connecthe transducer to the readout circuit, two coaxial cables hbeen used so that their outer conductors have been drivelow impedance, with a potential essentially equal to the voage of the inner conductor~active guarding!. This arrange-ment significantly reduces the effects of grounded straypacities. Stray capacities between the two plates of the sealso affect the measurements, but there is no easy methoreduce its effects on the readout circuit except by reducingvalue. In order to reduce its value, proper connections mbe arranged between the plates of the sensor and the cocables, and such proper connections must be made betwthe coaxial cables and the input of the readout circuit as wOn the whole this source of noise is the main sourceinstability of the output readout that degrades the resolut

Considering the sources of noise and disturbancestaking all the necessary precautions, the output fluctuatihave been reduced to65 ppm which is less than the effect othe minimum resolvable relative capacitance~32 ppm!.These fluctuations manifest themselves as the instabilitythe output.

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