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M68HC08Microcontrollers

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MC68HC908QY4MC68HC908QT4MC68HC908QY2MC68HC908QT2MC68HC908QY1MC68HC908QT1

Data Sheet

MC68HC908QY4/DRev. 603/2010

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.This product incorporates SuperFlash® technology licensed from SST.

© Freescale Semiconductor, Inc., 2005–2010. All rights reserved.

MC68HC908QY4MC68HC908QT4MC68HC908QY2MC68HC908QT2MC68HC908QY1MC68HC908QT1Data Sheet

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

http://freescale.com/

MC68HC908QY/QT Family Data Sheet, Rev. 6

Freescale Semiconductor 3

Revision History

The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.

Revision History (Sheet 1 of 3)

DateRevision

LevelDescription

PageNumber(s)

September,2002

N/A Initial release N/A

December, 2002

0.1

1.2 Features — Added 8-pin dual flat no lead (DFN) packages to features list. 19

Figure 1-2. MCU Pin Assignments — Figure updated to include DFN packages. 21

Figure 2-1. Memory Map — Clarified illegal address and unimplemented memory.

27

Figure 2-2. Control, Status, and Data Registers — Corrected bit definitions for Port A Data Register (PTA) and Data Direction Register A (DDRA).

27

Table 13-3. Interrupt Sources — Corrected vector addresses for keyboard interrupt and ADC conversion complete interrupt.

118

Chapter 13 System Integration Module (SIM) — Removed reference to break status register as it is duplicated in break module.

113

11.3.1 Internal Oscillator and 11.3.1.1 Internal Oscillator Trimming — Clarified oscillator trim option ordering information and what to expect with untrimmed device.

92

Figure 11-5. Oscillator Trim Register (OSCTRIM) — Bit 1 designation corrected. 98

Figure 15-13. Monitor Mode Circuit (Internal Clock, No High Voltage) — Diagram updated for clarity.

150

Figure 12-1. I/O Port Register Summary — Corrected bit definitions for PTA7, DDRA7, and DDRA6.

99

Figure 12-2. Port A Data Register (PTA) — Corrected bit definition for PTA7. 100

Figure 12-3. Data Direction Register A (DDRA) — Corrected bit definitions for DDRA7 and DDRA6.

101

Figure 12-6. Port B Data Register (PTB) — Corrected bit definition for PTB1 103

Chapter 9 Keyboard Interrupt Module (KBI) — Section reworked after deletion of auto wakeup for clarity.

83

Chapter 4 Auto Wakeup Module (AWU) — New section added for clarity. 49

Figure 10-1. LVI Module Block Diagram — Corrected LVI stop representation. 87

Chapter 16 Electrical Specifications — Extensive changes made to electrical specifications.

169

17.5 8-Pin Dual Flat No Lead (DFN) Package (Case #1452) — Added case outline drawing for DFN package.

177

Chapter 17 Ordering Information and Mechanical Specifications — Added ordering information for DFN package.

185

January,2003

0.2 4.2 Features — Corrected third bulleted item. 49


4 Freescale Semiconductor

August,2003

1.0

Reformatted to meet latest M68HC08 documentation standards N/A

Figure 1-1. Block Diagram — Diagram redrawn to include keyboard interrupt module and TCLK pin designator.

20

Figure 1-2. MCU Pin Assignments — Added TCLK pin designator. 21

Table 1-2. Pin Functions — Added TCLK pin description. 22

Table 1-3. Function Priority in Shared Pins — Revised table for clarity and to add TCLK.

23

Figure 2-1. Memory Map — Corrected names for the IRQ status and control register (INTSCR) bits 3–0.

26

3.7.3 ADC Input Clock Register — Clarified bit description for the ADC clock prescaler bits.

47

4.3 Functional Description — Updated periodic wakeup request values. 51

Figure 6-1. COP Block Diagram — Reworked for clarity 59

Chapter 8 External Interrupt (IRQ) — Corrected bit names for MODE, IRQF, ACK, and IMASK

77–79

Chapter 14 Timer Interface Module (TIM) — Added TCLK function. 131–139

15.3 Monitor Module (MON) — Updated with additional data. 147

Chapter 16 Electrical Specifications — Updated with additional data. 169–173

October,2003

2.0

Figure 2-2. Control, Status, and Data Registers — Deleted unimplemented areas from $FFB0–$FFBD and $FFC2–$FFCF as they are actually available. Also corrected $FFBF designation from unimplemented to reserved.

27

Figure 6-1. COP Block Diagram — Reworked for clarity 59

6.3.2 STOP Instruction — Added subsection 60

13.4.2 Active Resets from Internal Sources — Reworked notes for clarity. 111

Table 13-2. Reset Recovery Timing — Replaced previous table with new information.

112

Chapter 14 Timer Interface Module (TIM) — Updated with additional data. 131

Figure 15-3. Break I/O Register Summary — Corrected bit designators for the BRKAR register

143

15.3 Monitor Module (MON) — Clarified seventh bullet. 147

Table 17-1. MC Order Numbers — Corrected temperature and package designators.

175

January,2004

3.0

Figure 2-2. Control, Status, and Data Registers — Corrected reset state for the FLASH Block Protect Register at address location $FFBE and the Internal Oscillator Trim Value at $FFC0.

32

Figure 2-5. FLASH Block Protect Register (FLBPR) — Restated reset state for clarity.

38


DateRevision

LevelDescription

PageNumber(s)



Revision History

November,2004

4.0

Reformatted to meet current documentation standards Throughout

6.3.1 BUSCLKX4 — Clarified description of BUSCLKX4 58

Chapter 7 Central Processor Unit (CPU) — In 7.7 Instruction Set Summary:Reworked definitions for STOP instructionAdded WAIT instruction

7071

13.8.1 SIM Reset Status Register — Clarified SRSR flag setting 117

14.9.1 TIM Status and Control Register — Added information to TSTOP note 127

16.8 5-V Oscillator Characteristics — Added values for deviation from trimmed inernal oscillator

155

16.12 3-V Oscillator Characteristics — Added values for deviation from trimmed inernal oscillator

158

July,2005

5.0

Figure 5-2. Configuration Register 1 (CONFIG1) — Clarified bit definitions for COPRS.

54

Chapter 8 External Interrupt (IRQ) — Reworked for clarification. 73

11.3.4 RC Oscillator — Improved RC oscillator wording. 93

12.1 Introduction — Added note pertaining to non-bonded port pins. 97

17.3 Package Dimensions — Updated package information. 165

March,2010

6.0 Clarify internal oscillator trim register information.26, 27, 31, 34, 35, 38,

91, 96


DateRevision

LevelDescription

PageNumber(s)



List of Chapters

Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Chapter 4 Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Chapter 5 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Chapter 6 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Chapter 7 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Chapter 8 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Chapter 9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Chapter 10 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Chapter 11 Oscillator Module (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Chapter 12 Input/Output Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Chapter 13 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Chapter 14 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Chapter 15 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Chapter 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Chapter 17 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . .165



List of Chapters



Table of Contents

Chapter 1 General Description

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191.4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191.5 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221.6 Pin Function Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Chapter 2 Memory

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.2 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.3 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.4 Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272.5 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322.6 FLASH Memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332.6.1 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332.6.2 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342.6.3 FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352.6.4 FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352.6.5 FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362.6.6 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382.6.7 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392.6.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Chapter 3 Analog-to-Digital Converter (ADC)

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413.3.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.3.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.3.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.3.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45



Table of Contents

3.6 Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.7 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.7.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.7.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473.7.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Chapter 4 Auto Wakeup Module (AWU)

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504.6 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514.6.1 Port A I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514.6.2 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514.6.3 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Chapter 5 Configuration Register (CONFIG)

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Chapter 6 Computer Operating Properly (COP)

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586.3.1 BUSCLKX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586.3.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586.3.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586.3.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586.3.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586.3.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586.3.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59



Chapter 7 Central Processor Unit (CPU)

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Chapter 8 External Interrupt (IRQ)

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738.3.1 MODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758.3.2 MODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768.7.1 IRQ Input Pins (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Chapter 9 Keyboard Interrupt Module (KBI)

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799.3.1 Keyboard Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799.3.2 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829.6 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82



Table of Contents

9.7 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839.7.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839.7.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Chapter 10 Low-Voltage Inhibit (LVI)

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8510.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8510.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8510.3.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8610.3.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8610.3.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8610.3.4 LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8610.4 LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8710.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8710.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8710.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8710.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Chapter 11 Oscillator Module (OSC)

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8911.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8911.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8911.3.1 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9011.3.1.1 Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9111.3.1.2 Internal to External Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9111.3.2 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9111.3.3 XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9211.3.4 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9311.4 Oscillator Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9311.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9311.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9411.4.3 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9411.4.4 XTAL Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9411.4.5 RC Oscillator Clock (RCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9411.4.6 Internal Oscillator Clock (INTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9411.4.7 Oscillator Out 2 (BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9411.4.8 Oscillator Out (BUSCLKX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9411.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9511.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9511.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9511.6 Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9511.7 CONFIG2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9511.8 Input/Output (I/O) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9511.8.1 Oscillator Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9611.8.2 Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96



Chapter 12 Input/Output Ports (PORTS)

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9712.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9712.2.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9812.2.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9812.2.3 Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9912.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10012.3.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10012.3.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10112.3.3 Port B Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Chapter 13 System Integration Module (SIM)

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10313.2 RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10413.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10413.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10513.3.2 Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10513.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10513.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10513.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10613.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10613.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10713.4.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10813.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10813.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10813.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10813.5 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10813.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10813.5.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10913.5.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10913.6 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10913.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10913.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11113.6.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11213.6.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11213.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11313.6.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11313.6.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11313.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11413.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11413.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11413.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11413.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11413.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115



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13.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11613.8.1 SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11713.8.2 Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Chapter 14 Timer Interface Module (TIM)

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11914.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11914.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11914.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12114.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12214.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12214.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12214.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12214.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12214.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12314.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12414.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12414.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12514.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12514.6 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12614.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12614.8 Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12614.8.1 TIM Clock Pin (PTA2/TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12614.8.2 TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 12614.9 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12614.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12714.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12814.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12914.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12914.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Chapter 15 Development Support

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13315.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13315.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13315.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13515.2.1.2 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13515.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13515.2.2 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13515.2.2.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13615.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13615.2.2.3 Break Auxiliary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13715.2.2.4 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13715.2.2.5 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13815.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138



15.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13815.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13915.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14215.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14315.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14315.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14415.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14415.3.1.6 Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14415.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14415.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Chapter 16 Electrical Specifications

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14916.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14916.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15016.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15016.5 5-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15116.6 Typical 5-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15216.7 5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15316.8 5-V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15416.9 3-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15516.10 Typical 3.0-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15616.11 3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15716.12 3-V Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15816.13 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15916.14 Analog-to-Digital Converter Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16116.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16216.16 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Chapter 17 Ordering Information and Mechanical Specifications

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16517.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16517.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165



Table of Contents



Chapter 1 General Description

1.1 Introduction

The MC68HC908QY4 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is a Complex Instruction Set Computer (CISC) with a Von Neumann architecture. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.

0.4

1.2 Features

Features include:• High-performance M68HC08 CPU core• Fully upward-compatible object code with M68HC05 Family• 5-V and 3-V operating voltages (VDD)• 8-MHz internal bus operation at 5 V, 4-MHz at 3 V• Trimmable internal oscillator

– 3.2 MHz internal bus operation– 8-bit trim capability allows 0.4% accuracy(1)

– ± 25% untrimmed• Auto wakeup from STOP capability• Configuration (CONFIG) register for MCU configuration options, including:

– Low-voltage inhibit (LVI) trip point• In-system FLASH programming• FLASH security(2)

Table 1-1. Summary of Device Variations

DeviceFLASH

Memory SizeAnalog-to-Digital

ConverterPin

Count

MC68HC908QT1 1536 bytes — 8 pins

MC68HC908QT2 1536 bytes 4 ch, 8 bit 8 pins

MC68HC908QT4 4096 bytes 4 ch, 8 bit 8 pins

MC68HC908QY1 1536 bytes — 16 pins

MC68HC908QY2 1536 bytes 4 ch, 8 bit 16 pins

MC68HC908QY4 4096 bytes 4 ch, 8 bit 16 pins

1. The oscillator frequency is guaranteed to ±5% over temperature and voltage range after trimming.2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for

unauthorized users.



General Description

• On-chip in-application programmable FLASH memory (with internal program/erase voltage generation)– MC68HC908QY4 and MC68HC908QT4 — 4096 bytes– MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, and MC68HC908QT1 — 1536 bytes

• 128 bytes of on-chip random-access memory (RAM)• 2-channel, 16-bit timer interface module (TIM)• 4-channel, 8-bit analog-to-digital converter (ADC) on MC68HC908QY2, MC68HC908QY4,

MC68HC908QT2, and MC68HC908QT4• 5 or 13 bidirectional input/output (I/O) lines and one input only:

– Six shared with keyboard interrupt function and ADC– Two shared with timer channels– One shared with external interrupt (IRQ)– Eight extra I/O lines on 16-pin package only– High current sink/source capability on all port pins– Selectable pullups on all ports, selectable on an individual bit basis– Three-state ability on all port pins

• 6-bit keyboard interrupt with wakeup feature (KBI)• Low-voltage inhibit (LVI) module features:

– Software selectable trip point in CONFIG register• System protection features:

– Computer operating properly (COP) watchdog– Low-voltage detection with reset– Illegal opcode detection with reset– Illegal address detection with reset

• External asynchronous interrupt pin with internal pullup (IRQ) shared with general-purpose input pin

• Master asynchronous reset pin (RST) shared with general-purpose input/output (I/O) pin • Power-on reset• Internal pullups on IRQ and RST to reduce external components• Memory mapped I/O registers• Power saving stop and wait modes• MC68HC908QY4, MC68HC908QY2, and MC68HC908QY1 are available in these packages:

– 16-pin plastic dual in-line package (PDIP)– 16-pin small outline integrated circuit (SOIC) package– 16-pin thin shrink small outline package (TSSOP)

• MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are available in these packages:– 8-pin PDIP– 8-pin SOIC– 8-pin dual flat no lead (DFN) package



MCU Block Diagram

Features of the CPU08 include the following:• Enhanced HC05 programming model• Extensive loop control functions• 16 addressing modes (eight more than the HC05)• 16-bit index register and stack pointer• Memory-to-memory data transfers• Fast 8 × 8 multiply instruction• Fast 16/8 divide instruction• Binary-coded decimal (BCD) instructions• Optimization for controller applications• Efficient C language support

1.3 MCU Block Diagram

Figure 1-1 shows the structure of the MC68HC908QY4.

1.4 Pin Assignments

The MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are available in 8-pin packages and the MC68HC908QY4, MC68HC908QY2, and MC68HC908QY1 in 16-pin packages. Figure 1-2 shows the pin assignment for these packages.



General Description

Figure 1-1. Block Diagram

RST, IRQ: Pins have internal (about 30K Ohms) pull upPTA[0:5]: High current sink and source capabilityPTA[0:5]: Pins have programmable keyboard interrupt and pull upPTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 (see note in 12.1 Introduction)ADC: Not available on the MC68HC908QY1 and MC68HC908QT1

PTA0/AD0/TCH0/KBI0

PTA1/AD1/TCH1/KBI1

PTA2/IRQ/KBI2/TCLK

PTA3/RST/KBI3

PTA4/OSC2/AD2/KBI4

PTA5/OSC1/AD3/KBI5

KEYBOARD INTERRUPTMODULE

CLOCKGENERATOR

(OSCILLATOR)

SYSTEM INTEGRATIONMODULE

SINGLE INTERRUPTMODULE

BREAKMODULE

POWER-ON RESETMODULE

16-BIT TIMERMODULE

COPMODULE

MONITOR ROM

PTB0PT

B

DD

RB

M68HC08 CPUPT

A

DD

RA

PTB1PTB2PTB3PTB4PTB5PTB6PTB7

8-BIT ADC

128 BYTES RAM

MC68HC908QY4 AND MC68HC908QT44096 BYTES

MC68HC908QY2, MC68HC908QY1,MC68HC908QT2, AND MC68HC908QT1:

1536 BYTESUSER FLASH

POWER SUPPLY

VDD

VSS



Pin Assignments

Figure 1-2. MCU Pin Assignments

1

2

3

4

5

6

7

8

PTB0

PTB2

PTB3PTB4

VSS

PTB6

PTB7

PTB1

8-PIN ASSIGNMENTMC68HC908QT1 PDIP/SOIC

16-PIN ASSIGNMENTMC68HC908QY1 PDIP/SOIC

VSSVDD

PTA5/OSC1/KBI5

1

2

3

4

8

7

6

5

PTA4/OSC2/KBI4

PTA3/RST/KBI3

PTA1/TCH1/KBI1

PTA0/TCH0/KBI0

PTA2/IRQ/KBI2/TCLK

VDD

PTA1/TCH1/KBI1

PTB5

PTA2/IRQ/KBI2/TCLK

PTA0/TCH0/KBI0PTA5/OSC1/KBI5

PTA4/OSC2/KBI4

PTA3/RST/KBI3

PTB2PTB3

PTB4PTB6PTB7

16-PIN ASSIGNMENTMC68HC908QY1 TSSOP

PTA1/TCH1/KBI1

PTB5

PTA2/IRQ/KBI2/TCLK

PTA5/OSC1/KBI5 PTA4/OSC2/KBI4

PTA3/RST/KBI3

PTA0/TCH0/KBI0PTB1PTB0

VSSVDD

8-PIN ASSIGNMENTMC68HC908QT2 AND MC68HC908QT4 PDIP/SOIC

VSSVDD

PTA5/OSC1/AD3/KBI5

1

2

3

4

8

7

6

5

PTA4/OSC2/AD2/KBI4

PTA3/RST/KBI3

PTA1/AD1/TCH1/KBI1

PTA0/AD0/TCH0/KBI0

PTA2/IRQ/KBI2/TCLK

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

PTB0

PTB2

PTB3PTB4

VSS

PTB6

PTB7

PTB1

16-PIN ASSIGNMENTMC68HC908QY2 AND MC68HC908QY4 PDIP/SOIC

VDD

PTA1/AD1/TCH1/KBI1

PTB5

PTA2/IRQ/KBI2/TCLK

PTA0/AD0/TCH0/KBI0PTA5/OSC1/AD3/KBI5

PTA4/OSC2/AD2/KBI4

PTA3/RST/KBI3

16-PIN ASSIGNMENTMC68HC908QY2 AND MC68HC908QY4 TSSOP

16

15

14

13

12

11

10

9

PTA0/TCH0/KBI0

VSS

VDD

PTA5/OSC1/KB15

8-PIN ASSIGNMENTMC68HC908QT1 DFN

8-PIN ASSIGNMENTMC68HC908QT2 AND MC68HC908QT4 DFN

1

2

3

4

8

7

6

5

PTA1/TCH1/KBI1

PTA3/RST/KBI3

PTA2/IRQ/KBI2/TCLK

PTA4/OSC2/KBI4

PTA0/AD0/TCH0/KBI0

VSS

VDD

PTA5//OSC1/AD3/KB15

1

2

3

4

8

7

6

5

PTA1/AD1/TCH1/KBI1

PTA3/RST/KBI3

PTA2/IRQ/KBI2/TCLK

PTA4/OSC2/AD2/KBI4

12345678

161514131211109

PTB2PTB3

PTB4PTB6PTB7

PTA1/AD1/TCH1/KBI1

PTB5

PTA2/IRQ/KBI2/TCLK

PTA5/OSC1/AD3/KBI5 PTA4/OSC2/AD2/KBI4

PTA3/RST/KBI3

PTA0/AD0/TCH0/KBI0PTB1PTB0

VSSVDD

12345678

161514131211109



General Description

1.5 Pin Functions

Table 1-2 provides a description of the pin functions.

Table 1-2. Pin Functions

PinName

Description Input/Output

VDD Power supply Power

VSS Power supply ground Power

PTA0

PTA0 — General purpose I/O port Input/Output

AD0 — A/D channel 0 input Input

TCH0 — Timer Channel 0 I/O Input/Output

KBI0 — Keyboard interrupt input 0 Input

PTA1



TCH1 — Timer Channel 1 I/O Input/Output


PTA2

PTA2 — General purpose input-only port Input

IRQ — External interrupt with programmable pullup and Schmitt trigger input Input


TCLK — Timer clock input Input

PTA3


RST — Reset input, active low with internal pullup and Schmitt trigger Input


PTA4


OSC2 —XTAL oscillator output (XTAL option only)RC or internal oscillator output (OSC2EN = 1 in PTAPUE register)

OutputOutput



PTA5


OSC1 — XTAL, RC, or external oscillator input Input



PTB[0:7](1)

1. The PTB pins are not available on the 8-pin packages (see note in 12.1 Introduction).

8 general-purpose I/O ports Input/Output



Pin Function Priority

1.6 Pin Function Priority

Table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin.

NOTEUpon reset all pins come up as input ports regardless of the priority table.

Table 1-3. Function Priority in Shared Pins

Pin Name Highest-to-Lowest Priority Sequence

PTA0 AD0 → TCH0 → KBI0 → PTA0

PTA1 AD1 →TCH1 → KBI1 → PTA1

PTA2 IRQ → KBI2 → TCLK → PTA2

PTA3 RST → KBI3 → PTA3

PTA4 OSC2 → AD2 → KBI4 → PTA4

PTA5 OSC1 → AD3 → KBI5 → PTA5



General Description



Chapter 2 Memory

2.1 Introduction

The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes:

• 4096 bytes of user FLASH for MC68HC908QT4 and MC68HC908QY4

• 1536 bytes of user FLASH for MC68HC908QT2, MC68HC908QT1, MC68HC908QY2, and MC68HC908QY1

• 128 bytes of random access memory (RAM)

• 48 bytes of user-defined vectors, located in FLASH

• 416 bytes of monitor read-only memory (ROM)

• 1536 bytes of FLASH program and erase routines, located in ROM

2.2 Unimplemented Memory Locations

Accessing an unimplemented location can have unpredictable effects on MCU operation. In Figure 2-1 and in register figures in this document, unimplemented locations are shaded.

2.3 Reserved Memory Locations

Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-1 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R.



Memory

$0000↓

$003F

I/O REGISTERS64 BYTES

Note 1. Attempts to execute code from addresses in this range will generate an illegal address reset.

$0040↓

$007F

RESERVED(1)

64 BYTES

$0080↓

$00FF

RAM128 BYTES

$0100↓

$27FF

UNIMPLEMENTED(1)

9984 BYTES

$2800↓

$2DFF

AUXILIARY ROM 1536 BYTES

$2E00↓

$EDFF

UNIMPLEMENTED(1)

49152 BYTES UNIMPLEMENTED51712 BYTES

$2E00

↓

$F7FF$EE00

↓$FDFF

FLASH MEMORYMC68HC908QT4 AND MC68HC908QY4

4096 BYTESFLASH MEMORY

1536 BYTES

$F800↓

$FDFF

$FE00 BREAK STATUS REGISTER (BSR) MC68HC908QT1, MC68HC908QT2, MC68HC908QY1, and MC68HC908QY2

Memory Map$FE01 RESET STATUS REGISTER (SRSR)

$FE02 BREAK AUXILIARY REGISTER (BRKAR)

$FE03 BREAK FLAG CONTROL REGISTER (BFCR)

$FE04 INTERRUPT STATUS REGISTER 1 (INT1)



$FE07 RESERVED FOR FLASH TEST CONTROL REGISTER (FLTCR)

$FE08 FLASH CONTROL REGISTER (FLCR)

$FE09 BREAK ADDRESS HIGH REGISTER (BRKH)

$FE0A BREAK ADDRESS LOW REGISTER (BRKL)

$FE0B BREAK STATUS AND CONTROL REGISTER (BRKSCR)

$FE0C LVISR

$FE0D↓

$FE0F

RESERVED FOR FLASH TEST 3 BYTES

$FE10↓

$FFAFMONITOR ROM 416 BYTES

$FFB0↓

$FFBD

FLASH14 BYTES

$FFBE FLASH BLOCK PROTECT REGISTER (FLBPR)

$FFBF RESERVED FLASH

$FFC0 INTERNAL OSCILLATOR TRIM VALUE (VDD = 5.0 V)

$FFC1 INTERNAL OSCILLATOR TRIM VALUE (VDD = 3.0 V)

$FFC2↓

$FFCF

FLASH14 BYTES

$FFD0↓

$FFFF

USER VECTORS48 BYTES

Figure 2-1. Memory Map



Input/Output (I/O) Section

2.4 Input/Output (I/O) Section

Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have these addresses:

• $FE00 — Break status register, BSR

• $FE01 — Reset status register, SRSR

• $FE02 — Break auxiliary register, BRKAR

• $FE03 — Break flag control register, BFCR

• $FE04 — Interrupt status register 1, INT1



• $FE07 — Reserved

• $FE08 — FLASH control register, FLCR

• $FE09 — Break address register high, BRKH

• $FE0A — Break address register low, BRKL

• $FE0B — Break status and control register, BRKSCR

• $FE0C — LVI status register, LVISR

• $FE0D — Reserved

• $FFBE — FLASH block protect register, FLBPR

• $FFC0 — Internal OSC trim value (factory programmed, VDD = 5.0 V)

• $FFC1 — Internal OSC trim value (factory programmed, VDD = 3.0 V)

• $FFFF — COP control register, COPCTL

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0

$0000Port A Data Register

(PTA)See page 98.

Read:R

AWULPTA5 PTA4 PTA3

PTA2PTA1 PTA0

Write:

Reset: Unaffected by reset

$0001Port B Data Register

(PTB)See page 100.

Read:PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0

Write:


$0002 Unimplemented

$0003 Unimplemented

$0004Data Direction Register A

(DDRA)See page 98.

Read:R R DDRA5 DDRA4 DDRA3

0DDRA1 DDRA0

Write:

Reset: 0 0 0 0 0 0 0 0

$0005Data Direction Register B

(DDRB)See page 101.

Read:DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

Write:

Reset: 0 0 0 0 0 0 0 0

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)



Memory

$0006↓

$000A

Unimplemented

Unimplemented

$000BPort A Input Pullup Enable

Register (PTAPUE)See page 99.

Read:OSC2EN

0PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0

Write:

Reset: 0 0 0 0 0 0 0 0

$000CPort B Input Pullup Enable

Register (PTBPUE)See page 102.

Read:PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE1 PTBPUE0

Write:

Reset: 0 0 0 0 0 0 0 0

$000D↓

$0019Unimplemented

$001AKeyboard Status and

Control Register (KBSCR)See page 83.

Read: 0 0 0 0 KEYF 0IMASKK MODEK

Write: ACKK

Reset: 0 0 0 0 0 0 0 0

$001BKeyboard Interrupt

Enable Register (KBIER)See page 84.

Read: 0AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0

Write:

Reset: 0 0 0 0 0 0 0 0

$001C Unimplemented

$001DIRQ Status and Control

Register (INTSCR)See page 77.

Read: 0 0 0 0 IRQF 0IMASK MODE

Write: ACK

Reset: 0 0 0 0 0 0 0 0

$001EConfiguration Register 2

(CONFIG2)(1)

See page 53.

Read:IRQPUD IRQEN R OSCOPT1 OSCOPT0 R R RSTEN

Write:

Reset: 0 0 0 0 0 0 0 0(2)

1. One-time writable register after each reset. 2. RSTEN reset to 0 by a power-on reset (POR) only.

$001FConfiguration Register 1

(CONFIG1)(1)

See page 54.

Read:COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD

Write:

Reset: 0 0 0 0 0(2) 0 0 0

1. One-time writable register after each reset. 2. LVI5OR3 reset to 0 by a power-on reset (POR) only.

$0020TIM Status and Control

Register (TSC)See page 127.

Read: TOFTOIE TSTOP

0 0PS2 PS1 PS0

Write: 0 TRST

Reset: 0 0 1 0 0 0 0 0

$0021TIM Counter Register High

(TCNTH)See page 128.

Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Write:

Reset: 0 0 0 0 0 0 0 0







$0022TIM Counter Register Low

(TCNTL)See page 128.

Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Write:

Reset: 0 0 0 0 0 0 0 0

$0023TIM Counter Modulo

Register High (TMODH)See page 129.

Read:Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Write:

Reset: 1 1 1 1 1 1 1 1

$0024TIM Counter Modulo

Register Low (TMODL)See page 129.


Write:

Reset: 1 1 1 1 1 1 1 1

$0025TIM Channel 0 Status and

Control Register (TSC0)See page 130.

Read: CH0FCH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

Write: 0

Reset: 0 0 0 0 0 0 0 0

$0026TIM Channel 0

Register High (TCH0H)See page 132.


Write:

Reset: Indeterminate after reset

$0027TIM Channel 0

Register Low (TCH0L)See page 132.


Write:


$0028TIM Channel 1 Status and

Control Register (TSC1)See page 130.

Read: CH1FCH1IE

0MS1A ELS1B ELS1A TOV1 CH1MAX

Write: 0

Reset: 0 0 0 0 0 0 0 0

$0029TIM Channel 1

Register High (TCH1H)See page 132.


Write:


$002ATIM Channel 1

Register Low (TCH1L)See page 132.


Write:


$002B↓

$0035Unimplemented

$0036Oscillator Status Register

(OSCSTAT)See page 96.

Read:R R R R R R ECGON

ECGST

Write:

Reset: 0 0 0 0 0 0 0 0

$0037 Unimplemented Read:

$0038

Oscillator Trim Register(OSCTRIM)

See page 96.

Read:TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0

Write:

Reset: 1 0 0 0 0 0 0 0






Memory

$0039↓

$003BUnimplemented

$003CADC Status and Control

Register (ADSCR)See page 45.

Read: COCOAIEN ADCO CH4 CH3 CH2 CH1 CH0

Write: R

Reset: 0 0 0 1 1 1 1 1

$003D Unimplemented

$003EADC Data Register

(ADR)See page 47.


Write:


$003FADC Input Clock Register

(ADICLK)See page 47.

Read:ADIV2 ADIV1 ADIV0

0 0 0 0 0

Write:

Reset: 0 0 0 0 0 0 0 0

$FE00Break Status Register

(BSR)See page 137.

Read:R R R R R R

SBSWR

Write: See note 1

Reset: 0

1. Writing a 0 clears SBSW.

$FE01SIM Reset Status Register

(SRSR)See page 117.

Read: POR PIN COP ILOP ILAD MODRST LVI 0

Write:

POR: 1 0 0 0 0 0 0 0

$FE02Break Auxiliary

Register (BRKAR)See page 137.

Read: 0 0 0 0 0 0 0BDCOP

Write:

Reset: 0 0 0 0 0 0 0 0

$FE03Break Flag Control

Register (BFCR)See page 138.

Read:BCFE R R R R R R R

Write:

Reset: 0

$FE04Interrupt Status Register 1

(INT1)See page 77.

Read: 0 IF5 IF4 IF3 0 IF1 0 0

Write: R R R R R R R R

Reset: 0 0 0 0 0 0 0 0


(INT2)See page 77.

Read: IF14 0 0 0 0 0 0 0


Reset: 0 0 0 0 0 0 0 0


(INT3)See page 77.

Read: 0 0 0 0 0 0 0 IF15


Reset: 0 0 0 0 0 0 0 0

$FE07 Reserved R R R R R R R R







$FE08FLASH Control Register

(FLCR)See page 34.

Read: 0 0 0 0HVEN MASS ERASE PGM

Write:

Reset: 0 0 0 0 0 0 0 0

$FE09Break Address High

Register (BRKH)See page 136.


Write:

Reset: 0 0 0 0 0 0 0 0

$FE0ABreak Address low

Register (BRKL)See page 136.


Write:

Reset: 0 0 0 0 0 0 0 0

$FE0BBreak Status and Control

Register (BRKSCR)See page 136.

Read:BRKE BRKA

0 0 0 0 0 0

Write:

Reset: 0 0 0 0 0 0 0 0

$FE0CLVI Status Register

(LVISR)See page 87.

Read: LVIOUT 0 0 0 0 0 0 R

Write:

Reset: 0 0 0 0 0 0 0 0

$FE0D↓

$FE0FReserved for FLASH Test R R R R R R R R

$FFBEFLASH Block Protect

Register (FLBPR)See page 39.

Read:BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

Write:


$FFBF Reserved R R R R R R R R

$FFC0Internal Oscillator Trim(Factory Programmed,

VDD = 5.0 V)


Write:


$FFC1 Internal Oscillator Trim(Factory Programmed,

VDD = 3.0 V)


Write:


$FFFFCOP Control Register

(COPCTL)See page 59.

Read: LOW BYTE OF RESET VECTOR

Write: WRITING CLEARS COP COUNTER (ANY VALUE)







Memory

.

2.5 Random-Access Memory (RAM)

Addresses $0080–$00FF are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.

NOTEFor correct operation, the stack pointer must point only to RAM locations.

Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save the contents of the CPU registers.

NOTEFor M6805, M146805, and M68HC05 compatibility, the H register is not stacked.

During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls.

NOTEBe careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.

Table 2-1. Vector Addresses

Vector Priority Vector Address Vector

Lowest

Highest

IF15$FFDE ADC conversion complete vector (high)

$FFDF ADC conversion complete vector (low)

IF14$FFE0 Keyboard vector (high)

$FFE1 Keyboard vector (low)

IF13↓

IF6— Not used

IF5$FFF2 TIM overflow vector (high)

$FFF3 TIM overflow vector (low)

IF4$FFF4 TIM Channel 1 vector (high)

$FFF5 TIM Channel 1 vector (low)

IF3$FFF6 TIM Channel 0 vector (high)

$FFF7 TIM Channel 0 vector (low)

IF2 — Not used

IF1$FFFA IRQ vector (high)

$FFFB IRQ vector (low)

—$FFFC SWI vector (high)

$FFFD SWI vector (low)

—$FFFE Reset vector (high)

$FFFF Reset vector (low)



FLASH Memory (FLASH)

2.6 FLASH Memory (FLASH)

This subsection describes the operation of the embedded FLASH memory. The FLASH memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump.

The FLASH memory consists of an array of 4096 or 1536 bytes with an additional 48 bytes for user vectors. The minimum size of FLASH memory that can be erased is 64 bytes; and the maximum size of FLASH memory that can be programmed in a program cycle is 32 bytes (a row). Program and erase operations are facilitated through control bits in the FLASH control register (FLCR). Details for these operations appear later in this section. The address ranges for the user memory and vectors are:

• $EE00 – $FDFF; user memory, 4096 bytes: MC68HC908QY4 and MC68HC908QT4

• $F800 – $FDFF; user memory, 1536 bytes: MC68HC908QY2, MC68HC908QT2, MC68HC908QY1 and MC68HC908QT1

• $FFD0 – $FFFF; user interrupt vectors, 48 bytes.

NOTEAn erased bit reads as a 1 and a programmed bit reads as a 0.A security feature prevents viewing of the FLASH contents.(1)

2.6.1 FLASH Control Register

The FLASH control register (FLCR) controls FLASH program and erase operations.

HVEN — High Voltage Enable BitThis read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. It can only be set if either PGM =1 or ERASE =1 and the proper sequence for program or erase is followed.

1 = High voltage enabled to array and charge pump on0 = High voltage disabled to array and charge pump off

MASS — Mass Erase Control BitThis read/write bit configures the memory for mass erase operation.

1 = Mass erase operation selected0 = Mass erase operation unselected

1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users.

Address: $FE08

Bit 7 6 5 4 3 2 1 Bit 0

Read: 0 0 0 0HVEN MASS ERASE PGM

Write:

Reset: 0 0 0 0 0 0 0 0

= Unimplemented

Figure 2-3. FLASH Control Register (FLCR)



Memory

ERASE — Erase Control BitThis read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time.

1 = Erase operation selected0 = Erase operation unselected

PGM — Program Control BitThis read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time.

1 = Program operation selected0 = Program operation unselected

2.6.2 FLASH Page Erase Operation

Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 48-byte user interrupt vectors area also forms a page. Any FLASH memory page can be erased alone.

1. Set the ERASE bit and clear the MASS bit in the FLASH control register.2. Read the FLASH block protect register.3. Write any data to any FLASH location within the address range of the block to be erased. 4. Wait for a time, tNVS (minimum 10 μs).5. Set the HVEN bit.6. Wait for a time, tErase (minimum 1 ms or 4 ms).7. Clear the ERASE bit.8. Wait for a time, tNVH (minimum 5 μs).9. Clear the HVEN bit.

10. After time, tRCV (typical 1 μs), the memory can be accessed in read mode again.

NOTEProgramming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.

CAUTIONA page erase of the vector page will erase the internal oscillator trim values at $FFC0 and $FFC1.

In applications that require more than 1000 program/erase cycles, use the 4 ms page erase specification to get improved long-term reliability. Any application can use this 4 ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time.




2.6.3 FLASH Mass Erase Operation

Use the following procedure to erase the entire FLASH memory to read as a 1:1. Set both the ERASE bit and the MASS bit in the FLASH control register.2. Read the FLASH block protect register.3. Write any data to any FLASH address(1) within the FLASH memory address range.4. Wait for a time, tNVS (minimum 10 μs).5. Set the HVEN bit.6. Wait for a time, tMErase (minimum 4 ms).7. Clear the ERASE and MASS bits.

NOTEMass erase is disabled whenever any block is protected (FLBPR does not equal $FF).

8. Wait for a time, tNVHL (minimum 100 μs).9. Clear the HVEN bit.

10. After time, tRCV (typical 1 μs), the memory can be accessed in read mode again.

NOTEProgramming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.

CAUTIONA mass erase will erase the internal oscillator trim values at $FFC0 and $FFC1.

2.6.4 FLASH Program Operation

Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, or $XXE0. Use the following step-by-step procedure to program a row of FLASH memory

Figure 2-4 shows a flowchart of the programming algorithm.

NOTEOnly bytes which are currently $FF may be programmed.

1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming.

2. Read the FLASH block protect register.3. Write any data to any FLASH location within the address range desired.4. Wait for a time, tNVS (minimum 10 μs).5. Set the HVEN bit.6. Wait for a time, tPGS (minimum 5 μs).7. Write data to the FLASH address being programmed(2).

1. When in monitor mode, with security sequence failed (see 15.3.2 Security), write to the FLASH block protect register instead of any FLASH address.



Memory

8. Wait for time, tPROG (minimum 30 μs).9. Repeat step 7 and 8 until all desired bytes within the row are programmed.

10. Clear the PGM bit(1).11. Wait for time, tNVH (minimum 5 μs).12. Clear the HVEN bit.13. After time, tRCV (typical 1 μs), the memory can be accessed in read mode again.

NOTEThe COP register at location $FFFF should not be written between steps 5–12, when the HVEN bit is set. Since this register is located at a valid FLASH address, unpredictable behavior may occur if this location is written while HVEN is set.

This program sequence is repeated throughout the memory until all data is programmed.

NOTEProgramming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Do not exceed tPROG maximum, see 16.16 Memory Characteristics.

2.6.5 FLASH Protection

Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations.

NOTEIn performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit.

When the FLBPR is programmed with all 0 s, the entire memory is protected from being programmed and erased. When all the bits are erased (all 1’s), the entire memory is accessible for program and erase.

When bits within the FLBPR are programmed, they lock a block of memory. The address ranges are shown in 2.6.6 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than $FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass erase is disabled whenever any block is protected (FLBPR does not equal $FF). The FLBPR itself can be erased or programmed only with an external voltage, VTST, present on the IRQ pin. This voltage also allows entry from reset into the monitor mode.

2. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time, tPROG maximum.




Figure 2-4. FLASH Programming Flowchart

SET HVEN BIT

WRITE ANY DATA TO ANY FLASH ADDRESS

WITHIN THE ROW ADDRESS RANGE DESIRED

WAIT FOR A TIME, tNVS

SET PGM BIT

WAIT FOR A TIME, tPGS

WRITE DATA TO THE FLASH ADDRESSTO BE PROGRAMMED

WAIT FOR A TIME, tPROG

CLEAR PGM BIT

WAIT FOR A TIME, tNVH

CLEAR HVEN BIT

WAIT FOR A TIME, tRCV

COMPLETEDPROGRAMMING

THIS ROW?

Y

N

END OF PROGRAMMING

The time between each FLASH address change (step 7 to step 7),

must not exceed the maximum programmingtime, tPROG max.

or the time between the last FLASH address programmedto clearing PGM bit (step 7 to step 10)

NOTES:

1

3

4

5

6

7

8

10

11

12

13

Algorithm for Programminga Row (32 Bytes) of FLASH Memory

This row program algorithm assumes the row/sto be programmed are initially erased.

9

READ THE FLASH BLOCK PROTECT REGISTER2



Memory

2.6.6 FLASH Block Protect Register

The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting address of the protected range within the FLASH memory.

BPR[7:0] — FLASH Protection Register Bits [7:0]These eight bits in FLBPR represent bits [13:6] of a 16-bit memory address. Bits [15:14] are 1s and bits [5:0] are 0s.

The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 within the FLASH memory. See Figure 2-6 and Table 2-2.

Figure 2-6. FLASH Block Protect Start Address

Address: $FFBE

Bit 7 6 5 4 3 2 1 Bit 0

Read:BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

Write:

Reset: Unaffected by reset. Initial value from factory is 1.

Write to this register is by a programming sequence to the FLASH memory.

Figure 2-5. FLASH Block Protect Register (FLBPR)

Table 2-2. Examples of Protect Start Address

BPR[7:0] Start of Address of Protect Range

$00–$B8 The entire FLASH memory is protected.

$B9 (1011 1001) $EE40 (1110 1110 0100 0000)

$BA (1011 1010) $EE80 (1110 1110 1000 0000)

$BB (1011 1011) $EEC0 (1110 1110 1100 0000)

$BC (1011 1100) $EF00 (1110 1111 0000 0000)

and so on...

$DE (1101 1110) $F780 (1111 0111 1000 0000)

$DF (1101 1111) $F7C0 (1111 0111 1100 0000)

$FE (1111 1110)$FF80 (1111 1111 1000 0000)

FLBPR, internal oscillator trim values, and vectors are protected

$FF The entire FLASH memory is not protected.

0000011 FLBPR VALUESTART ADDRESS OF

16-BIT MEMORY ADDRESS

FLASH BLOCK PROTECT0




2.6.7 Wait Mode

Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive.

The WAIT instruction should not be executed while performing a program or erase operation on the FLASH, or the operation will discontinue and the FLASH will be on standby mode.

2.6.8 Stop Mode

Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive.

The STOP instruction should not be executed while performing a program or erase operation on the FLASH, or the operation will discontinue and the FLASH will be on standby mode

NOTEStandby mode is the power-saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is at a minimum.



Memory



Chapter 3 Analog-to-Digital Converter (ADC)

3.1 Introduction

This section describes the analog-to-digital converter (ADC). The ADC is an 8-bit, 4-channel analog-to- digital converter. The ADC module is only available on the MC68HC908QY2, MC68HC908QT2, MC68HC908QY4, and MC68HC908QT4.

3.2 Features

Features of the ADC module include:

• 4 channels with multiplexed input

• Linear successive approximation with monotonicity

• 8-bit resolution

• Single or continuous conversion

• Conversion complete flag or conversion complete interrupt

• Selectable ADC clock frequency

3.3 Functional Description

Four ADC channels are available for sampling external sources at pins PTA0, PTA1, PTA4, and PTA5. An analog multiplexer allows the single ADC converter to select one of the four ADC channels as an ADC voltage input (ADCVIN). ADCVIN is converted by the successive approximation register-based counters. The ADC resolution is eight bits. When the conversion is completed, ADC puts the result in the ADC data register and sets a flag or generates an interrupt.

Figure 3-2 shows a block diagram of the ADC.

3.3.1 ADC Port I/O Pins

PTA0, PTA1, PTA4, and PTA5 are general-purpose I/O pins that are shared with the ADC channels. The channel select bits (ADC status and control register (ADSCR), $003C), define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a 0 if the corresponding DDR bit is at 0. If the DDR bit is at 1, the value in the port data latch is read.



Analog-to-Digital Converter (ADC)

Figure 3-1. Block Diagram Highlighting ADC Block and Pins

PTA0/AD0/TCH0/KBI0

PTA1/AD1/TCH1/KBI1

PTA2/IRQ/KBI2/TCLK

PTA3/RST/KBI3

PTA4/OSC2/AD2/KBI4

PTA5/OSC1/AD3/KBI5

KEYBOARD INTERRUPTMODULE

CLOCKGENERATOR

(OSCILLATOR)

SYSTEM INTEGRATIONMODULE

SINGLE INTERRUPTMODULE

BREAKMODULE

POWER-ON RESETMODULE

16-BIT TIMERMODULE

COPMODULE

MONITOR ROM

PTB0PT

B

DD

RB

M68HC08 CPU

PTA

DD

RA

PTB1PTB2PTB3PTB4PTB5PTB6PTB7

8-BIT AD

mc68hc908qy4, mc68hc908qy4, mc68hc908qt4, … · 2016. 8. 29. · 4 freescale semiconductor the...

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