mc te3001 chapter 3 architecture pic18 1

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TE3001 Microcontrollers Chapter #3

PIC18F4585 Architecture

2 Dr. Rodolfo J. Castelló Z.

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Dr. Rodolfo J. Castelló Z. 3

  4 16 bits-timers (T0 – T3).

  5 I/O ports (A, B, C, D, y E) .

  Serial port, parallel communication, and A/D converter of 10 bits and 11 channels.


  PIC18 Clock Sources

Source: “PIC18C Reference Manual”, Microchip DS39500a, 2000

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Mode Description EC External Clock ECIO External Clock with I/O pin enabled LP Low Frequency (Power) Crystal XT Crystal/Resonator HS High Speed Crystal/Resonator RC External Resistor/Capacitor RCIO External Resistor/Capacitor with I/O pin enabled HS4 High Speed Crystal/Resonator with 4x fequency

PLL multiplier enabled



Bit Sym-bol

Reset value

Description

0 SCS 0 System Clock Switch bit: 1 = Timer1 Oscillator is the system clock 0 = Use External clock

1 – 7 - Unimplemented bits. Read as “0”


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FOSC2:FOSC0 Configuration Bits

Oscillator Mode

111 RCIO 110 HS4 101 ECIO 100 EC 011 RC 010 HS 001 XT 000 LP


  PIC18F4585 Clock Sources

Source: “PIC18F4585 Data Sheet”, Microchip DS39625C, 2007

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Mode Description EC External Clock ECIO External Clock with I/O pin enabled LP Low Frequency (Power) Crystal XT Crystal/Resonator HS High Speed Crystal/Resonator RC External Resistor/Capacitor with FOSC/4 output on RA6 RCIO External Resistor/Capacitor with I/O on RA6 HSPLL High Speed Crystal/Resonator with PLL multiplier enabled INTIO1 Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 INTIO2 Internal Oscillator with I/O on RA6 and RA7


Bit Symbol Reset value

Description

0 - 1 SCS1:SCS0 00 System Clock Select bits: 1x = Internal Oscillator Block 01 = Timer1 Oscillator 00 = Primary Oscillator specified by FOSC3:FOSC0 of CONFIG1H

2 IOFS 0 INTOSC Frequency Stable bit 1 = Stable. 0 = Not stable

3 OSTS 0 Oscillator Start-up time-out status bit

6 - 4 IRCF2:IRCF0 100 Internal Oscillator Frequency Select Bits 111 = 8MHz 011 = 500KHz 110 = 4MHz 010 = 250KHz 101 = 2MHz 001 =125KHz 100 = 1MHz 000 = 31KHz

7 IDLEN 0 Idle Enable Bit




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FOSC3:FOSC0 Configuration

Bits

Oscillator Mode

11xx RC 1001 INTIO1 1000 INTIO2 0111 RCIO 0110 HSPLL 0101 EC 0100 ECIO



FOSC3:FOSC0 Configuration

Bits

Oscillator Mode

0001 XT 0000 LP


Program Memory (Flash) Processor

Data Memory

(SFR’s and GP RAM)

21 lines

16 lines

Program’s Address Bus

Instruction’s Bus

12 lines

Data’s Address Bus

8 lines

Data Bus

2M Program

Space

16 bits Opcode

4K (212= 4096)

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Program Memory (Flash)

PC

31 Levels Stack

Address

IR

Instruction Decoder

16

Internal Resources

Clock

MPX

FSR’s

Data Memory (SRAM)

21

12

Address

I/O Ports

Timers

EEPROM

A/D Converter

Serial Port

Parallel Port

8

8

8

ALU

8

W (accumulator)

8

8

STATUS

12

12

BSR 4

Access Bank

4


8



9


  PIC18F4585 Program Memory

2 MB

48 KB @ el PIC18F4585

Code Memory

Reset Vector 0000H

0008H

BFFFH

1FFFFFH

PC 0 20

21

Address

21

Level 1

Level 31

0 20

0 20 Stack

0018H

Internal Program Memory

C000H

7 0

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  SFRs to Control Program Memory

Data Bus <8>

0 7 8 15 16 20

PCLATH PCLATU

8 8

<20 – 0>

Address Bus

31 Level Stack

8

10

19

20

11

21

  Code Storage in Program Memory

Address Contents Instruction Operand(s) 000000H

000001H

000002H 0x55 MOVLW 0x55 000003H 0x0F 000004H 0x23 MOVFF 0x123, 0x456 000005H 0xC1 000006H 0x56 000007H 0x04


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  RAM Data Memory Map for the PIC 18 Family Bank #

0 00H 000H – 07FH

FFH GPRs 080H – 0FFH

1 00H 100H

FFH 1FFH

2 00H 200H

FFH 2FFH

13 00H D00H

FFH DFFH

14 00H E00H

FFH EFFH

15 00H F00H – F7FH

FFH SFRs F80H – FFFH

BSR <3 – 0> """"

""""

""""

GPRs SFRs

00H

7FH 80H

FFH

Access Bank

See Data Sheet for each PIC


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  Bank Select Register (BSR)

Data Memory 0 Bank # 0 00H – FFH

1 Bank # 1 00H – FFH




C Bank # 12 00H – FFH

D Bank # 13 00H – FFH

E Bank # 14 00H – FFH

F Bank # 15 00H – FFH

"""

7 0 1 1 1 1 1 1 1 1

7 0 0 0 0 0 1 1 0 0


  Bank Select Register (BSR)

  The only instruction from PIC18 core instruction set that fully specifies by itself the 12-bit address of both, the source and target registers, is MOVFF.

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GPRs SFRs

00H

7FH 80H

FFH

Access Bank


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  I/O Ports.   Interruptions.   Serial Port.   Timers.   A/D Converters.   CPU Functionality.

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  Bank #15, PIC18 Basic SFRs Set F80h FA0h PIE2 FC0h FE0hF81h FA1h PIR2 FC1h ADCON1 FE1hF82h FA2h IPR2 FC2h ADCON0 FE2hF83h FA3h FC3h ADRESL FE3h PLUSW1F84h FA4h FC4h ADRESH FE4h PREINC1F85h FA5h FC5h SSPCON2 FE5h POSTDEC1F86h FA6h FC6h SSPCON1 FE6h POSTINC1F87h FA7h FC7h SSPSTAT FE7h INDF1F88h FA8h FC8h SSPADD FE8hF89h LATA FA9h FC9h SSPBUF FE9hF8Ah LATB FAAh FCAh T2CON FEAhF8Bh LATC FABh RCSTA FCBh PR2 FEBh PLUSW0F8Ch LATD FACh TXSTA FCCh TMR2 FECh PREINC0F8Dh LATE FADh TXREG FCDh T1CON FEDh POSTDEC0F8Eh FAEh RCREG FCEh TMR1L FEEh POSTINC0F8Fh FAFh SPBRG FCFh TMR1H FEFh INDF0F90h FB0h FD0h RCON FF0h INTCON3F91h FB1h T3CON FD1h WDTCON FF1h INTCON2F92h FB2h TMR3L FD2h LVDCON FF2h INTCONF93h FB3h TMR3H FD3h OSCCON FF3h PRODLF94h FB4h FD4h FF4h PRODHF95h FB5h FD5h T0CON FF5h TABLATF96h FB6h FD6h TMR0L FF6h TBLPTRL

F97h FB7h FD7h TMR0H FF7h TBLPTRH

F98h FB8h FD8h FF8h TBLPTRU

F99h FB9h FD9h FF9h PCL

F9Ah FBAh CCP2CON FDAh FFAh PCLATH

F9Bh FBBh CCPR2L FDBh PLUSW2 FFBh PCLATU

F9Ch FBCh CCPR2H FDCh PREINC2 FFChF9Dh PIE1 FBDh CCP1CON FDDh POSTDEC2 FFDh TOSLF9Eh PIR1 FBEh CCPR1L FDEh POSTINC2 FFEh TOSHF9Fh IPR1 FBFh CCPR1H FDFh INDF2 FFFh TOSU


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ALU

WREG

STATUS

Data

N, OV, Z, DC, C

Carry Bit

8 Bits

8 Bits


Bit Sym-bol

Reset value

Description

0 C R/W-x Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF) 1 = A carry-out from the MSb of the result occurred 0 = No carry

1 DC R/W-x Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF) 1 = A carry-out of the Least Significant Nibble’s Msb of the result occurred 0 = No carry-out from the 4th low order bit of the result

2 Z R/W-x Zero Bit 1 = The result of an arithmetic or logic operation is cero. 0 = The result of an arithmetic or logic operation is NO cero.

3 OV R/W-x Overflow Bit 1 = Overflow on bit 7 for arithmetic signed operations. 0 = No overflow.

4 N R/W-x Negative Bit 1 = Result was negative, when the MSb = 1 0 = Result was positive.

5-7 U-O Unimplemented, read as‘0’

Significado de los valores de Reset

R – Readable bit 1 - Bit is set x – Bit is unknown

W – Writable bit 0 – Bit is cleared U – Unimplemented bit, read as “0”

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  PIC18F4585 Pin Out


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  I/O Ports

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  I/O Ports


Bit Function Description Default Function (POR)

RA0 AN0/CVREF A/D input channel 0 / Comparator Voltage ref As Analog Inputs (AN0)

RA1 AN1 A/D input channel 1 As Analog Inputs (AN1)

RA2 AN2/VREF- A/D input channel 2 / Negative Voltage ref. As Analog Inputs (AN2)

RA3 AN3/VREF+ A/D input channel 3 / Positive Voltage reg. As Analog Inputs (AN3)

RA4 T0CKI TIMER 0 External Clock Signal Input As Digital Input (RA4)

RA5 AN4/SS A/D input channel 4 As Analog Inputs (AN4)

RA6 OSC2 External Oscillator As Digital Input (RA6)

RA7 OSC1 External Oscillator External RC Oscillator

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  Port A

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MOVLW 0x00 ; WREG = 0 MOVWF TRISA ; PORT A as output MOVLW 0x3A ; WREG = 0x3A MOVWF PORTA ; Write 0x3A to PORT A

MOVLW 0xFF ; WREG = 255 MOVWF TRISA ; PORT A as input MOVFF PORTA, W ; WREG = PORT A



RB0 AN10/INT0 A/D channel 10 / External Interruption #0 As Analog Inputs (AN10)

RB1 AN8/INT1 A/D channel 8 / External Interruption #1 As Analog Inputs (AN8)

RB2 CANTX/INT2 CAN transmit / External Interruption #2. As Analog Inputs

RB3 CANRX CAN receive As Analog Inputs

RB4 AN9/KBIO A/D channel 9 / Interrupt on pin change As Analog Inputs (AN9)

RB5 KBI1 Interrupt on pin change As Digital Input



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  Port B

list p=18f4585 #include "p18f4585.inc"

CONFIG PBADEN = OFF ; CONFIG3H.1 = 0: RBO – RB4 digital CONFIG LVP= OFF ; CONFIG4L.2 = 0: RB5 digital

MOVLW 0x0F ; WREG = 0x07 MOVWF ADCON1 ; Disables A/D Converter

CLRF PORTB ; PORTB reset CLRF LATB ; Clears latch MOVLW 0xFF / 0x00 ; Set bits as inputs or outputs MOVWF TRISB

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  Their double functionality is activated when the related devices are used. (see data sheet)


  Port C

CLRF PORTC ; PORTC reset CLRF LATC ; Clears latch MOVLW 0xFF / 0x00 ; Set bits as inputs or outputs MOVWF TRISC

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Bit Function Description Default Funtion (POR)

RD0 PSP0/C1IN+ Parallel Slave Port / Comparator 1 Pos IN Comparator 1 Pos IN (C1IN+)

RD1 PSP1/C1IN- Parallel Slave Port / Comparator 1 Neg IN Comparator 1 Neg IN (C1IN-)

RD2 PSP2/C2IN+ Parallel Slave Port / Comparator 2 Pos IN Comparator 2 Pos IN (C2IN)

RD3 PSP3/C2IN- Parallel Slave Port / Comparator 2 Neg IN Comparator 2 Neg IN (C2IN-)

RD4 PSP4/ECCP1 Parallel Slave Port / Comparator Out I/O Digital





  Port D

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  Port D

MOVLW 0x07 ; WREG = 0x07 MOVWF CMCON ; Disables Comparators CM2:CM0 = 111

CLRF PORTD ; PORTD reset CLRF LATD ; Clears latch MOVLW 0xFF / 0x00 ; Set bits as inputs or outputs MOVWF TRISD



RE0 AN5 A/D channel 5 As Analog Inputs (AN5)



RE3 MCLR External Reset Input Master Reset

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  Read Followed by Write I/O Operation

CLRF TRISB ;PORTB as Output SETF TRISC ;PORTC as Input loop MOVF PORTC, W ;WREG PORTC MOVWF PORTB ;PORTB WREG BRA loop

✗

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  Read After Write (RAW) cycle:

Meaning of Letter Values

Fetch D R P W

Instruction MOVF PORTC, W ;WREG Port C

MOVWF PORTB ;Port B WREG Fetch D R P W



CLRF TRISB ;PORTB as Output SETF TRISC ;PORTC as Input loop MOVF PORTC, W ;WREG PORTC

NOP MOVWF PORTB ;PORTB WREG BRA loop

✓ CLRF TRISB ;PORTB as Output

SETF TRISC ;PORTC as Input loop MOVFF PORTC, PORTB ;PORTB PORTC

BRA loop ✓

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  Some of the features that can be configured are:   Oscillator selection,   Type of Resets,   Interruptions,   Code Protection.   Etc see data sheet.


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59

  Configuration Registers FLASH ROM`

CONFIG1H

CONFIG2L

CONFIG2H

CONFIG3H

CONFIG4L

CONFIG5L

CONFIG5H

CONFIG6L

CONFIG6H

CONFIG7L

CONFIG7H

DEVID1

DEVID2

≈ ≈

≈ ≈

≈ ≈


  The way to set the configuration through table writing will be seen in the following chapter when table operations are introduced.

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  Configuration Registers

32


7.  Minimum System

10KΩ – 100KΩ

27 pF

27 pF

4 MHz

Vcc

mc te3001 chapter 3 architecture pic18 1

Documents

pic18c reference

pic18 clock

pic18f4585

bank select

pin change

pic18f4585

trisb trisc

data sheet