mb86r21 application note ddr3 interface pcb design guideline€¦ · 3 mb86r21 application note...

FUJITSU SEMICONDUCTOR CONFIDENTIAL

MB86R21 Application Note DDR3 Interface

PCB Design Guideline

September, 2012 The 1.0 edition

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MB86R21 Application Note DDR3 Interface PCB Design Guideline


Preface This guideline describes PCB design restrictions related to MB86R21 DDR3 interface signal wiring.

· The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering.

· The information, such as descriptions of function and application circuit examples, in this document are

presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.

· Any information in this document, including descriptions of function and schematic diagrams, shall not be

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· The products described in this document are designed, developed and manufactured as contemplated for

general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

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owners. All rights reserved, Copyright FUJITSU SEMICONDUCTOR LIMITED 2012

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Revision History Date Ver. Contents

2012/9/14 1.0 Newly issued

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Contents 1. Floor plan ............................................................................................................ 1

2. PCB laminating ................................................................................................... 2

3. DDR3_SDRAM specifications ............................................................................ 3

4. Signal design restrictions (DDR3 interface part) ............................................. 4

4.1. Definition of signal line group ................................................................................................................ 4 4.2. General wiring restrictions ...................................................................................................................... 5 4.3. Resistance ................................................................................................................................................ 5 4.4. Termination resistor/Wire length ............................................................................................................. 6 4.5. Wiring gap/Crosstalk ............................................................................................................................... 7 4.6. ZQ/ODT setting ...................................................................................................................................... 8 4.7. Wiring topology ...................................................................................................................................... 9

4.7.1. Wiring topology diagram of MCKx_Group .................................................................................... 9 4.7.2. Wiring topology diagram of MCNTLx_Group and MCMDx_Group ........................................... 10 4.7.3. Wiring topology diagram of MDQSx_Group................................................................................. 11 4.7.4. Wiring topology diagram of MDQx_Group .................................................................................. 12

5. Power system design restrictions .................................................................. 14

5.1. Number and capacity of bypass capacitor ............................................................................................. 14 5.2. Pull-out wiring condition ...................................................................................................................... 15 5.3. VREF pin connection ............................................................................................................................ 16 5.4. VTT power supply design ..................................................................................................................... 17 5.5. ZQRES pin connection ......................................................................................................................... 18

6. Appendix ........................................................................................................... 19

6.1. DQ配線のPCB上の入れ替えについて .............................................................................................. 19 6.2. RESET# signal connection.................................................................................................................... 20

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1. Floor plan Figure 1-1 shows the reference example of the floor plan of MB86R21 and connected DDR3 memory devices.

Figure 1-1 Reference example of the floor plan of MB86R21 and DDR3 memory devices

MB86R21 DRAM

DRAM D

RA

M

DR

AM

27mm

27 mm

10mm 15.5mm

32mm

9mm

7mm

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2. PCB laminating This chapter shows the recommended laminating conditions of the PCB.

Figure 2-1 PCB laminating

Specified condition of wiring layer • L1 and L8 are used as a wiring layer of CLK and a pull-out wiring layer of other signals. • L3 and L6 are used as a wiring layer of DQS, DQ, and CMD/ADD. • L2, L4, L5 and L7 are used as a power/GND layer.

Conductor thickness

Insulator thickness

L1 43μm SIG. (copper foil: 18mm, plating: 25mm) L2 35μm Power/GND L3 35μm SIG. L4 35μm Power/GND L5 35μm Power/GND L6 35μm SIG. L7 35μm Power/GND L8 43μm SIG. (copper foil: 18mm, plating: 25mm)

Resist thickness

40μm 100μm 150μm 150μm 100μm 150μm 150μm 100μm 40μm

Insulation material: relative permittivity=4.3 (only the resist part is 3.9)

Classification

Resist thickness

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3. DDR3_SDRAM specifications This chapter shows DDR3_SDRAM that can be used for the DDR3 interface with MB86R21. If an alternative device fulfills the same requirements, it can also used. Please note however, that if you use an alternative device, there may be differences concerning I/O quality which may require your attention. However, all I/O characteristics should be checked as could differ. Even if you use the device(s) listed below, you must refer to the specifications provided by the DRAM manufacturer for the confirmation of details (e.g. operating temperature conditions etc.).

Table 3-1 Recommended DDR3_SDRAM Manufacturer Product name IBIS model name Driver strength Remarks

Micron Technology, Inc.

MT41J128M16HA-15E (2Gb 1333Mbps)

v69a_at.ibs 34Ω It has already been verified by the transmission line analysis.

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4. Signal design restrictions (DDR3 interface part) This chapter describes the signal wiring design restrictions for the DDR3 interface part.

4.1. Definition of signal line group In order to make the requirements for wiring configurations described further on in this document easier to understand, the DDR3 interface signals are classified into the groups listed below.

Table 4-1 DDR3 interface signal grouping Wiring

preferential order

Group name Pin name of MB86R21

1 MCK_0_Group MCK_0, MXCK_0 MCK_1_Group MCK_1, MXCK_1

2 MDQS0_0_Group MDQS0_0, MXDQS0_0 MDQS1_0_Group MDQS1_0, MXDQS1_0 MDQS2_0_Group MDQS2_0, MXDQS2_0 MDQS3_0_Group MDQS3_0, MXDQS3_0 MDQS0_1_Group MDQS0_1, MXDQS0_1 MDQS1_1_Group MDQS1_1, MXDQS1_1 MDQS2_1_Group MDQS2_1, MXDQS2_1 MDQS3_1_Group MDQS3_1, MXDQS3_1

3 MDQ0_0_Group MDQ0_0~MDQ7_0, MDM0_0 MDQ1_0_Group MDQ8_0~MDQ15_0, MDM1_0 MDQ2_0_Group MDQ16_0~MDQ23_0, MDM2_0 MDQ3_0_Group MDQ24_0~MDQ31_0, MDM3_0 MDQ0_1_Group MDQ0_1~MDQ7_1, MDM0_1 MDQ1_1_Group MDQ8_1~MDQ15_1, MDM1_1 MDQ2_1_Group MDQ16_1~MDQ23_1, MDM2_1 MDQ3_1_Group MDQ24_1~MDQ31_1, MDM3_1

4 MCNTL_0_Group MCKE_0, MXCS_0, MODT_0 MCNTL_1_Group MCKE_1, MXCS_1, MODT_1

5 MCMD_0_Group MA0_0~MA14_0, MBA0_0~MBA2_0, MXCAS_0, MXRAS_0, MXWE_0 MCMD_1_Group MA0_1~MA14_1, MBA0_1~MBA2_1, MXCAS_1, MXRAS_1, MXWE_1

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4.2. General wiring restrictions This section describes the general wiring restrictions. • It is recommended that signal wiring be designed to have the following characteristic impedance.

Single impedance: 50Ω±10% Differential impedance: 100Ω±10%

• Signal wiring on power layer and GND layer should be sufficient width to guarantee the flow of return current. (Signal line should be wired on the same power group or GND group. It must not cross over other power and GND groups.)

• Those signals can be referenced to GND or 1.5V DDR power for DDRVDE/VDDQ supply. When 1.5V DDR power is used as power reference, make single plane and connect DDRVDE and VDDQ each other.

• Please use parallel wiring for the positive and negative signals of the differential MCK_Group and MDQSx_Group signals. In addition, also take care that the position and number of layer vias is the same.

• The DQS/DQ signal (MDQS0_0_Group and MDQ0_0_Group, etc.) that composes the same byte must wire the same layer respectively, and the number of layer transfer vias must become the same, too. There are no restrictions to the number of layer transfer vias for other signals, but use a minimum possible.

• When using meander wiring layouts for signal delay, crosstalk may occur and the delay value reduced, therefore having wider spacing between wirings is recommended. The recommended wire spacing is about five times the wiring width.

Figure 4-1 Meander wiring The recommended conditions and the simulation waveform which are described further on in this document are valid under the above conditions. If your design greatly differs from the above conditions, then please run a simulation on your wiring.

4.3. Resistance • Resistors described in this guideline should be generally selected from the E12 series.

E12 series: 10, 12, 15, 18, 22, 27, 33, 39, 47, 56, 68, 82

• The following resistance tolerance values should be used (according to the resistance type): Termination resistor: under ±5% Divider resistance for VREF: under ±1%

Bevelled corners used in order to reduce signal reflections

Wire spacing

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4.4. Termination resistor/Wire length Table 4-2 shows the recommended resistance value and wire length for each group. The wiring topology diagram relevant to this section is shown in "4.7. Wiring topology".

Table 4-2 Resistance value and wire length list No. Group name External termination

resistor value (Rt)

Wire length from MB86R21 output to SDRAM input

Internal group approved wire length variation

1 MCKx_Group 39Ω × 2 0.1μF capacitor × 1 (Refer to "4.7.1.")

Refer to "4.7.1." Meet the conditions of "4.7.1."

2 MCMDx_Group MCNTLx_Group

39Ω Refer to "4.7.2." Meet the conditions of "4.7.2."

3 MDQSx_Group N/A Refer to "4.7.2." Meet the conditions of "4.7.2."

4 MDQx_Group N/A Refer to "4.7.4." Meet the conditions of "4.7.4."

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4.5. Wiring gap/Crosstalk Please keep to the wiring configurations shown below in order to avoid malfunctions and deteriorated signal integrity due to crosstalk. (1) The recommended gap for wiring within MDQx_Group and MCMDx_Group groups should be over

300µm.

Figure 4-2 Gap for wiring within MDQx_Group and MCMDx_Group

(2) The gap for wiring with other groups should be over 300µm.

Figure 4-3 Gap for wiring of other signal groups (3) Differential wiring signals of MCKx_Group and MDQSx_Group should use a wiring gap of over

500µm to other signals. If it is difficult to guarantee a gap above 500µm, separate the wire from other signals using a GND area. However, please take the consequent decrease of the wiring impedance into consideration.

Figure 4-4 Gap for wiring between signal in MCKx_Group/MDQSx_Group and other signals

A1

Over 300μm

A0 Example: DQ1

Over 300μm

DQ0 Example:

DQ8

Over 300μm

DQ0 Example: A0

Over 300μm

DQ0 Example:

Other signals

Over 500μm

DQS0 Example: Other signals

Over 500μm

CK Example:

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4.6. ZQ/ODT setting Table 4-3 shows the conditions of the driver strength, the termination resistor, and ODT.

Table 4-3 Recommended setting of ZQ/ODT/Termination resistor

Signal Operating condition MB86R21 DRAM Termination

resistor [Ω]

Driver strength [Ω]

ODT [Ω]

Driver strength [Ω]

ODT [Ω]

MCKx_Group Write to DRAM 40 - - - 39x2 +cap0.1u

MCMDx_Group MCNTLx_Group Write to DRAM 60 - - - 39

MDQSx_Group Write to DRAM 48 Off Off 60 - Read from DRAM Off 40 34 Off -

MDQx_Group Write to DRAM 48 Off Off 60 - Read from DRAM Off 40 34 Off -

* Both MB86R21 and DRAM use the ZQ calibration.

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4.7. Wiring topology This section illustrates the recommended wiring topology of each group.

4.7.1. Wiring topology diagram of MCKx_Group

Figure 4-5 Wiring topology diagram of MCKx_Group

DDR3_

SDRAM

For DQ[15:0]

MB86R21

DDR3_

SDRAM

For DQ[31:16]

15.5mm~17.0mm

Under 3.6mm

39Ω

20.6mm~22.7mm RON: 40[Ω]

- In wiring, the L1/L8 layer is assumption.

- Wire length doesn't contain the length of the via.

- The difference in wire length between the positive line and the

negative line of the differential signal shall be under 0.1mm.

- The values of the wire length described in this diagram are the

reference values that we confirmed the waveform quality and timing.

If you change these values, you must perform the transmission line

analysis, and confirm the waveform quality and timing.

39Ω

Under 0.6mm

GND

0.1μF

Under 0.6mm

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4.7.2. Wiring topology diagram of MCMDx_Group and MCNTLx_Group

Figure 4-6 Wiring topology diagram of MCMDx_Group and MCNTLx_Group

DDR3_

SDRAM

For DQ[15:0]

MB86R21

DDR3_

SDRAM

For DQ[31:16]

Under 0.6mm

25.1mm~45.8mm

39Ω

RON: 60[Ω]

15.4mm~17.7mm

Under 15.1mm

- In wiring, the L1/L3/L6/L8 layer is assumption.


- The values of the wire length described in this diagram are the

reference values that we confirmed the waveform quality and timing.

If you change these values, you must perform the transmission line

analysis, and confirm the waveform quality and timing.

Under 0.6mm

VTT=DDRVDE/2

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4.7.3. Wiring topology diagram of MDQSx_Group

Figure 4-7 Wiring topology diagram of MDQSx_Group

DDR3_

SDRAM

MB86R21

RON: 48[Ω]

ODT: 40[Ω]

Driver strength: 34[Ω]

ODT: 60[Ω]

20.3~23.1mm



- The difference in wire length between the positive line and the negative line of

the differential signal shall be under 0.1mm.

- The values of the wire length described in this diagram are the reference

values that we confirmed the waveform quality and timing.

If you change these values, you must perform the transmission line analysis,

and confirm the waveform quality and timing.

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4.7.4. Wiring topology diagram of MDQx_Group

Figure4-8 Wiring topology diagram of MDQx_Group

Refer to Table 4-4 for the wire length of each DQ signal.

DDR3_

SDRAM

MB86R21

RON: 48[Ω]

ODT: 40[Ω] Driver strength: 34[Ω]

ODT: 60[Ω]



- The values of the wire length described in this diagram are the reference values

that we confirmed the waveform quality and timing.

If you change these values, you must perform the transmission line analysis,

and confirm the waveform quality and timing.

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Table 4-4 Wire length of each DQ signal Signal name Length of DQ wiring [mm] Signal

name Length of DQ wiring [mm]

MDM0_0 Wire length of MDQS0_0_Group (Average value): +4.3±2 MDM0_1 Wire length of MDQS0_1_Group (Average value): +1.1±2

MDQ0_0 Wire length of MDQS0_0_Group (Average value): +4.9±2 MDQ0_1 Wire length of MDQS0_1_Group (Average value): +4.6±2



































Note 1) The DQ signal can be shuffled in byte. Refer to "6.1. Shuffle on PCB of DQ wiring" for details.

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5. Power system design restrictions This chapter describes the power system design restrictions for the DDR3 interface part of MB86R21.

5.1. Number and capacity of bypass capacitor Table 5-1 shows recommended number of bypass capacitors for the high frequency noise removal for which mounting is necessary directly under MB86R21.

Table 5-1 Recommended number of bypass capacitors

Pin name of MB86R21

Power supply voltage

Recommended number of bypass capacitors Remarks

0.1µF DDRVDE 1.5V Over 20 For DDR3 interface

VSS 0V -

• If capacity is a value close to 0.1µF (0.22µF etc. for instance), the bypass capacitor can be used. • Place the 0.1µF capacitor as close as possible to the power/GND pins of MB86R21 (refer to "5.2.

Pull-out wiring condition"). • For the 0.1µF capacitor, we recommend the use of ceramic capacitors of under size 1005

(1.0mm × 0.5mm). In addition, use low ESL (Equivalent Series Inductance) value components where possible in order to decrease noise.

• Mount a high-capacity capacitor for the low frequency if needed. One 100µF is recommended to be used for the current variation of 1A only as a guide.

• Verify your board design by simulations and measurements if you can not mount capacitors of the above number.

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5.2. Pull-out wiring condition This section shows the example of mounting the bypass capacitor for the high frequency noise removal. Be sure to meet the following pull-out wiring conditions to reduce the inductance value by wiring and to reduce the noise. If it doesn't meet these conditions, widen the wire width as much as possible, and shorten the wire length. Be sure to mount the bypass capacitor with the Chip on Via method.

Pull-out wiring

Power PAD

GND PAD PAD

PAD PAD

PAD PAD

1mm

GND via

Power via

L1 layer MB86R21 PAD

1mm

L1~Ln layer via

Wire length (L)

PAD

［Pull-out wiring conditions］ Wire width (W): over 0.3mm Wire length (L): under 0.71mm * Average value of all pull-out witing

L1 layer pull-out wiring

Pull-out wiring

PAD

Bypass capacitor PAD

Bypass capacitor (mounted on

Ln layer)

Figure 5-1 Example of mounting a bypass capacitor

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5.3. VREF pin connection The example of the circuit to be connected to VREF pin is shown below.

VREF pin

GND

VDE15

R1

R2 C3 C2

C1

[Recommended value]C1, C2, C3: 0.1µFR1, R2: 100~10kΩ

C3

VREF

Notes: • VREF wiring should be as shorter as possible.

If its length is over 10mm, mount bypass capacitor (C3) at 10mm intervals. • Via for bypass capacitor (C1) must not be common with R1 and R2 vias. • Mount the bypass capacitor (C2) immediately under the LSI pin (about 2mm below.) • Place the bypass capacitor (C2 and C3) for VREF between VREF and GND

(do not set it between power supplies.) • Although supply voltage of both VREF and VTT is 0.75V, VTT's voltage variation during

operation is larger since it is termination voltage of the bus wiring. Therefore, VTT should be generated with other power drivers. Do not connect VTT with VREF.

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5.4. VTT power supply design Place the bypass capacitors of an enough number in the close vicinity of the VTT resistance so that VTT is supplied in low impedance.

Notes: • The above diagram is one example. • Although supply voltage of both VREF and VTT is 0.75V, VTT's voltage variation during

operation is larger since it is termination voltage of the bus wiring. Therefore, VTT should be generated with dedicated power drivers. Do not connect VTT with VREF.

• Place Decoupling Capacitor (0.1µF) in the close vicinity of the termination resistors. As rough indication, the number of placement of capacitors is one per two termination resistors. Review this numerical value appropriately according to the operating frequency, the driver impedance, and the termination resistor value.

• Besides the above Decoupling Capacitor, place Bulk Capacitor (several tens or hundreds µF)

[Example] VTT

0.1uF

0.1uF

0.1uF

TerminationResistors

Command/Control/AddressSignals

数数 ~数数 uFSeveral tens or hundreds µF

0.1µF

0.1µF

0.1µF

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5.5. ZQRES pin connection Connect the MZQRES_0/MZQRES_1 pin of MB86R21 and the ZQ pin of each DRAM to GND respectively through 240Ω resistance. Place 240Ω resistance near each pin.

MZQRES_x

GND

240Ω

ZQ

GND

240Ω

※DRAM側ZQ抵抗の接続については、使用するDRAMのData Sheetで確認してください。

* Confirm the connection of the ZQ resistance on DRAM side with the data sheet of DRAM to use.

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6. Appendix

6.1. Shuffle on PCB of DQ wiring

Table 6-1 Connection example of the DQ signal between MB86R21 and DRAM MDQ0_0_Group MDQ1_0_Group MDQ2_0_Group MDQ3_0_Group

MB86R21 ball DRAM0 ball MB86R21 ball DRAM0 ball MB86R21 ball DRAM1 ball MB86R21 ball DRAM1 ball

MDQ0_0 DQL7 MDQ8_0 DQU1 MDQ16_0 DQL3 MDQ24_0 DQU7








In consideration of the routability, the DQ signal in same BYTE can be shuffled to each other, and be connected.

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6.2. RESET# signal connection When you design "Wire length", "Wiring route", "Wiring gap", and "Topology" for RESET# signals (MXRESET_0/MXRESET_1), consult the description page of restrictions of MCMDx/MCNTLx_Group. (See "4.7.2.") However, strictly observing these restrictions for the wire length is not necessary. Unlike the other signals, RESET# signals are CMOS interfaces. Do not connect the termination resistor. The diagrammatic illustration is shown below.

DDR3_

SDRAM

For DQ[15:0]

MB86R21

DDR3_

SDRAM

For DQ[31:16]

Under 0.6mm

25.1mm~45.8mm

15.4mm~17.7mm

- In wiring, the L1/L3/L6/L8 layer is assumption.


- The values of the wire length described in this diagram are the reference values.

Under 0.6mm

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mb86r21 application note ddr3 interface pcb design guideline€¦ · 3 mb86r21 application note...

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