max13253 - 1a, spread-spectrum, push-pull, transformer driver for isolated power … ·...

General DescriptionThe MAX13253 is a 1A, push-pull, transformer driver designed to provide a simple solution for low-EMI isolated power supplies. The MAX13253 has an internal oscillator and operates from a single +3.0V to +5.5V supply. The transformer’s secondary-to-primary winding ratio defines the output voltage, allowing selection of virtually any isolated output voltage with galvanic isolation.The MAX13253 features an integrated oscillator driving a pair of n-channel power switches. The driver includes pin-selectable spread-spectrum oscillation and a well-controlled slew rate to reduce EMI. The MAX13253 can optionally be driven by an external clock to further manage EMI. Internal circuitry guarantees a fixed 50% duty cycle to prevent DC current flow through the transformer, regardless of which clock source is used.The MAX13253 operates with up to 1A of continuous current and features integrated protection including fault detection, overcurrent protection, and thermal shutdown.The MAX13253 includes a low-current shutdown mode to reduce the overall supply current to less than 5µA (max) when the driver is disabled.The MAX13253 is available in a small 10-pin (3mm x 3mm) TDFN package and is specified over the -40°C to +125°C temperature range.

Features and Benefits Simple, Flexible Design

• +3.0V to +5.5V Supply Range• Low RON 300mΩ (max) at 4.5V• Up to 90% Efficiency• Provides Up to 1A to the Transformer• Internal or External Clock Source • Internal Oscillator Frequency: 250kHz or 600kHz• Optional Spread-Spectrum Oscillation • -40ºC to +125ºC Temperature Range

Integrated System Protection• Fault Detection and Indication• Overcurrent Limiting• Undervoltage Lockout• Thermal Shutdown

Saves Space on Board • Small 10-Pin TDFN Package (3mm x 3mm)

Applications Power Meter Data Interface Isolated Fieldbus Interface Medical Equipment Isolated Analog Front-End Isolated USB Power

19-6600; Rev 2; 9/18

Ordering Information appears at end of data sheet.

FAULT

1µF

1µF

10µF

5V

VDD

EN

CLK

SPRDHICLK

T1

GND PGND

T2

ISOLATEDVOUT

1CT:1.3CT

MAX13253

MAX13253 1A, Spread-Spectrum, Push-Pull, Transformer Driver for Isolated Power Supplies

Typical Operating Circuit

EVALUATION KIT AVAILABLE

Click here for production status of specific part numbers.

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(All voltages referenced to GND.)VDD, FAULT, CLK, HICLK, SPRD, EN....................-0.3V to +6V T1, T2 .................................................................-0.3V to +16.5VT1, T2 Maximum Continuous Current ..............................+1.75AFAULT Maximum Continuous Current .............................+50mAContinuous Power Dissipation (TA = +70ºC) TDFN (Multilayer Board)

(derate 24.4mW/ºC above +70ºC) ..........................1951.2mW

TDFN (Single-Layer Board) (derate 18.5mW/ºC above +70ºC) ..........................1481.5mW

Operating Temperature Range ..........................-40ºC to +125ºCJunction Temperature ...................................................... +150ºCStorage Temperature Range .............................-65ºC to +150°CLead Temperature (soldering, 10s) .................................+300°CSoldering Temperature (reflow) .......................................+260°C

(VDD = +3.0V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5.0V and TA = +25ºC.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC CHARACTERISTICS

Supply Voltage Range VDD 3.0 5.5 V

Supply Current IDDVEN = 0V, VCLK = 0V, VSPRD = 0V, T1 and T2 not connected

VHICLK = 0V 1.1 1.8mA

VHICLK = VDD 2.1 3.5

Disable Supply Current IDISVEN = VDD, T1, T2, CLK, SPRD, HICLK connected to GND or VDD (Note 2) 5 µA

Driver Output Resistance RO IOUT = 500mAVDD = 3.0V 160 350

mΩVDD = 4.5V 145 300

PACKAGE TYPE: 10 TDFNPackage Code T1033+1Outline Number 21-0137Land Pattern Number 90-0003THERMAL RESISTANCE, SINGLE-LAYER BOARDJunction to Ambient (θJA) 54°C/WJunction to Case (θJC) 9°C/WTHERMAL RESISTANCE, MULTILAYER BOARDJunction to Ambient (θJA) 41°C/WJunction to Case (θJC) 9°C/W


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Electrical Characteristics

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings

Package Information

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

http://pdfserv.maximintegrated.com/package_dwgs/21-0137.PDF

http://pdfserv.maximintegrated.com/land_patterns/90-0003.PDF

(VDD = +3.0V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5.0V and TA = +25ºC.) (Note 1)

Note 1: All units are 100% production tested at TA = +25ºC. Specifications over temperature are guaranteed by design.Note 2: Disable supply current includes output switch-leakage currents.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Undervoltage Lockout Threshold VUVLO VDD rising 2.6 2.75 2.9 V

Undervoltage Lockout Threshold Hysteresis VUVLO_HYST 250 mV

T1, T2 Current Limit ILIM3.0V < VDD < 3.6V 1.1 1.3 1.5

A4.5V < VDD < 5.5V 1.2 1.4 1.6

T1, T2 Leakage Current ILKG VEN = VDD, VCLK = 0V; T1, T2 = 0V or VDD -1 +1 µA

LOGIC SIGNALS (CLK, EN, HICLK, SPRD, FAULT)

Input Logic-High Voltage VIH 2 V

Input Logic-Low Voltage VIL 0.8 V

Input Leakage Current IIL EN, CLK, SPRD, HICLK = 0V or 5.5V -1 +1 µA

SPRD Pulldown Current IPD VSPRD = VDD 5 10 20 µA

FAULT Output Logic-Low Voltage VOL ISINK = 10mA 0.4 V

FAULT Leakage Current ILKGF VFAULT = 5.5V, FAULT deasserted 1 µA

AC CHARACTERISTICS

Switching Frequency fSWFigure 2, VCLK = 0V, VSPRD = 0V

VHICLK = 0V 237 250 263kHz

VHICLK = VDD 564 600 636

Frequency Spread DfSW Figure 1, VSPRD = VDD ±4 %

Spread Modulation Rate fMOD Figure 1, VSPRD = VDDVHICLK = 0V fSW/12

kHzVHICLK = VDD fSW/28

CLK Input Frequency fEXT 200 2000 kHz

CLK to T1, T2 Propagation Delay tPD T1/T2 switching low 230 ns

T1, T2 Duty Cycle D Internal or external clocking 50 %

T1, T2 Slew Rate tSLEW Figure 2 200 V/µs

Crossover Dead Time tDEAD Figure 2 50 ns

Watchdog Timeout tWDOG 20 35 55 µs

PROTECTION

Thermal-Shutdown Threshold TSHDN +160 ºC

Thermal-Shutdown Hysteresis TSHDN_HYS 30 ºC



Electrical Characteristics (continued)

Figure 1. Frequency Spread Timing Diagram

Figure 2. T1, T2 Timing Diagram

IF SPRD = GND(DITHER AMOUNT = 0%)

TIME

8% DITHERAMOUNT

+4% of fSW

-4% of fSW

fSW

1fMOD

50pF

100I

VDD

T1, T2

2 x VDD

T1

0V

0V

2 x VDD

T2

tDEADtDEAD



(VDD = +5V, TA = +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. EXTERNAL CLOCK FREQUENCY

MAX

1325

3 to

c01

EXTERNAL CLOCK FREQUENCY (MHz)

SUPP

LY C

URRE

NT (m

A)

1.81.60.4 0.6 0.8 1.21.0 1.4

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

00.2 2.0

SWITCHING FREQUENCY vs. TEMPERATURE

MAX

1325

3 to

c02

TEMPERATURE (°C)

SWIT

CHIN

G FR

EQUE

NCY

(kHz

)

1058030 555-20

260

310

360

410

460

510

560

610

660

210-45 130

HICLK = VDD

HICLK = GND

CLK = GNDSPRD = GND

CURRENT LIMITvs. TEMPERATURE

MAX

1325

3 to

c03

TEMPERATURE (°C)

CURR

ENT

LIMIT

(A)

1058055305-20

1.1

1.2

1.3

1.4

1.5

1.6

1.0-45 130

VDD = 5V

VDD = 3.3V

T1/T2 OUTPUT VOLTAGE LOWvs. OUTPUT CURRENT

MAX

1325

3 to

c04

OUTPUT CURRENT (A)

T1/T

2 OUT

PUT

VOLT

AGE

LOW

(V)

0.80.60.40.2

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

0.18

0.20

00 1.0

VDD = 5V

VDD = 3.3V

FAULT OUTPUT VOLTAGE LOWvs. SINK CURRENT

MAX

1325

3 to

c05

SINK CURRENT (mA)302010

20

40

60

80

100

120

140

160

180

200

00 40

FAULT IS ASSERTED

FAUL

T OU

TPUT

VOL

TAGE

LOW

(mV)

ISOLATED OUTPUT VOLTAGEvs. LOAD CURRENT (5V to 5V)

MAX

1325

3 to

c06

LOAD CURRENT (A)

ISOL

ATED

OUT

PUT

VOLT

AGE

(V)

0.60.40.2

1

2

3

4

5

6

7

8

9

10

00 0.8

CLK = GNDHICLK = GNDSPRD = GND1:1:1.3:1.3 HALO TGM-H240V8LFTRANSFORMER

ISOLATED OUTPUT VOLTAGEvs. LOAD CURRENT (3.3V to 5V)

MAX

1325

3 to

c07

LOAD CURRENT (A)

ISOL

ATED

OUT

PUT

VOLT

AGE

(V)

0.50.40.30.20.1

123456789

101112

00 0.6

VDD = 3.3VCLK = GNDHICLK = GNDSPRD = GND1:1:2:2HALO TGM-H260V8LFTRANSFORMER


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Typical Operating Characteristics

(VDD = +5V, TA = +25°C, unless otherwise noted.)

MAX

1325

3 to

c10

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

0.70.60.50.40.30.20.1

75

80

85

90

95

700 0.8


VDD = 4.5V

VDD = 5V

VDD = 5.5V

EFFICIENCY vs. LOAD CURRENT(5V to 5V)


MAX

1325

3 to

c08

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

0.80.70.60.50.40.30.20.1

80

82

84

86

88

90

780 0.9


TA = +25°C

TA = +125°C

TA = +85°C

TA = -40°CM

AX13

253

toc1

1

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

0.50.40.30.20.1

75

80

85

90

95

700 0.6

VDD = 3.3VCLK = GNDHICLK = GNDSPRD = GND1:1:2:2 HALO TGM-H260V8LFTRANSFORMER

TA = +125°C

TA = +85°C

TA = +25°C

TA = -40°C

EFFICIENCY vs. LOAD CURRENT(3.3V to 5V)

MAX

1325

3 to

c09

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

75

80

85

90

95

700.90.80.70.60.50.40.30.20.10

HICLK = GND

HICLK = VDD

CLK = GNDSPRD = GND1:1:1.3:1.3 HALO TGM-H240V8LFTRANSFORMER


MAX

1325

3 to

c12

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

0.60.50.40.30.20.1

70

75

80

85

90

95

650 0.7

VDD = 3.3VCLK = GNDSPRD = GND1:1:2:2 HALO TGM-H260V8LFTRANSFORMER

HICLK = VDD

HICLK = GND

EFFICIENCY vs. LOAD CURRENT(3.3V to 5V)

MAX

1325

3 to

c13

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

0.60.50.40.30.20.1

70

75

80

85

90

95

650 0.7

VDD = 3.3VCLK = GNDHICLK = GNDSPRD = GND1:1:2:2 HALO TGM-H260V8LFTRANSFORMER

VDD = 3.0V

VDD = 3.3V

VDD = 3.6V

EFFICIENCY vs. LOAD CURRENT(3.3V to 5V) SWITCHING WAVEFORMS

MAX13253 toc14

T15V/div

T25V/div

0V

0V

1µs/div

CLK = GNDHICLK = GND

SPRD = GNDRLOAD = 1kΩ


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Typical Operating Characteristics (continued)

PIN NAME FUNCTION

1 VDD Power-Supply Input. Bypass VDD to GND with a 1µF capacitor as close as possible to the device.

2 CLK Clock Input. Connect CLK to GND to enable internal clocking. Apply a clock signal to CLK to enable external clocking.

3 HICLK Internal Oscillator Frequency Select Input. Drive HICLK high to set the internal oscillator to a 600kHz switching frequency. Drive HICLK low to set the internal oscillator to a 250kHz switching frequency.

4 EN Active-Low Enable Input. Drive EN low to enable the device. Drive EN high to disable the device.

5 SPRDSpread-Spectrum Enable Input. Drive SPRD high to enable ±4% spread spectrum on the internal oscillator. Drive SPRD low or leave it unconnected to disable spread spectrum. SPRD does not have any effect when an external clock is used.

6 FAULT Active-Low Fault Open-Drain Output. The FAULT open-drain transistor turns on when an overcurrent or overtemperature condition occurs.

7 GND Logic and Analog Ground

8 T2 Transformer Drive Output 2

9 PGND Power Ground. The transformer primary current flows through PGND. Ensure a low-resistance connection to ground.

10 T1 Transformer Drive Output 1

— EP Exposed Pad. Internally connected to GND. Connect EP to a large ground plane to maximize thermal performance; not intended as an electrical connection point.

1 3 4

10 8 7

T1 T2 GND

2

9

PGND

5

+

6

FAULT

VDD HICLK ENCLK SPRD

*EP

TDFN

TOP VIEW

*EXPOSED PAD—CONNECT TO GND

MAX13253



Pin Description

Pin Configuration

Detailed DescriptionThe MAX13253 is an integrated primary-side transformer driver for low-EMI isolated power-supply circuits. An on-board oscillator, protection circuitry, and internal MOSFETs provide up to 1A of drive current to the primary windings of a center-tapped transformer. The MAX13253 features an internal oscillator for autonomous operation and an external clock source input to synchronize multiple MAX13253 devices. Regardless of the clock source used, an internal flip-flop stage guarantees a fixed 50% duty cycle to prevent DC current flow in the transformer.The MAX13253 operates from a single +3.0V to +5.5V supply and includes undervoltage lockout for controlled startup. Overcurrent protection and thermal shutdown circuitry provides additional protection against excessive power dissipation.

Isolated Power-Supply ApplicationThe MAX13253 allows a versatile range of secondary-side rectification circuits (see Figure 3). The primary-to-

secondary transformer winding ratio can be chosen to adjust the isolated output voltage. The MAX13253 allows up to 1A of current into the primary transformer winding with a supply voltage up to +5.5V.

Clock SourceEither the internal oscillator or an external clock provides the switching signal for the MAX13253. Connect CLK to ground to select the internal oscillator. Provide an external signal to CLK to automatically select external clocking.

Internal Oscillator ModeThe MAX13253 includes an internal oscillator with a guaranteed 50% duty cycle. Drive the HICLK input high to set the internal oscillator frequency to 600kHz (typ). Drive the HICLK input low to set the internal oscillator frequency to 250kHz (typ).The MAX13253 features spread-spectrum oscillation for reducing EMI peaks. Drive the SPRD input high to enable spread spectrum on the internal oscillator. Drive the

CLK

SPRD

HICLK

VDD

EN

DRIVER

T1

T2

UVLO

MUX FLIP-FLOP

VUVLO

CURRENT LIMIT

OSC

10µA

WATCHDOG

FAULT

GND PGND

MAX13253



Functional Diagram

SPRD input low or leave unconnected to disable spread spectrum on the internal oscillator. SPRD has an internal 10µA pulldown to ground.

External Clock ModeThe MAX13253 provides an external clock mode for synchronizing multiple MAX13253 devices. Apply an external clock source to the CLK input to enable external clock mode. An internal flip-flop divides the external clock by two in order to generate a switching signal with a guaranteed 50% duty cycle. As a result, the MAX13253 outputs switch at one-half of the external clock frequency. T1 and T2 switch on the rising edge of the external clock signal.SPRD has no effect when an external signal is applied to CLK.

WatchdogWhen the MAX13253 is operating in external clock mode, a stalled clock can cause excessive DC current to flow through the primary winding of the transformer. The MAX13253 integrates internal watchdog circuitry to prevent damage from this condition. The internal oscillator

provides the switching signal to the driver whenever the period between edges on CLK exceeds the watchdog timeout period of 20µs (min).

Slew-Rate ControlThe T1 and T2 drivers feature a controlled slew rate to limit EMI.

Disable ModeThe MAX13253 includes a pin-selectable disable mode to reduce current consumption. In disable mode the device consumes less than 5µA (max) of supply current. The T1 and T2 outputs are high impedance in disable mode.

Power-Up and Undervoltage LockoutThe MAX13253 provides an undervoltage lockout feature to ensure controlled power-up state and prevent operation before the oscillator has stabilized. On power-up and during normal operation, if the supply voltage drops below the VUVLO, the undervoltage-lockout circuit forces the device into disable mode. The T1 and T2 outputs are high impedance in disable mode.

Overcurrent LimitingThe MAX13253 features overcurrent limiting to protect the IC from excessive currents when charging large capacitive loads or driving into short circuits. Current limiting is achieved in two stages: internal circuity monitors the output current and detects when the peak current rises above 2A. When the 2A limit is exceeded, internal protection circuitry is immediately enabled, reducing the output current and regulating it to the 1.4A (typ) current-limit threshold. The MAX13253 monitors the driver current on a cycle-by-cycle basis, and the driver output current is regulated to the current-limit threshold until the short is removed.The MAX13253 can dissipate large amounts of power during overcurrent limiting, causing the IC to enter thermal shutdown.

FAULT OutputThe FAULT output is asserted low during an overcurrent or overtemperature fault. FAULT is an open-drain output.Thermal ShutdownThe MAX13253 is protected from overtemperature damage by integrated thermal-shutdown circuitry. When the junction temperature (TJ) exceeds +160ºC (typ), the device is disabled and FAULT is asserted. FAULT is asserted for the duration of either an overcurrent or overtemperature event. The device resumes normal operation when TJ falls below +130°C (typ).

Figure 3. Secondary-Side Rectification Topologies

+VOUT = nVIN - VD

1CT: nCT

VD = DIODE FORWARD VOLTAGE

-

T1

T2

T1

T2

T1

T2

VIN

(A) PUSH-PULL RECTIFICATION

+

VOUT = 2(nVIN - VD)

1CT: nCT

VD = DIODE FORWARD VOLTAGE

-

VIN

(B) VOLTAGE DOUBLER

+

VOUT = nVIN - 2VD

1CT: nCT

VD = DIODE FORWARD VOLTAGE-

VIN

(C) FULL-WAVE RECTIFIER



Applications InformationPower DissipationThe power dissipation of the device is approximated by:

PD = (RO x IPRI2) + (IDD x VDD)where RO is the resistance of the internal FET drivers and IPRI is the load current flowing into T1 and T2. Ensure that the power dissipation of the MAX13253 is kept below the Absolute Maximum Ratings for proper operation.

High-Temperature OperationWhen the MAX13253 is operated under high ambient temperatures, the power dissipated in the package can raise the junction temperature close to the thermal shutdown threshold. Under such temperature conditions, the power dissipation should be held low enough that the junction temperature observes a factor of safety margin. The maximum junction temperature should be held below +140°C. Use the package’s thermal resistance to calculate the junction temperature.

Power-Supply DecouplingBypass VDD to ground with a 1µF ceramic capacitor as close as possible to the device.Connect at least 10µF between VDD and ground as close as possible to the primary-side center tap of the transformer. This capacitor helps to stabilize the voltage on the supply line and protects the IC against large voltage spikes on VDD.

Output Voltage RegulationFor many applications, the unregulated output of the MAX13253 circuit meets output voltage tolerances. This configuration represents the highest efficiency possible. When the load currents on the transformer’s secondary side are low, the output voltage of the rectifier can strongly increase. To protect downstream circuitry, limit the output voltage when operating the circuit under low load conditions. If the minimum output load current is less than approximately 5mA, connect a zener diode from the output node of the rectifier to ground to limit the output voltage to a safe value. For applications requiring a regulated output voltage, Maxim provides several solutions. In the following examples, assume a tolerance of ±10% for the input voltage.

Example 1: 5V to Isolated, Unregulated 6VIn the circuit of Figure 4, the MAX13253 is used to generate an isolated 6V output. For a minimum input voltage of 5V, the output voltage of the rectifier is approximately 6V.

Example 2: 3.3V to Isolated, Regulated 5VIn the circuit of Figure 5, the MAX8881 low-dropout linear regulator regulates the isolated output voltage to 5V. A 1:2 center-tapped transformer is used to step-up the secondary side voltage from a 3.3V input. For a minimum input voltage of 3.3V, the output voltage of the rectifier is approximately 5V.

Figure 4. 5V to Isolated, Unregulated 6V Application Circuit

FAULT

1µF

1µF

10µF

5V

VDD

EN

CLK

SPRDHICLK

T1

GND PGND

T2

5VISO OUTPUT

1CT:1.3CT

MAX13253



Isolated USB/RS-485/RS-232 Isolated ApplicationsThe MAX13253 can provide isolated power for USB/RS-485/RS-232 applications. The 1A output current capability of the MAX13253 allows multiple RS-485/RS-232 transceivers to operate simultaneously.

PCB Layout GuidelinesAs with all power-supply circuits, careful PCB layout is important to achieve low switching losses and stable operation. Connect the exposed pad to a solid copper ground plane for optimum thermal performance.The traces from T1 and T2 to the transformer must be low-resistance and low-inductance paths. Locate the transformer as closely as possible to the MAX13253 using short, wide traces.If possible, use a power plane for all VDD connections to the MAX13253 and the primary-side of the transformer. If a power plane is not available, avoid damage to the IC by ensuring that the current flowing through the primary-side center tap of the transformer does not flow through the same trace that connects the supply pin of the MAX13253 to the VDD source, and connect the primary-side center tap to the VDD supply using a very low-inductance connection.When the internal oscillator is used, it is possible for high frequency switching on T1 and T2 to couple into the CLK circuitry through PCB parasitic capacitance. This capacitive coupling can induce duty cycle errors in the oscillator, resulting in a DC current through the transformer. For proper operation, ensure that CLK has a solid ground connection.

Exposed PadFor optimal thermal performance, ensure that the exposed pad has a low thermal resistance connection to the ground plane. Failure to provide a low thermal impedance path to the ground plane results in excessive junction temperatures when dissipating high power.

Component SelectionTransformer SelectionTransformer selection for the MAX13253 can be simplified by the use of the ET product. The ET product relates the maximum allowable magnetic flux density in a transformer core to the voltage across a winding and switching period. Inductor magnetizing current in the primary winding changes linearly with time during the switching period of the MAX13253. Each transformer has a minimum ET product, though not always stated on the transformer data sheet. Ensure that the transformer selected for use with the MAX13253 has an ET product of at least ET = VDD/(2 x fSW) for each half of the primary winding, where fSW is the minimum switching frequency of the T1 and T2 ouputs. Select a transformer with sufficient ET product for each half of the primary winding to ensure that the transformer does not saturate during operation. Saturation of the magnetic core results in significantly reduced inductance of the primary, and therefore in a large increase in current flow. This can cause the current limit to be reached even when the load is not high.

Figure 5. 3.3V to Isolated, Regulated 5V Application Circuit

FAULT SHDN

IN

1µF

1µF

10µF

3.3V

VDD

4.7µF

5VISO OUTPUT

EN

CLK

SPRDHICLK

T1GND

GND

OUT

PGND

T2 1CT:2CT

MAX13253MAX8881

FB



For example, when the internal oscillator is used to drive the outputs and HICLK is low, the required transformer ET product to the center tap for an application with VDD (max) = 5.5V, is 13.1V-µs. An application with VDD (max) = 3.3V has a transformer ET product to the center tap requirement of 7.9V-µs.In addition to the constraint on ET product, choose a transformer with low leakage inductance and low DC-winding resistance. Power dissipation of the transformer due to the copper loss is approximated as:

PD_TX = ILOAD2 x (RPRI/N2 + RSEC)

where RPRI is the DC winding resistance of the primary, and RSEC is the DC winding resistance of the secondary. In most cases, an optimum is reached when RSEC = RPRI/N2. For this condition, the power dissipation is equal for the primary and secondary windings. As with all power-supply designs, it is important to optimize efficiency. In designs incorporating small transformers, the possibility of thermal runaway makes low transformer efficiencies problematic. Transformer losses produce a temperature rise that reduces the efficiency of the transformer. The lower efficiency, in turn, produces an even larger temperature rise. To ensure that the transformer meets these requirements under all operating conditions, the design should focus on the worst-case conditions. The most stringent demands on ET product arise for maximum input voltage, minimum switching frequency, and maximum temperature and load current. Additionally, the worst-case values for transformer and rectifier losses should be considered.

The primary must be center-tapped; however the secondary winding may or may not be center-tapped, depending on the rectifier topology used. The phasing between primary and secondary windings is not critical. The transformer turns ratio must be set to provide the minimum required output voltage at the maximum anticipated load with the minimum expected input voltage. In addition, include in the calculations an allowance for the worst-case losses in the rectifiers. Since the turns ratio determined in this manner will ordinarily produce a much higher voltage at the secondary under conditions of high input voltage and/or light loading, be careful to prevent an overvoltage condition from occurring.Transformers for use with the MAX13253 are typically wound on a high-permeability magnetic core. To minimize radiated electromagnetic emissions, select a toroid, pot core, E/I/U core, or equivalent.

Diode SelectionThe high switching speed capability of the MAX13253 necessitates high-speed rectifiers. Ordinary silicon signal diodes such as the 1N914 or 1N4148 can be used for low-output current levels (less than 50mA), but at high output current levels, their reverse recovery times might degrade efficiency. At higher output currents, select low forward-voltage Schottky diodes to improve efficiency. Ensure that the average forward current rating for the rectifier diodes exceeds the maximum load current of the circuit. For surface-mount applications, Schottky diodes such as the B230A, MBRS230, and MBRS320 are recommended.

Table 1. Component ManufacturersMANUFACTURER COMPONENT WEBSITE

Halo Electronics Transformers www.haloelectronics.comWurth Electronics Transformers www.we-online.comDiodes Inc. Diodes www.diodes.comMurata Americas Capacitors www.murataamericas.com



Suggested External Component Manufacturers

http://www.haloelectronics.com

http://www.we-online.com

http://www.diodes.com

http://www.murataamericas.com

+Denotes lead(Pb)-free/RoHS-compliant package.*EP = Exposed Pad

PART TEMP RANGE PIN-PACKAGEMAX13253ATB+ -40°C to +125°C 10 TDFN-EP*



Ordering Information

Chip InformationPROCESS: BiCMOS

REVISIONNUMBER

REVISIONDATE DESCRIPTION PAGES

CHANGED0 3/13 Initial release —

1 4/13 Updated TOC parameters, updated Figure 4, replaced Figure 5, updated the Output Voltage Regulation section 5, 6, 10, 11

2 9/18 Updated TOC06–TOC13, and updated Table 1 5, 6, 12

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.


© 2018 Maxim Integrated Products, Inc. 14

Revision History

For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.

https://www.maximintegrated.com/en/storefront/storefront.html

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