managing ip subsystems at the system level
DESCRIPTION
Semico Research estimates that over 50 IP cores are present on average in SoCs being developed today. As a result, more SoCs contain distributed computing, multicore architectures. These topologies are making it increasingly difficult to manage power, security, error-recovery and even boot sequencing. No one IP core can easily be given enough accessibility and control to manage the other cores without complicating the architecture. And with many software operating systems and applications on the single SoC, synchronizing their states with their support hardware is also becoming complex. Solutions designed in-house often result in adding some combination of extra logic and additional software development to manage the system tasks. These solutions are often designed and tested specifically for the SoC configuration. As complexities grow, significant cost and verification risks are now escalating from the need to redesign and re-verify these solutions for each new chip development project. SSM represents a unique “subsystem” alternative which decouples the system management from the specific design, promoting high reuse and faster hardware-software integration. SSM creates virtualization in the SoC architecture. Hardware level virtualization comes from SSM’s ability to operate as a self contained unit independent from the other SoC components. SSM connects to the other IP cores using a simple hardware bus scheme. SSM utilizes commands sent to it by any source to execute the necessary signal level transitions that change an IP cores’ operation state. Software virtualization comes from SSMs ability to synchronize software and hardware states as it is performing the hardware level tasks. SSM provides API’s and a kernel which is hosted on SSMs hardware core. Drivers are connected to other software on the SoC, which communicates the status of the hardware state changes. SSM can also take command directives directly from the software through the drivers. Says Rich Wawryzniak, Senior Analyst, Semico Research, “Virtualizing system management using a subsystem approach creates real economies when measuring the development costs for complex SoCs. Since these costs are multiplying from both hardware and software complexity growth, the need for modular SoC architectures that effects both hardware and software development dictates the need for these subsystems.”TRANSCRIPT
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SoC System Manager (SSM)
Co-Developed By:
The Industry’s First SoC IP Subsystem Dedicated
To System Resource Management
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SoC Complexity Accelerating
Volume Consumer Markets
Driving the Trend
"Average" Number of IP Blocks on SoCs Today
0
10
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30
40
50
60
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100
1998
1999
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2009*
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2013*
Av
g.
Nu
mb
er
of
SIP
Blo
cks
Avg. Number of CPU / DSP / Controllers Avg. Number of 'Other' SIP Blocks
Avg. Number of Embedded Memory Blocks Total SIP Blocks
Source: Semico Research
Over 50 IP Blocks!
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The Resource Management Challenge
Global Interconnect
Host
Subsystem
Multimedia
Subsystem
Memory
Subsystem
I/O
Subsystem
Comm
Subsystem
How Will the System Be Managed?
Lack of direct hardware
connectivity & complex
interconnect arbitration
complicates ability for host
to manage system state
changes and maintain H/W-
S/W synchronization during
operation and error recovery
Host Visibility and Control Inadequate to Optimize System ManagementVirtualization Based on Control Plane a More Effective Architecture
System
Manager
Subsystem
Subsystem manager
allows SoC architecture to
use a control plane
framework that provides
independent top down
system management with
H/W-S/W synchronization
during operation and error
recovery
SSM
H/W
CPU DSP
CPU I/OMEM
CTL
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Introducing SSM:
System Resource Management IP
Hardware/Software
IP “block”
• Power and Security Management
• Error Recovery
• Boot and Reset Sequencing
SSM Connects Directly to Hardware AND
Synchronizes with Software via Drivers
SSM Consolidates and Virtualizes these System Management Services:
SSM
CTL
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SSM Advantages
Lowers development costs and risks
Design and verify at architecture stage
Pre-verify system management policies and reuse
Increases the value of the SoC deliverable
Improves software-system management control
Mitigates hardware-software dependencies
Creates new opportunities to innovate
New power management schemes made possible
Increasing integration complexities manageable
Shift System Management Out of the Design
and into the Architecture
The “Ripple Savings” Effect
Architecture Top down system management provides high reuse framework for streamlining
product line management.
Design Pre-defined topology eliminates creating ad hoc solutions during the design process.
Verification Test schemes predesigned during architecture development accelerates starting
point for verification script generation.
Software Development Shift to architecture significantly reduces burden to create similar solutions and
provides more chip behavior predictability before chip design commences.
Bring Up and Test Provides unique post silicon control of IP cores for checkout and functional
verification. Scripts also a way to implement potential work-arounds.
Production Engineering Consistent testing methodology throughout all phases of the development cycle
yields a comprehensive suite of testing sequences that are also easily modified.
Savings Multiply During Development
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100 200 300 400 500 600 700 800 900
LABOR (PERSON - MONTHS)
CA
PIT
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(M
$ U
SD
)
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Before SSM
After SSM
Advance Tech Marketing
Production Curves
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100 200 300 400 500 600 700 800 900
LABOR (PERSON - MONTHS)
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100 200 300 400 500 600 700 800 900
LABOR (PERSON - MONTHS)
A
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Before SSM
After SSM
Advance Tech Marketing
Production Curves
Quantifying the Aggregate Savings
Possible Project Savings
33% Capital Reduction AND
10% Labor Reduction
OR
42% Labor Reduction for
Same Capital Investment
Reference: Semico Research SoC Reports
(Assumes $3.25M USD, 300 P-M Project Cost Before SSM)
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SSM Use Models
SSM Use Models
SSM facilitates the management of system resources such
as power management, security, error recover, and boot
and reset sequencing
Control of these system resources, and the ability to
communicate directly with software, makes SSM an
excellent resource for many different uses: Hardware Development
○ Architecture Enhancement
Top down system management provides high reuse framework for streamlining system
resource management across product lines
○ Design Acceleration
Pre-defined topology within the architecture eliminates creating ad hoc solutions during the
design process.
○ Verification
Test schemes predesigned during architecture development can be used to accelerate the
starting point for verification test generation.
SSM Use Models… continued
Software Development
Shift to architecture significantly reduces burden to create similar system
management solutions in software and creates clear methodology for maintaining
synchronization between software and underlying IP hardware during operation
Bring Up and Test
Provides unique post silicon control of IP cores for debugging. Scripts also a way to
implement potential work-arounds to problems associated with IP block state
changes.
Production Engineering Testing
Consistent testing methodology throughout all phases of the development cycle yields
a comprehensive suite of testing sequences that are also easily modified.
Remote Diagnostics and Updating
SSM can deliver IP block state data to a remote host using a communications link or
a JTAG port for debugging and monitoring functions.
SSM can be used to coordinate firmware and software updates remotely through the
use of its communications bus and connectivity to the IP blocks.
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SSM Technical Overview
SSM
H/W
CPU DSP
CPU I/OMEM
CTL
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SSM Hardware Connectivity
• SSM H/W block contains processor which executes commands
• An SSM block is connected to each IP block to be managed
• SSM executes requests through SSM registers/bus
• Message passing option which is user defined
SSM register
blocks and
control bus
SSM
CTL
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SSM Connects to Software via Drivers
Application Software
SoC Hardware
SSM Software
SSM Hardware
O/S
API
•Applications or O/S Communicates
with SSM via API’s and Drivers
•SSM Software Translates SSM
Commands to Signals
•SSM Hardware Executes State
Transitions
Conditional or Unconditional Command Execution
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“Top Down” Power Management
SSM
H/W
CPU DSP
CPU I/OMEM
CTL
HOST
Simple IPTV Example
SSM Scripts
Power Sequencing
Managed by SSM
Software Synchronization
Managed by SSM
OFF
ON
OFF
IP
Packets
Accept IPTV Packets
OFF
ON ON
Macroblocks
Accept IPTV Packets
Process Macroblocks
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SSM Facilitates Policies
Policies (chains of commands) accepted from any
source are loaded into local RAM
Executes policy enforcement in any desired pattern
(called scripting)
Guaranteed conditional or unconditional
enforcement sequencing
Hardware uses message passing for IP block to block
communication
Software uses drivers
Sequences of Commands Are Predetermined
and Tested For Any Number of Scenarios
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Virtualizing System Management
Typical Multicore Host Reset Script
Suspend DSP; Send message to DSP O/S on DSP, Wait for ACK, toggle IP core
enable signal inactive
Suspend MPE; Same as above
Reset Host; Send message to host O/S, wait for ACK, toggle reset
Resume DSP; Activate enable signal, send message to DSP O/S
Resume MPE; Same as above
Software Scripts are Developed
Independent of Hardware Development
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SSM Advantages
Simplifies accessibility and control of all managed IP blocks
Guaranteed synchronization between hardware and
software while executing complex sequences
Virtualization of system management functions
Compartmentalizes instantiation dependencies
Improves software’s ability to control hardware
Saves Time and Money
Offers SoC Architecture Consistency
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SSM Subsystem Components
Hardware (Soft IP)
SSM Controller
SSM Register bus connection
Software
SSM software
API
Drivers
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SSM Addresses Key System Issues
Standardizes Management of Key System Functions
Power, security, error recovery, boot sequencing
Eases Hardware Software Integration
Provides A Reusable Architecture Across Many SoCs
A Subsystem Suited for Universal Adoption
About ChipStart
ChipStart is the only, full-function
semiconductor IP solution alternative
IP Subsystem Solutions oriented
Experienced team (+250 years in IP)
Delivering value with integration
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