Peter Miller (London School of Economics and Political Science) Jodie Moll (University of Manchester)Ted O’Leary (University of Manchester)

Managing inter-firm interdependencies in R&D investmentInsights from the semiconductor industry

Volume 8 | Issue 3

Key conclusions

• Investment in R&D often takes the form of long-term interdependent patterns of spending by networks of specialized firms.

• Such specialization allows each firm to focus on its core skills, but risks significant capital misallocation unless interdependencies between investment programs are coordinated effectively.

• Centered on the semiconductor industry, our research shows how firms may share information to coordinate R&D investments without divulging their individual trade secrets or acting in violation of anti-trust legislation.

• If accountants are to estimate accurately the value of R&D investments in “ecosystems” of innovation, an understanding of such information sharing arrangements is crucial.

4 | Managing inter-firm interdependencies in R&D investment: Insights from the semiconductor industry

Introduction

Investment in interdependent and long-term R&D programs is often distributed widely across firms to share the burdens of cost and uncertainty, and to allow individual organizations to focus on their areas of comparative advantage. A consequence is that any one firm can only evaluate and manage accurately the profitability of its R&D investments if it is aware of decisions and rates of progress being made by others. Our research is motivated by the challenge that firms face in exchanging such data without divulging proprietary knowledge or otherwise harming their individual interests.

Objectives

We set out to understand the information sharing practices that enable firms in the semiconductor and related industries to adjust to unanticipated changes, advances and setbacks affecting their interdependent programs of R&D. Such information sharing is arguably crucial if investments on the part of individual enterprises are to result in coherent and efficient outcomes at the level of a network of innovating firms. It is a topic that remains largely unexamined in studies of capital budgeting that focus primarily on how to value investments in R&D, rather than how to manage them as long-term and highly uncertain processes of interactive decision making by sets of firms.

Research methodology

Field based research was conducted internationally at semiconductor firms and their suppliers, and at industry consortia. The methods employed were interviews, participation in industry meetings and conferences, and perusal of archival materials.

First-hand interviews were carried out with executives and managers from firms and organizations across the relevant industries, including chip makers such as AMD, Intel and Texas Instruments, and suppliers including ASML and DuPont (Table 1).

Table 1: Summary of Interview Participants

Type of company represented: Number of interviews

Semiconductor Producers 8

Supplier Companies 7

Semiconductor Industry Consortia 11

Supplier Industry Consortia 9

Other 3

Total 38

We attended a series of 11, 3-5 day industry conferences dealing with information sharing and aligning of R&D programs by firms from across the semiconductor sector internationally.

An extensive archive of public record data was collected including reports and industry modelling documents prepared by various consortia of semiconductor producers and their suppliers. We accessed published annual reports of key firms, as well as presentations made by executives of those firms to industry analysts and to stockholder meetings.

Main findings and their implications for practical application

One of the distinctive features of the semiconductor sector is a public-record information system whereby firms share selected data regarding their R&D programs. The intent is to enable individual firms to align their investments in R&D with the achievement of particular industry or network-wide targets. Our findings relate to how such an information sharing system has been organized and made operational, and how barriers to putting it in place have been overcome in a key sector of the modern economy.

We identify three general processes. These are concerned with organizing the relevant set of firms and other agencies; modelling R&D interdependencies between them; and intervening to influence resource allocations.

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Organizing

The CFO of a major chip company told us of his firm’s policy to introduce more advanced manufacturing processes every two to three years for more efficient fabrication of increasingly powerful semiconductor products. As he explained, the company’s success depends on the ability of an extensive supplier network to match his firm’s preferred rate of progress:

“So, for us, it is simple: what is the fastest we can move and keep all of our ecosystem with us? That is the view we will always take.” 1

This concern to align suppliers’ pace of advance with that preferred by chip makers, and so to “keep all of our ecosystem with us”, has become a fundamental tenet across the semiconductor and related industries. Semiconductor firms anticipate certain shared requirements in the performance of future manufacturing technologies. These expectations are then refined, modified and updated in consultation with suppliers that carry out the requisite R&D.

Such collective action is meant to ensure the readiness of the supply base. It is intended, also, to lower the cost of new manufacturing technologies by allowing suppliers to amortize rising levels of R&D investment across larger volumes of demand:

“All of these improvements (in chip fabrication processes), sometimes called “scaling” trends, have been enabled by large R&D investments (in manufacturing technologies). In the last

three decades, the growing size of the required investments has motivated industry collaboration and spawned many R&D partnerships, consortia, and other cooperative ventures.” 2

With the increasing globalization of semiconductor production, networks of cooperation on R&D have been instantiated across all of the world’s major semiconductor regions. Two attributes of the networks are particularly significant: how cooperative action is organized; and how that structure permits information sharing on R&D programs across the boundaries of competing firms. Both may be illustrated by reference to so-called ITRS meetings where scientists and engineers from semiconductor producers, suppliers, universities and government research agencies are brought together in working groups several times a year. 3

Figure 1 shows the organizing framework for ITRS meetings, whose aim is to monitor progress (or its absence) in the development of specific types of semiconductor manufacturing technologies. The agenda and policy setting roles of the top-level International Roadmap Committee (IRC) are assumed by delegates from the major semiconductor producers. To further reinforce the influence of such firms, they are represented also throughout the individual Technology Working Groups (TWGs).

Several interviewees stated that it is highly beneficial to have agenda and policy setting roles held by semiconductor producers, rather than by research institutes as in other industries. This gives ITRS meetings a distinctive focus on means to meet specific industry needs at defined times. However, for the chip makers to engage appropriately with

International Roadmap Committee

18 International Technology Working Groups (TWG)

Emerging Research Materials TWG

Metrology TWG -------- Lithography TWGSystems Drivers &

Design TWG

Figure 1: Organization of the ITRS Network 4

1 Interview, Executive Vice President & CFO, semiconductor producer. 2 Various Authors, International Technology Roadmap for Semiconductors (Albany NY: International SEMATECH, 2010, p. 1). 3 ITRS stands for International Technology Roadmap for Semiconductors. 4 Adapted from International Technology Roadmap for Semiconductors (Albany NY: International SEMATECH, 2011, front sheet).

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one another, and with suppliers, depends on stringent rules as to what may be discussed regarding their respective R&D programs and what types of information may be exchanged. A key aim here is to enable inter-firm information sharing arrangements that do not violate antitrust legislation or divulge the trade secrets of individual participants. In the terms of an industry white-paper, it is a matter of finding terms of discussion and means of mediating between the interests of diverse organizations that allow “a common good (to be) pursued and collectively managed”5.

A core rule underpinning this inter-firm information sharing is that discussions at ITRS meetings, and the documents produced from them, are not to include “any commercial considerations pertaining to individual product or equipment”6. This stipulation is consistent with legislation such as the US National Cooperative Research Act of 1984. The Act provides that the pursuit of collaborative R&D programs may be shielded from punitive antitrust penalties only when such programs do not entail:

“exchanging information among competitors relating to costs, sales, profitability, prices, marketing, or distribution of any product, process or service that is not reasonably required to conduct the research and development that is the purpose of such venture.”

Rather, such exchanges are expected to centre on what the Act terms “theoretical analysis, experimentation, or systematic study of phenomena or observable facts” and the “extension of investigative findings or theory of a scientific or technical nature into practical application for experimental or demonstration purposes”7.

ITRS members thus meet as scientists and technologists to analyse issues such as the physics and chemistry affecting the design of future semiconductor devices, and the equipment sets and materials needed to manufacture them. The aim is to identify barriers to particular rates of progress, and the research pathways that might overcome them.

But this does not mean that matters of science and technology are disconnected from economic and financial concerns. Many IRC and TWG members hold detailed knowledge of the proprietary product and investment plans of their respective firms. While such matters are not for consideration at ITRS meetings, what is central to the discussions, and to the industry-level modelling of R&D that results from them, is to utilize and adapt scientific conventions to enable information sharing that guides and influences the proprietary decisions of individual firms. This use of scientific communication to achieve better informed investment decisions across networks of firms is a key innovation of the ITRS process, one that we analyze and illustrate in the next section.

5 W. Arden et al., “More than Moore - A White Paper” (Albany, NY: International SEMATECH, 2011, p. 6). 6 Various Authors, ITRS Executive Summary (Albany NY: International SEMATECH, 2011, p. 4). 7 US Congress, National Cooperative Research Act 1984, sections 2 (a) and (b).

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Modelling

A key output of ITRS meetings is a model that projects enhanced features of future semiconductor devices, and that tracks rates of progress in devising the technologies needed to manufacture them. The model is constructed and updated frequently by delegates from semiconductor firms and their suppliers, with support from industry consortia and research agencies. It is then available to each firm as an information source when appraising and adjusting its investment programs for changes, advances and setbacks affecting the programs of others. Our examination of the model sheds light on practices developed in a key economic sector by which networks of organizations may manage complex, highly uncertain, and interdependent investment processes.

Figure 2 illustrates the model by showing data related to one type of semiconductor product, DRAMs (memories), and to a core manufacturing technology, lithography. Making semiconductors more powerful involves continued miniaturizing of electronic feature sizes, which is enabled particularly by advances in lithographic technologies that pattern such features on silicon wafers. The figure projects feature sizes for DRAMs that continue to reduce at frequent intervals to 2026, followed by a ranking of potential lithographic technologies for forming them on silicon wafers. The incumbent, 193nm immersion, is shown as the sole technology in the very short run and, with so-called double pattern innovation, as the lead contender to 2015. Then, EUV (extreme ultraviolet), one of several lithographic technologies still in development, is ranked first among several next-generation systems.

The variables modelled in Figure 2, while overtly technical, reflect concerns that are also fundamentally financial and economic. At issue is a desire to continue a longstanding trajectory of profitability and growth in demand for semiconductor products through continued miniaturization of the electronic features comprising them:

“Since its inception ... a basic premise of the Roadmap (industry model) has been that continued scaling (or miniaturization) of electronics would further reduce the cost per function (historically, ~25 – 29% per year) and promote market growth for integrated circuits (historically averaging ~17% per year, but maturing to slower growth in more recent history)” 8.

Advances in lithography that scale down feature sizes are critical to both aims, helping to reduce cost by packing more elements on an area of silicon and to boost demand through enabling chips to operate faster and more effectively.

Modelling is a means for corporate customers to influence collectively the timing and sequencing of suppliers’ R&D investments. The intent on the part of the semiconductor firms is to align suppliers’ capital investment decisions with industry-wide objectives related to miniaturization, product costs, and demand. The process has been structured so that the semiconductor producers are seen as neither frustrating attempts by suppliers to devise technologies valuable to consumers, nor as asking them to disclose trade secrets to the benefit of their rivals.

Figure 2: Industry Level R&D Modelling - Lithographic Technologies

Year of fi rst production 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026

Feature Size Data for DRAM

Minimum feature sizes (nm): 36nm 32nm 28nm 25nm 23nm 20nm 17.9nm 15.9nm 14.2nm 12.6nm 11.3nm 10.0nm 8.9nm 8.0nm 7.1nm 6.3nm

Alternative Lithographic Technologies

193nm Immersion (incumbent) (CI)

193nm Double Pattern (modifi ed incumbent) Qualify Continuous Improvement (CI)

Extreme Ultraviolet (EUV)

Narrow Options193nm Multiple Pattern Qualify Continuous Improvement (CI)

Imprint Lithography

Extreme Ultraviolet (EUV) enhanced

Research and Development

193nm Multiple Pattern

Narrow OptionsMaskless Lithography Qualify Continuous Improvement (CI)

Imprint Lithography

DSA + Litho Platform

Extreme Ultraviolet (EUV) enhanced

Research and Development

Maskless Lithography

Narrow OptionsImprint Lithography Qualify Continuous Improvement (CI)

Litho + DSA

Other

Various Authors, ITRS - Lithography, (Albany, NY: ITRS, 2011, p.14).

8 Various Authors, ITRS Executive Summary (Albany NY: International SEMATECH, 2011, p. 1).

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With regard to the first of these issues, a central feature of the ITRS modelling process since its inception has been to forecast requirements in terms that do not preclude any pathways of supplier innovation, and that do not arbitrarily favour one solution over others9. Feature size data for DRAMs are shown in Figure 2 in terms that are intentionally neutral with respect to which lithographic technology (if any) may achieve the desired outcomes. Indeed, the red-coloured cells in the Figure indicate that, while imperfect “work arounds” might be available, the industry lacks a proven lithographic technology for cost effective high-volume DRAM manufacture from about 2016.

Matters are more complicated when it comes to modelling progress by suppliers of alternative lithographic technologies without requiring them to disclose sensitive and confidential information. The ITRS, as its authors note, is “put together in the spirit of a challenge” to suppliers, one in which they are encouraged to compete to devise new manufacturing technologies10. What is envisaged in the case of a particularly complex technology like lithography is a funnelling process in which an extensive set of alternatives is pursued initially by suppliers, and gradually winnowed-down through evaluation and pilot-testing to arrive ideally at one superior system for commercialization and use world-wide. Figure 2 rank-orders three potential technologies for use from about 2015. The incumbent system is projected to be ineffective for lead-edge manufacture beyond that date. The challenge to suppliers with a stake in the system is to disprove that assessment, extending the technology’s usefulness if only for a short period and thus deferring chip makers’ need to spend on complex new equipment. By contrast, the competitive issue for suppliers investing in next-generation technologies is to demonstrate the superiority of one of them, with EUV listed as the current front-runner.

Modelling involves tracking and evaluating the development of alternative technologies, highlighting publicly the obstacles to particular pathways of innovation, so that firms throughout the semiconductor and supplier industries may make more informed resource allocation decisions:

“The ITRS has(sought to improve) the quality of R&D investment decisions made at all levels and(to help) channel research efforts to areas that most need research breakthroughs”11.

Modelling depends crucially on the willingness of suppliers to make frequent and credible disclosures concerning the progress of their R&D programs. Such firms are likely to be predisposed to cooperate with their major customers, and may view disclosures as opportunities to “..influence the industry (in) their direction, if they have a real solution, versus hiding it”12. But those considerations are paired with concerns on the part of suppliers that the modelling process should portray information in an unbiased and even-

handed way, and that it should not call for the disclosure of proprietary data. The solution that has been devised in this sector is to combine the presumed openness of scientific enquiry with specific means for protecting intellectual property rights:

“So if you keep it to the issues, the concerns – the science behind it, less on how you go and fix it in practice – that is something that is very important to (the modelling process)”13.

The idea is that, following ordinary professional conventions, experts from a supplier firm should be prepared to discuss the science underlying their technologies with peers from chip makers, research agencies, and even competing supplier firms. To that end, conferences on the development of lithographic technologies have been hosted frequently by SEMATECH, a consortium of semiconductor producers, and SPIE, a professional association of optics and photonics researchers.

Suppliers’ claims are exposed to expert scrutiny in scientific and professional forums with intent to enhance the quality of information available for ITRS modelling and industry-wide decision making. Assessment involves probing the physics and chemistry underpinning suppliers’ claims. But more is at stake than the laboratory science. Technology development requires engineering a device to operate effectively in high-volume factories. Insofar as a supplier’s trade secrets consist in such engineering, the firm may be reluctant to detail the construction of its new devices in an open forum. Here, protection is provided by allowing claims regarding device efficacy to be validated through third-party testing that is facilitated by agencies such as university or consortia laboratories. Suppliers developing EUV power sources incorporated versions of the components in early-stage lithographic tools for evaluation at the IMEC laboratories in Leuven, for instance, and at the University at Albany’s nanotechnology research centre.

Figure 3 illustrates the publicly available information on suppliers’ rates of R&D progress. It compares results for three competing suppliers devising light sources for EUV lithography, with the actual performance of one of them seen as lagging that of the other two during 2009, and projected to do so during early-stage commercialization of the component14.

In more familiar settings of intra-firm capital investment, confidential technical information may be used directly to inform decisions. But where interdependent technology investments are made by networks of firms, novel mechanisms are called for such as ITRS modelling. This allows relevant information exchanges to take place without eroding individual firms’ intellectual property. In the sector analyzed here, one result is a ranking of alternatives, such as the indication that EUV remains the most likely next-generation lithography (Figure 2).

9 Various Authors, International Technology Roadmap for Semiconductors (Albany NY: International SEMATECH, 2003, p. 5), emphases in original. 10 Ibid., p. 4. 11 Ibid, p. 1. 12 Interview, R&D executive, semiconductor producer. 13 Interview, R&D executive, supplier company. 14 While the particular diagram does not name the three supplier firms, their identities are well known to industry participants

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The ranking of technologies is based on conjoint technical and financial appraisals that derive from on-going tests of the systems’ performance in laboratories and development facilities. This is something that is tentative, and changeable by competition from alternative technologies. Effectiveness of a lithographic technology is seen as its ability to pattern layers of ever smaller electronic features on silicon, in line

with historic levels of cost containment. So, for instance, Figure 4 projects average industry-wide costs-of-ownership for EUV lithography. It shows the system as potentially achieving significant economies in key lithographic processes when compared with available alternatives. This results particularly from projections of lower costs for the reticle (or mask) component of EUV lithography.

Figure 4: Lithography Cost-of-Ownership Estimates: Projected Full-Costs of Patterning a Layer of Circuitry on Silicon16

0

50

100

150

200

250

300

350

Public roadmaps enable 125 wphat 15 mJ/cm2: ~2x power to go

Feb 2009 Oct 2009 Apr 2010 NXE: 3100 NXE: 3300B

Expo

se P

ower

(W

)

Commercialised systems

2012/132011

Prototype lithographic systems

Supplier 1

Supplier 2

Supplier 3

0%

50%

100%

150%

200%

250%

193nm system~2009

Litho

Deposition

Metrology

Etch

Clean

Reticle

EUV system~2015

Cost Elements

Enhancements to incumbent 193nm lithography~ 2015

Figure 3: Appraising Suppliers’ R&D Progress - EUV Power Sources15

15 Adapted from ASML Presentation at SEMATECH Symposium, Taiwan, September 2010, from SEMATECH website. 16 Adapted from A. Wuest, A. J. Hazelton and G. Hughes, “Estimation of cost comparison of lithography technologies”, in F. M. Schellenberg and

B. M. La Fontaine (eds.), Alternative Lithographic Technologies: Proceedings of SPIE Conference, Vol. 7271 (Bellingham, WA: SPIE, 2009). Estimates based on high volume patterning of memory products.

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Intervening

If the organizing and modelling of technological and financial trajectories go hand in hand, a way of intervening so as to align the multitude of discrete investments is also needed. During the often lengthy process of developing new technologies, capital spending may become stalled by what some regard as undue pessimism about the chances for success. Equally, investment in some elements of a technology may persist without awareness that creating others faces insurmountable odds. Intervention practices are meant to resolve such issues and thus to encourage or discourage particular patterns of resource allocation. In the semiconductor context, interventions consist importantly in integrating the components of an emergent technology in laboratories and development facilities, and then reporting the results publicly. The development of EUV lithography will again serve to illustrate.

“The lithography that’s being done now is way out of the realm where your intuition works”, a leading lithographer told us17. Equally, the appraisal of investment in R&D is not a matter only of building forecasts and simulations leading to NPV calculations. It depends crucially on interventions. These are aimed at identifying scientific, engineering or cost barriers to the effective working of a technology, through integrating its various components in test beds. To show that a system works, even on a small scale in laboratory settings, is key to ranking that alternative convincingly in such as an ITRS model and thus to eliciting more substantive investment.

As early as 1992, ITRS modelling identified a need for R&D on next-generation lithographic technologies. Five years later, Intel executives argued based on their own internal assessments that one approach, EUV, had received significantly less than its deserved attention and investment. A company was formed, the EUV LLC, jointly held by Intel and other semiconductor firms. It was effectively a “bank”, as a finance manager said to us, through which the partners contributed venture capital for a key intervention18.

The EUV LLC provided project funding to an independent third-party, the US Virtual National Laboratories, to integrate the components of the lithographic system as a prototype Engineering Test Stand (ETS). The components were to be provided by suppliers from across the industry. The intent in building the ETS was to provide a framework for technology and information sharing between suppliers, chip makers, the EUV LLC, and the Laboratories, that was enacted in a controlled environment and aimed at protecting contributors’ individual interests. New intellectual property created by

the Laboratories was to vest in the EUV LLC whose licensing of it to lithographic component suppliers was intended to preserve competition between them. By 2001, the ETS was printing wafers to required tolerances, albeit in a mode still far from capable of high-volume semiconductor production.

The successful integration of components was significant for unfreezing investment in EUV. The intervention had been funded by major semiconductor firms, including Intel, whose combined market shares spoke to potential industry-wide adoption of the technology. Also, albeit indirectly, it indicated possible revenue levels for lithography equipment manufacturers and component suppliers. And, in showing that EUV lithography did not seem to face insuperable “show-stoppers”, in the industry colloquialism, the intervention lowered investment risk and shifted the focus to commercialization. In 2000, the lithography equipment manufacturer, ASML, announced its program to commercialize EUV tools. Exitech Limited took forward the construction of micro-stepper machines that the SEMATECH consortium would use for cooperative industry-wide innovation and firms like Intel for proprietary development. And significant venture capital activity followed, which accelerated development by suppliers of components such as EUV power sources, optics and masks.

This is not to suggest a straightforward path to commercialization. Timelines have been missed repeatedly due to economic downturn and technical delays. Yet, SEMATECH and other consortia have continued to complement proprietary commercialization by supporting generic component development and integration. During 2006, ASML delivered full-field EUV systems to New York’s University at Albany and to the IMEC facility in Leuven to facilitate later-stage component development. And the same firm announced “first light” in April 2010 – the successful printing of wafers by a system operating at significantly increased levels of source power and throughput.

17 Interview, Research Fellow, semiconductor producer. 18 Interview, Research Fellow, semiconductor producer.

Managing inter-firm interdependencies in R&D investment: Insights from the semiconductor industry | 11

Conclusion

Advances in the design and manufacture of semiconductor devices are highly significant for the modern economy. Much attention has been paid recently to inter-company coordination mechanisms, both within the semiconductor industry and beyond. But the capital budgeting aspects of such coordination processes have been largely neglected. Our research has examined three aspects of such mechanisms: the organising of appropriate forums for information exchanges between competing firms; the modelling of joint financial and technological trajectories, in so far as these impact on the decisions of individual firms that are needed to optimise the financial returns for all parties; and the mechanisms for intervening, so as to align the multiple discrete investments required. We analyze these processes and the linkages between them to capture the roles they play in informing investment decisions across the boundaries of firms and sectors. For it is these processes, we suggest, that are increasingly important for understanding and managing capital investment programs carried out by sets of firms in a network or innovation “ecosystem”.

Additional outputs of interest to the reader

P. B. Miller, J. L. Moll and T. O’Leary, “Pushing back the red brick wall”, Working Paper: University of Manchester/ London School of Economics, July 2012. (Available from the authors).

P. B. Miller, J. L. Moll and T. O’Leary, “The power of networks”, Excellence in Leadership, July 2011, pp. 50 – 52.

References and further reading

Ariela Caglio and Angelo Ditillo. Management Accounting in networks: Techniques and applications Research Executive Summaries Series, Vol. 2, No. 14.

Hakan Hakansson, Kalle Kraus and Johnny Lind, Accounting in Networks (Stockholm and London: Routledge, 2010)

Researchers’ names and contact details including e-mail or address

Ted O’Leary Manchester Accounting and Finance Group University of Manchester Crawford House Oxford Rd Manchester M13 9PL Email Address: ted.o’leary@mbs.ac.uk

Peter Miller Department of Accounting London School of Economics and Political Science Houghton Street London WC2A 2AE Email Address: p.b.miller@lse.ac.uk

Jodie Moll Accounting and Finance Group Manchester Business School University of Manchester Crawford House Oxford Rd Manchester M13 9PL Email Address: Jodie.moll@mbs.ac.uk

Acknowledgements

We are grateful to CIMA’s General Charitable Trust for funding this research project.

ISSN 1744-7038

Chartered Institute of Management Accountants 26 Chapter Street London SW1P 4NP United Kingdom T. +44 (0)20 7663 5441 E. research@cimaglobal.com www.cimaglobal.com

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