MAIN MEMORY SYSTEM

CS/ECE 6810: Computer Architecture

Mahdi Nazm Bojnordi

Assistant Professor

School of Computing

University of Utah

Overview

¨ Announcement¤ Homework 3 submission deadline: Nov. 11th

¨ This and the following lectures¤ Dynamic random access memory (DRAM)¤ DRAM operations¤ Memory scheduling basics¤ Emerging memory technologies

Computer System Overview

¨ DRAM technology is commonly used for main memory

Computer System Overview

¨ DRAM technology is commonly used for main memory

CPU

Computer System Overview

¨ DRAM technology is commonly used for main memory

CPU

Memory

Computer System Overview

¨ DRAM technology is commonly used for main memory

CPU

Memory

¨ SRAM is used for caches

¨ DRAM is used for main memory

¨ DRAM is accessed on a TLB or last level cache miss

Static vs. Dynamic RAM

¨ Fast and leaky¤ 6 transistors per bit¤ Normal CMOS Tech.

¨ Static volatile¤ Retain data as long as

powered on

¨ Dense and slow¤ 1 transistor per bit¤ Special DRAM process

¨ Dynamic volatile¤ Periodic refreshing is

required to retain data

Static RAM (SRAM) Dynamic RAM (DRAM)

DRAM Organization

¨ DRAM array is organized as rows×columns

DRAM Organization

¨ DRAM array is organized as rows×columns

wordline

bitline

DRAM Organization

¨ DRAM array is organized as rows×columnsde

code

r

wordline

bitline

DRAM Organization

¨ DRAM array is organized as rows×columnsde

code

r

Sense Amplifier

row buffer

wordline

bitline

DRAM Organization

¨ DRAM array is organized as rows×columnsde

code

r

Sense Amplifier

row buffer

wordline

bitline

Data Block

multiplexer

DRAM Organization

¨ DRAM array is organized as rows×columnsde

code

rRow Address

ColumnAddress

Sense Amplifier

row buffer

wordline

bitline

Data Block

multiplexer

DRAM Organization

¨ DRAM array is organized as rows×columnsde

code

rRow Address

ColumnAddress

Sense Amplifier

row buffer

wordline

bitline

Data Block

multiplexer All reads and writes are performed through the row

buffer

Reading DRAM Cell

¨ DRAM read is destructive¤ After a read, contents of cells are destroyed

Precharge Activate Sense

Reading a zero

Reading a one

Reading DRAM Cell

¨ DRAM read is destructive¤ After a read, contents of cells are destroyed

Precharge Activate Sense

Reading a zero

Reading a one

0V/2

?

Reading DRAM Cell

¨ DRAM read is destructive¤ After a read, contents of cells are destroyed

Precharge Activate Sense

Reading a zero

Reading a one

0V/2

?

1V/2

?

Reading DRAM Cell

¨ DRAM read is destructive¤ After a read, contents of cells are destroyed

Precharge Activate Sense

Reading a zero

Reading a one

0V/2

?

1V/2

?

1V/2 + ℇ

0

Reading DRAM Cell

¨ DRAM read is destructive¤ After a read, contents of cells are destroyed

Precharge Activate Sense

Reading a zero

Reading a one

0V/2

?

1V/2

?

1V/2 + ℇ

0

0V/2

?

Reading DRAM Cell

¨ DRAM read is destructive¤ After a read, contents of cells are destroyed

Precharge Activate Sense

Reading a zero

Reading a one

0V/2

?

1V/2

?

1V/2 + ℇ

0

0V/2

?

1V/2

?

Reading DRAM Cell

¨ DRAM read is destructive¤ After a read, contents of cells are destroyed

Precharge Activate Sense

Reading a zero

Reading a one

0V/2

?

1V/2

?

1V/2 + ℇ

0

0V/2

?

1V/2

?

1V/2 - ℇ

V

DRAM Row Buffer

¨ All reads and writes are performed through RB

Data Array

Row Buffer (RB)

DRAM Cell

DRAMSense Amp.

Row Access Strobe (RAS)

Column Access Strobe (CAS)

DRAM Row Buffer

¨ Row buffer holds a single row of the array¤ A typical DRAM row (page) size is 8KB

¨ The entire row is moved to row buffer; but only a block is accessed each time

¨ Row buffer access possibilities¤ Row buffer hit: no need for a precharge or activate

n ~20ns only for moving data between pins and RB

¤ Row buffer miss: activate (and precharge) are neededn ~40ns for an empty rown ~60ns for on a row conflict

DRAM Refresh

¨ Charge based memory cells may gradually lose their states due to current leakage

¨ DRAM requires the cells’ contents to be read and written periodically¤ Burst refresh: refresh all of the cells each time

n Simple control mechanism

¤ Distributed refresh: a group of cells are refreshedn Avoid blocking memory for a long time

n

time

bursts m

time

distributed