magillem system on chip assembly fueled with 3dexperience ... · with 3dexperience platform...

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IP & SOC revision control DS 3DEXPERIENCE Platform IP’ DB IP DB Defects Design Platform Fueled with DS 3D IP-XACT Design Register Capture IP-XACT Registers IP & Connectivity Capture IP-XACT Components MAGILLEM DESIGN PLATFORM Desi Platf Fueled ith DS 3D D i IP Select IP configuration IP Extraction Chip Composition FMEA Chip Assembly SPECIFICATIONS DATASHEETS Register Capture R C IP & IP Catalog IP Management and Integration: Synchronize the design database and documentation with the 3DEXPERIENCE platform Software that streamline your design and document ation flows WWW.3DS.COM/HIGH-TECH Magillem System on Chip Assembly fueled with 3DEXPERIENCE Platform optimizes IP governance design flow, IP Reuse and collaborative work.

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Page 1: Magillem System on Chip Assembly fueled with 3DEXPERIENCE ... · with 3DEXPERIENCE Platform optimizes IP governance design flow, IP Reuse and collaborative work. For more information,

IP & SOC revision control

DS 3DEXPERIENCE Platform

IP’

DB

IP

DBDefects…

Design Platform Fueled with DS 3D

IP-XACT Design

Register CaptureIP-XACTRegisters

IP &ConnectivityCapture

IP-XACTComponents

MAGILLEM DESIGN

PLATFORM

Desi Platf Fueled ith DS 3DDesi

IP Select IP con"guration IP ExtractionChip

Composition

FMEA

Chip Assembly

SPECIFICATIONS

DATASHEETS

Register CaptureRe C

IP &

IP Catalog

IP Management and Integration: Synchronize the design database

and documentation with the 3DEXPERIENCE platform

Software that streamlineyour design and document ation "ows W

WW.3DS.COM/HIGH-TECH

Magillem System on Chip Assembly fueled

with 3DEXPERIENCE Platform optimizes IP governance

design flow, IP Reuse and collaborative work.

Page 2: Magillem System on Chip Assembly fueled with 3DEXPERIENCE ... · with 3DEXPERIENCE Platform optimizes IP governance design flow, IP Reuse and collaborative work. For more information,

For more information, feel free to connect to 3DS.COM/HIGH-TECH

Business Case - semiconductors

“We optimized IP reuse, improved IP quality & integration while reducing time to market”

IP based design methodologies in the Semiconductor industry

System-on-Chip (SoC) designs now and into the future are almost all platform based. This means that

the sub systems that make up them are usually a blend of internally developed and externally acquired

IP that can be catalogued for a dedicated purpose such as 3D video, GPS, Wi-Fi communication and so

on. SoCs can save space and power while improving speed, performance and in an ASIC are the lowest

costs for the highest volume. Designing a platform based SoC that reaches its business requirements

for time to market amounts to the e"ective reuse and management of internal and external IP blocks,

digital or analog. This includes using standard processes with sign-o" and release controls, enforcing

the appropriate use of licensed and negotiated IP and improving the ability to find IP whilst maintaining

tight controls on visibility and access.

Situation to be improved

The chip architect is defining the system partition/map and is looking for potential IP. He/she searches

internally by looking at other projects, talking to peers over the phone and by email and tries to piece

together what is available. IP data are not consolidated, it is bit piece and fragmented over many

systems, sometimes incomplete. It is difficult to find out contract and legal conditions on external IP.

A lot of work and time is required to try to understand what is available and in what state. The result

is an increase in the task which can result in a delay to the market. Even worse is that the design may

start with illegal IP or a new sub system / IP block may be developed in the context of the project when

in fact it is not actually necessary.

Goal

The goal is to incorporate already existing IP either external of internal (already approved in terms of

legal, finance, compliance, IP maturity…) in the project to avoid development costs and speed time to

market. To be confident in the IP quality and validity, to seamlessly integrate the IP into the elaboration

environment and to allow for the dynamic updating of important governance assets such as defects /

change as IP is reused across the projects in the company.

Solution

The solution experience combines the usage of Magillem Content Platform and Dassault Systemes’

3DEXPERIENCE business platform. It allows the IP catalogue to be leveraged to search for existing IP,

to request access, to request a need for IP so that all IP tasks are centralized and capitalized for the

overall benefit of the company. The elaborated design is constructed in Magillem Front end Assembly

tools (connectivity & registers) and referenced back in the catalog to the configurable IP that has

been instantiated. This allows for the e"ective tracking of change/enhancements/maturity/defects

throughout the entire design (and manufacturing) process. Use of IP and issues/ changes within a

project context can be capitalized for the benefit of other projects Mistakes are eliminated , the correct

IP is “designed in” , productivity is increased , time to market windows are met.

Our customer is a key

supplier for automotive

electronics :

Magillem Content Platform& Dassault Systemes

3DEXPERIENCE Platform

Design database bringing IP management

capabilities to all IP lifecycle

stakeholders through

an integrated platform

Fuel the

Optimize IP Governance

accessing IP relevant facets

according the type of user

and context

Improve the flowconnecting IP design reuse

and IP governance processes

Manage Defect & Traceability

expediting propagation of IP

modifications and improving

IP Quality.