Spring 2003 Yield Management Solutions 31

quantify the impact in terms of both parametric perfor-mance and yield. If the root cause can be properly quan-tified, the process and integration engineering teamscan be confident they are working on the best solution.In addition, proper quantification of the issue providesthe basis for the identification of critical metrics.Through the monitoring of these metrics, progresstoward the elimination of the issue can be tracked.

Two-component strategyThe strategy is comprised of two components, electronbeam inspection and advanced test chip design. Themerging of these two components is called eDo.1 Thefundamental concept of the eDo technology is the useof an automated e-beam defect inspection tool and datafiltering techniques to isolate only electrical defects,while at the same time using smart test chip design tomaximize wafer throughput.

The isolation of the electrical defects from the manyphysical and nuisance defects is critical to acceleratingyield learning. This is done using voltage contrast (VC)methodology. Contrast imaging is used to differentiatefloating and grounded structures.

In addition to using VC filtering, smart test chipdesigns are utilized to dramatically improve the relativethroughput of the inspection allowing for what can be

Copper Interconnects

Cycling Your Way to Faster Developmentand Integration at the BEOL

Accelerating Copper Interconnect Development

Judy Shaw, Richard L. Guldi, Tae Kim, Dan Corum, and Jeffrey Ritchison, Texas InstrumentsSteve Oestreich, Jason Lin, Kurt Weiner, Kara Davis, and Robert Fiordalice, KLA-Tencor Corporation

Development and integration learning cycles of a 130 nm advanced logic device were accelerated using area-accelerated e-beam inspection. The devices used in this study employed a low-κ dielectric (κ<3.0), a silicon carbide (SiC) etch-stopscheme, and several levels of copper interconnect.

D E F E C T M A N A G E M E N T

IntroductionWith the introduction of copper intercon-nects at 180 nm, and the subsequentblending of low-κ interlevel dielectrics(ILD) at 130 nm, interconnect modulescontinue to represent the biggest challengefor achieving fast ramps and high yields ofthe most advanced logic devices. Moreover,technology introduction cycles of 18 months,or less, require that technology ramps beefficient and that the limited number ofcycles of learning be used effectively.Leading edge microprocessor technologiesat the 100 nm node will utilize eight ormore levels of back-end-of-line (BEOL)interconnect, making up over 70 percent of the device processing. So, rapid BEOLprocess development and integration arekey to a timely ramp from the developmentto pilot production stages.

Rapid development requires that problemsbe identified and isolated quickly. Once theissue is identified, process and integrationsplits that target the root cause can beidentified. The key is providing the yieldand integration teams with tools that canhelp them identify the source of the issuequickly. At the same time, it’s important to

Spring 2003 Yield Management Solutions32

processing time requirements may belengthy. In contrast, eDo requires onlyback-end interconnect structures.

Case study 1The first experiment focused on post-ECD (electrochemical deposition)anneals. It is well known that the post-ECD anneal is a critical componentof the copper interconnect processdevelopment. Performing an annealinduces copper grain growth andreleases stress. eDo was used to helpquickly define a thermal budget, whichprovided for high-yielding via chains.Figure 2 is a histogram showing totalelectrical defect counts in the eDo teststructures after a post-copper CMP(chemical mechanical polishing) fortwo different ECD anneal conditions.Electrically probable test structuresconfirmed that the defect types wereelectrical in nature, and a sharp

distinction could be discerned between the two annealconditions. Figure 3 is a cumulative probability plotshowing the via chain results. Inset in the figure is aFIB (focused ion beam) image collected from failureanalysis. The total inspection and review took less than90 minutes per wafer and, because the ID scan providesthe exact defect locations, the FIB analysis took lessthan 45 minutes. Conventional defect inspection andsourcing methods typically take much longer than this.

called “area acceleration.” The inspection methodologyis comprised of two separate e-beam scans of the testchip structure. The first scan, called the assessment(assess) scan, inspects only a very small potion of the viachain (typically eight percent), and provides an overalldefect assessment with regards to the test structure.

The data collected in the assess scan is used to programthe sites to be scanned in the second scan, which iscalled the identification (ID) scan. It is in the ID scanthat the precise x-y location of the physical source of anelectrical defect is determined. This data is then portedto a SEM review tool. An example of how assess and IDscans are used to isolate electrical defects is shown inFigure 1. In summary, eDo provides: 1) Voltage contrastidentification and filtering to identify electrical defects,2) High relative scan rates through area acceleration,and 3) Exact locations of physical sources to electricaldefects.

The focus of this work is to use eDo to help driveprocess development and process integration. The ability to precisely locate the defect site quickly is anadvantage over short loop development, which requiresboth in-line probe, and at times, extensive failureanalysis. While SRAM bit-map analysis can provideprecise defect locations, the device must be an electri-cally addressable full-flow design and the associated

D E F E C T M A N A G E M E N T

Figure 2. Histogram of “electrical” defect counts from e-beam inspec-

tion, comparing two ECD anneal splits.

Figure 1. On the left is a typical via chain failure as detected by the assess scan in eDo. The

ID scan confirms the exact (x,y) location of the defect for FIB analysis.

Assess and ID ScanAssess Scan ID Scan FIB Analysis

Spring 2003 Yield Management Solutions 33

Case study 2This second experiment was designed to examine thecorrelation between the defect densities reported byeDo and those obtained with conventional inline proberesults. Conventionally-tested via chains were printedand processed in close proximity to the eD0 via chains.True electrical defect density (D0) for the probe teststructures was calculated using Poisson’s equation, Y = e-AD0. The calculated D0 value in the eD0 structureswas calculated from the same equation. Figure 4 is agraph comparing the D0 from the probed and eD0 teststructures for 13 wafers from various lots.

While there is certainly some correlation between theconventional probe and eDo results for wafers 1-6, it is

D E F E C T M A N A G E M E N T

clear that the eD0 defect density values trend higherthan those calculated for theprobed structures for the high-er numbered wafers. The dis-crepancy can be understoodupon closer examination of thedifferences between the twostructures.

The electrically probed viachains used in this study were546K vias in length. WhileeD0 via chain segments were415K vias in length, moregranularity is achieved withthe addition of 70 percentmore via chains in each die. Itis possible to achieve a much

higher via chain density per unit area with the eD0

structure due to the fact that bond pads are notrequired. This results in a higher and more accurateestimation of the true detect density.

In addition to the added granularity, this evaluationuncovered a new defect type, which was named “resistivevias.” It resulted in an even higher defect density ascalculated using eD0. Resistive vias are defined as singleor multiple vias, which when electrically probed are notof high enough resistance to cause an electrical limitfailure, and are thus not captured as failures with con-ventional inline electrical probe.

These resistive vias image “gray” in the e-beam voltagecontrast mode. The inset in Figure 4 is an example of aresistive via which imaged gray in VC mode and wascaptured by the eD0 strategy, but not by inline probe.One of the primary advantages of eD0 is in the detectionof single and multiple resistive via defects in a singlevia chain. This enhances the accuracy of the eD0 ascompared to electrical probe results.

The insertion of multiple bond pads could be utilizedto closer approximate true defect density on conven-tional electrical structures. However, the “tapping” oflarge via chains to gain granularity requires largeamounts of area due to the number of bond padsrequired, as well as a more complicated electrical prob-ing scheme. In contrast, bond pads are not required forthe eD0 methodology resulting in a more efficient utilization of silicon for test structure design.

Def

ects

/cm

2

14.00

12.00

10.00

8.00

6.00

4.00

2.00

0.00

Inline Probe Data

eD0

1 4 8 12

Wafer ID

Figure 4. Comparison of via chain defect densities calculated from

conventional and eD0 via chain test structures.

Figure 3. On the left is the cumulative distribution plot from the conventional via chain, which confirms the

high defect density, captured in the eD0 scans.

Sub-surface Via Void Detection

Spring 2003 Yield Management Solutions34

ConclusionAn advanced yield methodology, eD0, has beenemployed to significantly reduce the development cycletime of a 0.13 µm copper/low-κ logic technology. Thedefect densities determined by eD0 trend well with thedefect densities calculated from the electrical parametrics.In addition, eD0 provides a means to maximize teststructure area in conjunction with an increase in sensi-tivity over conventional inline electrical probe.

AcknowledgementsThis paper is based on a previously published article,“Rapid Interconnect Development Using an Area

Accelerated Electron Beam Inspection Methodology,”Proceedings of the 2002 International InterconnectTechnology Conference, June 3-5, 2002, p. 33; permis-sion to publish was granted by IITC. The authorswould like to thank the KFAB Pilot line engineeringstaff members, as well as Doron Gal, Gaurav Verma,David Price, Peter Nunan, and Tom Long.

References1. R.Guldi, J. Shaw, J. Ritchison, S. Oestreich, K. Davis,

R. Fiordalice - “Characterization of Copper Voids in DualDamascene Processes” Advanced Semiconductor Manu-facturing Conference, April 2002.

D E F E C T M A N A G E M E N T

As the industry was making the transition from 1x to 5xmasks, KLA-Tencor and SEMATECH formed a partner-ship to develop the next-generation reticle inspectionplatform for the 100-nm node.

As part of an innovative clause in the partnership, it was agreed that if the TeraStar product were a success,KLA-Tencor would paySEMATECH a royalty on product shipments.SEMATECH would reinvest the funds so morebreakthrough technologieslike TeraStar can be developed to enable futuretechnology generations.

At the 2002 Semicon Westshow in San Francisco,KLA-Tencor CEO, Ken Schroeder, presented a check for $409,000 toBob Helms, CEO ofSEMATECH, in what

promises to be “the first of many checks.”

“It’s time for me to perform an unnatural act, which isto give money away,” announced Ken Schroeder, “I wantto thank SEMATECH for the great vision they had inseeing the roadmap, envisioning where our industryneeded to go, and for their faith in us and this program.”

Royalty check presented to Bob Helms (CEO, Sematech) by Ken Schroeder at the company’s Yield Management Seminar held

during Semicon West 2002.

A Resounding Success

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©2002 KLA-Tencor Corporation.