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LTM8067

1Rev. D

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TYPICAL APPLICATION

FEATURES DESCRIPTION

3VIN to 40VIN Isolated µModule DC/DC Converter

The LTM®8067 is a 2kVAC isolated flyback µModule® (power module) DC/DC converter. Included in the pack-age are the switching controller, power switches, trans-former, and all support components. Operating over an input voltage range of 3V to 40V, the LTM8067 supports an output voltage range of 2.5V to 24V, set by a single resistor. Only output and input capacitors are needed to finish the design.

The LTM8067 is packaged in a thermally enhanced, com-pact (9mm × 11.25mm × 4.92mm) overmolded ball grid array (BGA) package suitable for automated assembly by standard surface mount equipment. The LTM8067 is available with SnPb or RoHS compliant terminal finish.

APPLICATIONS

n 2kVAC Isolated µModule Converter n UL60950 Recognized File 464570 n Wide Input Voltage Range: 3V to 40V n Up to 450mA Output Current (VIN = 24V, VOUT = 5V)

Output Adjustable from 2.5V to 24V n Current Mode Control n User Configurable Undervoltage Lockout n Low Profile (9mm × 11.25mm × 4.92mm)

BGA Package

n Isolated IGBT Gate Drive n Industrial Sensors n Industrial Switches n Test and Measurement Equipment

Maximum Output Current vs VIN2kVAC Isolated µModule Regulator

VIN (V)0 10 20 30 40

0

200

400

600

LOAD

CUR

RENT

(mA)

Max Load Current vs VIN

8067 TA01b

8.25k

2.2µF22µF

VIN

GND

VOUT

VOUTN

RUN

FB

VIN3V TO

40V

VOUT5V

LTM8067

8067 TA01a

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LTM8067

2Rev. D

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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

VIN, RUN, BIAS ........................................................42VVOUT Relative to VOUTN .............................................25VVIN + VOUT (Note 2) ...................................................48VGND to VOUT– Isolation (Note 3) ...........................2kVACMaximum Internal Temperature (Note 4) .............. 125°CPeak Solder Reflow Body Temperature ................. 245°CStorage Temperature.............................. –55°C to 125°C

(Note 1)

TOP VIEW

H

G

F

E

D

C

B

A

1 2 3 4 5 6 7

BANK 2VOUTN

BANK 1VOUT

BANK 4GND

RUNFB

BANK 5VIN

BGA PACKAGE38-LEAD (11.25mm × 9mm × 4.92mm)

TJMAX = 125°C, θJA = 20.8°C/W, θJCbottom = 5.1°C/W, θJCtop = 18.4°C/W, θJB = 5.3°C/WWEIGHT = 1.1g, θ VALUES DETERMINED PER JESD 51-9, 51-12

ORDER INFORMATION

PART NUMBER PAD OR BALL FINISH

PART MARKING PACKAGE TYPE

MSL RATING TEMPERATURE RANGE (SEE NOTE 4)DEVICE CODE

LTM8067EY#PBF SAC305 (RoHS) LTM8067Y e1 BGA 3 –40°C to 125°C

LTM8067IY#PBF SAC305 (RoHS) LTM8067Y e1 BGA 3 –40°C to 125°C

LTM8067IY SnPb (63/37) LTM8067Y e0 BGA 3 –40°C to 125°C

• Contact the factory for parts specified with wider operating temperature ranges.

• Device temperature grade is indicated by a label on the shipping container.• Pad or ball finish code is per IPC/JEDEC J-STD-609.

• Recommended LGA and BGA PCB Assembly and Manufacturing Procedures

• LGA and BGA Package and Tray Drawings

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LTM8067

3Rev. D


ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: VIN + VOUT is defined as the sum of (VIN – GND) + (VOUT – VOUTN).Note 3: The LTM8067 isolation test voltage of either 2kVAC or its equivalent of 2.83kVDC is applied for one second.Note 4: The LTM8067E is guaranteed to meet performance specifications from 0°C to 125°C. Specifications over the –40°C to 125°C internal temperature range are assured by design, characterization and correlation

The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25°C, RUN = 2V (Note 4).

PARAMETER CONDITIONS MIN TYP MAX UNITS

Minimum Input DC Voltage RUN = 2V l 3 V

VOUT DC Voltage RADJ = 15.4k RADJ = 8.25k RADJ = 1.78k

l

4.75

2.5 5

24

5.25

V V V

VIN Quiescent Current VRUN = 0V Not Switching

7

3 µA mA

VOUT Line Regulation 3V ≤ VIN ≤ 40V, IOUT = 0.1A, RUN = 2V 1 %

VOUT Load Regulation 0.05A ≤ IOUT ≤ 0.3A, RUN = 2V 1 %

VOUT Ripple (RMS) IOUT = 0.1A, 1MHz BW 30 mV

Isolation Voltage (Note 3) 2 kV

Input Short-Circuit Current VOUT Shorted 80 mA

RUN Pin Input Threshold RUN Pin Falling 1.18 1.214 1.25 V

RUN Pin Current VRUN = 1V VRUN = 1.3V

2.5 0.1

µA µA

with statistical process controls. LTM8067I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. Note that the maximum internal temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors.

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LTM8067

4Rev. D


TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency vs Load Current, VOUT = 2.5V

Efficiency vs Load Current, VOUT = 8V


Efficiency vs Load Current, VOUT = 3.3V


Input Current vs Load Current VOUT = 2.5V



Input Current vs Load Current VOUT = 3.3V

Unless otherwise noted, operating conditions are as in Table 1 (TA = 25°C).

LOAD CURRENT (mA)0 50 100 150 200 250 300 350

30

40

50

60

70

80

EFFI

CIEN

CY (%

)

Efficiency, VOUT = 2.5V

8067 G01

VIN = 5VVIN = 12VVIN = 24VVIN = 36V

LOAD CURRENT (mA)0 50 100 150 200 250 300 350 400

40

50

60

70

80

EFFI

CIEN

CY (%

)

OUT

8067 G02


LOAD CURRENT (mA)0 100 200 300 400 500 600

40

50

60

70

80

90

EFFI

CIEN

CY (%

)

OUT

8067 G03


LOAD CURRENT (mA)0 100 200 300 400 500

45

55

65

75

85

EFFI

CIEN

CY (%

)

OUT

8067 G04


LOAD CURRENT (mA)0 50 100 150 200 250 300

45

55

65

75

85

EFFI

CIEN

CY (%

)

Efficiency, VOUT = 12V

8067 G05


VIN = 5VVIN = 12VVIN = 24V

LOAD CURRENT (mA)0 50 100 150 200 250

55

65

75

85

EFFI

CIEN

CY (%

)

OUT

8067 G06


LOAD CURRENT (mA)0 25 50 75 100 125

55

65

75

85

EFFI

CIEN

CY (%

)

OUT

8067 G07


LOAD CURRENT (mA)0 50 100 150 200 250 300 350

0

25

50

75

100

INPU

T CU

RREN

T (m

A)

VOUT = 2.5V

8067 G08


LOAD CURRENT (mA)0 100 200 300 400

0

25

50

75

100

125

INPU

T CU

RREN

T (m

A)

VOUT = 3.3V

8067 G09


LTM8067

5Rev. D



Input Current vs Load Current VOUT = 5V



Maximum Load Current vs VOUT


Input Current vs VIN, VOUT Shorted



LOAD CURRENT (mA)0 100 200 300 400 500 600

0

60

120

180

240

300

INPU

T CU

RREN

T (m

A)

OUT

8067 G10


LOAD CURRENT (mA)0 100 200 300 400 500

0

100

200

300

400

INPU

T CU

RREN

T (m

A)

OUT

8067 G11



LOAD CURRENT (mA)0 100 200 300

0

100

200

300

400

INPU

T CU

RREN

T (m

A)

VOUT = 12V

8067 G12



0

100

200

300

400

INPU

T CU

RREN

T (m

A)

VOUT = 15V

8067 G13



0

100

200

300

400

INPU

T CU

RREN

T (m

A)

OUT

8067 G14

VIN (V)0 10 20 30 40

0

50

100

150

200

250

INPU

T CU

RREN

T (m

A)

Input Current vs VIN, VOUT Shorted

8067 G15


VOUT (V)0 5 10 15 20 25

0

125

250

375

500

MAX

IMUM

LOA

D CU

RREN

T (m

A)

Maximum Load Current vs VOUT

8067 G16

Maximum Load Current vs VIN Maximum Load Current vs VIN

2.5VOUT3.3VOUT

VIN (V)0 10 20 30 40

100

200

300

400

MAX

IMUM

LOA

D CU

RREN

T (m

A)

IN

8067 G17

5VOUT8VOUT12VOUT

VIN (V)0 10 20 30 40

0

200

400

600

MAX

IMUM

LOA

D CU

RREN

T (m

A)


8067 G18


LTM8067

6Rev. D


Maximum Load Current vs VIN


Output Noise and Ripple DC2357A, 200mA Load Current

Frequency vs VOUT Load Current Stock DC2357A Demo Board


Derating, 2.5VOUT Derating, 3.3VOUT

VOUT1 (V)0 6 12 18 24

0

5

10

15

20

25

MIN

IMUM

LOA

D CU

RREN

T (m

A)

8067 G20

Minimum Load Current vs VOUT Over Full Output Voltage Range

0LFM AIRFLOW


AMBIENT TEMPERATURE (°C)25 50 75 100 125

0

100

200

300

400

MAX

IMUM

LOA

D CU

RREN

T (m

A)

OUT

8067 G23

0LFM AIRFLOW



0

100

200

300

400

MAX

IMUM

LOA

D CU

RREN

T (m

A)

Derating, 3.3VOUT

8067 G24

DATA0

HP461 150MHz AMPLIFIER AT 40dB GAIN

C5 = 470pF

2µs/DIV

10mV/DIV

8067 G21

5VIN12VIN24VIN

LOAD CURRENT (mA)0 100 200 300 400 500

150

250

350

450

SWIT

CHIN

G FR

EQUE

NCY

(kHz

)

Stock DC2357A Demo Board

8067 G22

24VOUT15VOUT

VIN (V)0 10 20 30 40

0

100

200

300

MAX

IMUM

LOA

D CU

RREN

T (m

A)


8067 G19


LTM8067

7Rev. D


TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, operating conditions are as in Table 1 (TA = 25°C).

Derating, 12VOUTDerating, 5VOUT

Derating, 15VOUT

Derating, 8VOUT0LFM AIRFLOW



0

150

300

450

600

MAX

IMUM

LOA

D CU

RREN

T (m

A)

Derating, 5VOUT

8067 G25

0LFM AIRFLOW



0

150

300

450

MAX

IMUM

LOA

D CU

RREN

T (m

A)

OUT

8067 G26

0LFM AIRFLOW

VIN = 5VVIN = 12VVIN = 24V, 36V


0

75

150

225

300

MAX

IMUM

LOA

D CU

RREN

T (m

A)

Derating, 12VOUT

8067 G27

0LFM AIRFLOW



0

75

150

225

300

MAX

IMUM

LOA

D CU

RREN

T (m

A)

OUT

8067 G28

0LFM AIRFLOW

VIN = 5VVIN = 12V, 24V


0

30

60

90

120

150

MAX

IMUM

LOA

D CU

RREN

T (m

A)

OUT

8067 G29

Derating, 24VOUT


LTM8067

8Rev. D


PIN FUNCTIONS

VOUT (Bank 1): VOUT and VOUTN comprise the isolated output of the LTM8067 flyback stage. Apply an external capacitor between VOUT and VOUTN. Do not allow VOUTN to exceed VOUT.

VOUTN (Bank 2): VOUTN is the return for VOUT. VOUT and VOUTN comprise the isolated output of the LTM8067. In most applications, the bulk of the heat flow out of the LTM8067 is through the GND and VOUTN pads, so the printed circuit design has a large impact on the thermal performance of the part. See the PCB Layout and Thermal Considerations sections for more details. Apply an exter-nal capacitor between VOUT and VOUTN.

GND (Bank 4): This is the primary side local ground of the LTM8067 primary. In most applications, the bulk of the heat flow out of the LTM8067 is through the GND and VOUTN pads, so the printed circuit design has a large impact on the thermal performance of the part. See the PCB Layout and Thermal Considerations sections for more details.

VIN (Bank 5): VIN supplies current to the LTM8067’s internal regulator and to the integrated power switch.

These pins must be locally bypassed with an external, low ESR capacitor.

RUN (Pin F3): A resistive divider connected to VIN and this pin programs the minimum voltage at which the LTM8067 will operate. Below 1.214V, the LTM8067 does not deliver power to the secondary. When RUN is less than 1.214V, the pin draws 2.5µA, allowing for a programmable hys-teresis. Do not allow a negative voltage (relative to GND) on this pin. Tie this pin to VIN if it is not used.

FB (Pins G7): Apply a resistor from this pin to GND to set the output voltage VOUTN relative to VOUTN, using the recommended value given in Table 1. If Table 1 does not list the desired VOUT value, the equation:

RFB = 37.415 VOUT

–0.955( )kΩmay be used to approximate the value. To the seasoned designer, this exponential equation may seem unusual. The equation is exponential due to nonlinear current sources that are used to temperature compensate the regulation. Do not drive this pin with an external power source.

PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.


LTM8067

9Rev. D


BLOCK DIAGRAM

VIN

RUN

FB

GND

0.1µF 1µF

VOUT

CURRENTMODE

CONTROLLER

VOUTN

8067 BD

•

•


LTM8067

10Rev. D


OPERATIONThe LTM8067 is a stand-alone isolated flyback switching DC/DC power supply that can deliver up to 450mA of output current at 5VOUT, 24VIN. This module provides a regulated output voltage programmable via one external resistor from 2.5V to 24V. The input voltage range of the LTM8067 is 3V to 40V. Given that the LTM8067 is a fly-back converter, the output current depends upon the input and output voltages, so make sure that the input voltage is high enough to support the desired output voltage and load current. The Typical Performance Characteristics section gives several graphs of the maximum load versus VIN for several output voltages.

A simplified block diagram is given. The LTM8067 con-tains a current mode controller, power switching element, power transformer, power Schottky diode and a modest amount of input and output capacitance.

The LTM8067 has a galvanic primary to secondary iso-lation rating of 2kVAC. For details please refer to the Isolation, Working Voltage and Safely Compliance sec-tion. The LTM8067 is a UL 60950 recognized component.

The RUN pin is used to turn on or off the LTM8067, dis-connecting the output and reducing the input current to 1μA or less.

The LTM8067 is a variable frequency device. For a given input and output voltage, the frequency increases from light load through moderate load, then begins to decrease until full load is reached. An example of this is shown in the Typical Performance Characteristics section. For light loads, the current through the internal transformer may be discontinuous.


LTM8067

11Rev. D


APPLICATIONS INFORMATIONFor most applications, the design process is straight for-ward, summarized as follows:

1. Look at Table 1 and find the row that has the desired input range and output voltage.

2. Apply the recommended CIN, COUT and RFB.

While these component combinations have been tested for proper operation, it is incumbent upon the user to verify proper operation over the intended system’s line, load and environmental conditions. Bear in mind that the maximum output current may be limited by junc-tion temperature, the relationship between the input and output voltage magnitude and polarity and other factors. Please refer to the graphs in the Typical Performance Characteristics section for guidance.

Capacitor Selection Considerations

The CIN and COUT capacitor values in Table 1 are the mini-mum recommended values for the associated operating conditions. Applying capacitor values below those indi-cated in Table 1 is not recommended, and may result in undesirable operation. Using larger values is generally

acceptable, and can yield improved dynamic response, if it is necessary. Again, it is incumbent upon the user to verify proper operation over the intended system’s line, load and environmental conditions.

Ceramic capacitors are small, robust and have very low ESR. However, not all ceramic capacitors are suitable. X5R and X7R types are stable over temperature and applied voltage and give dependable service. Other types, includ-ing Y5V and Z5U have very large temperature and voltage coefficients of capacitance. In an application circuit they may have only a small fraction of their nominal capaci-tance resulting in much higher output voltage ripple than expected.

A final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the LTM8067. A ceramic input capacitor combined with trace or cable inductance forms a high-Q (underdamped) tank circuit. If the LTM8067 circuit is plugged into a live supply, the input voltage can ring to much higher than its nominal value, possibly exceeding the device’s rating. This situa-tion is easily avoided; see the Hot-Plugging Safely section.

Table 1. Recommended Component Values for Specific VOUT Values (TA = 25°C)VIN VOUT CIN COUT RFB

3V to 40V 2.5V 2.2µF, 50V, 1206 100µF, 6.3V, 1210 15.4k

3V to 40V 3.3V 2.2µF, 50V, 1206 47µF, 6.3V, 1210 11.8k

3V to 40V 5V 2.2µF, 50V, 1206 22µF, 16V, 1210 8.25k

3V to 37V 8V 2.2µF, 50V, 1206 22µF, 16V, 1210 5.23k

3V to 33V 12V 4.7µF, 50V, 1206 10µF, 50V, 1210 3.48k

3V to 30V 15V 4.7µF, 50V, 1206 4.7µF, 25V, 1210 2.8k

3V to 27V 18V 4.7µF, 50V, 1206 4.7µF, 25V, 1210 2.37k

3V to 21V 24V 4.7µF, 50V, 1206 4.7µF, 25V, 1210 1.78k

Note: An input bulk capacitor is required.


LTM8067

12Rev. D


APPLICATIONS INFORMATIONIsolation, Working Voltage and Safety Compliance

The LTM8067 isolation is 100% hi-pot tested by tying all of the primary pins together, all of the secondary pins together and subjecting the two resultant circuits to a high voltage differential for one second. This establishes the isolation voltage rating of the LTM8067 component.

The isolation rating of the LTM8067 is not the same as the working or operational voltage that the application will experience. This is subject to the application’s power source, operating conditions, the industry where the end product is used and other factors that dictate design requirements such as the gap between copper planes, traces and component pins on the printed circuit board, as well as the type of connector that may be used. To maxi-mize the allowable working voltage, the LTM8067 has two columns of solder balls removed to facilitate the printed circuit board design. The ball to ball pitch is 1.27mm, and the typical ball diameter is 0.75mm. Accounting for the missing columns and the ball diameter, the printed circuit board may be designed for a metal-to-metal separation of up to 3.06mm. This may have to be reduced somewhat to allow for tolerances in solder mask or other printed circuit board design rules. For those situations where informa-tion about the spacing of LTM8067 internal circuitry is required, the minimum metal to metal separation of the primary and secondary is 1mm.

To reiterate, the manufacturer’s isolation voltage rating and the required working or operational voltage are often different numbers. In the case of the LTM8067, the iso-lation voltage rating is established by 100% hi-pot test-ing. The working or operational voltage is a function of the end product and its system level specifications. The actual required operational voltage is often smaller than the manufacturer’s isolation rating.

The LTM8067 is a UL recognized component under UL 60950, file number 464570. The UL 60950 insula-tion category of the LTM8067 transformer is Functional. Considering UL 60950 Table 2N and the gap distances stated above, 3.06mm external and 1mm internal, the

LTM8067 may be operated with up to 250V working voltage in a pollution degree 2 environment. The actual working voltage, insulation category, pollution degree and other critical parameters for the specific end application depend upon the actual environmental, application and safety compliance requirements. It is therefore up to the user to perform a safety and compliance review to ensure that the LTM8067 is suitable for the intended application.

Safety Rated Capacitors

Some applications require safety rated capacitors, which are high voltage capacitors that are specifically designed and rated for AC operation and high voltage surges. These capacitors are often certified to safety standards such as UL 60950, IEC 60950 and others. In the case of the LTM8067, a common application of a safety rated capaci-tor would be to connect it from GND to VOUTN. To provide maximum flexibility, the LTM8067 does not include any components between GND and VOUTN. Any safety capaci-tors must be added externally.

The specific capacitor and circuit configuration for any application depends upon the safety requirements of the system into which the LTM8067 is being designed. Table 2 provides a list of possible capacitors and their manufacturers. The application of a capacitor from GND to VOUTN may also reduce the high frequency output noise on the output.

Table 2. Safety Rated CapacitorsMANUFACTURER PART NUMBER DESCRIPTION

Murata Electronics

GA343DR7GD472KW01L 4700pF, 250V AC, X7R, 4.5mm × 3.2mm Capacitor

Johanson Dielectrics

302R29W471KV3E-****-SC 470pF, 250V AC, X7R, 4.5mm × 2mm Capacitor

Syfer Technology 1808JA250102JCTSP 100pF, 250V AC, C0G, 1808 Capacitor


LTM8067

13Rev. D


APPLICATIONS INFORMATIONPCB Layout

Most of the headaches associated with PCB layout have been alleviated or even eliminated by the high level of integration of the LTM8067. The LTM8067 is neverthe-less a switching power supply, and care must be taken to minimize electrical noise to ensure proper operation. Even with the high level of integration, you may fail to achieve specified operation with a haphazard or poor layout. See Figure 1 for a suggested layout. Ensure that the grounding and heat sinking are acceptable.

A few rules to keep in mind are:

1. Place the RFB resistor as close as possible to its respec-tive pin.

2. Place the CIN capacitor as close as possible to the VIN and GND connections of the LTM8067.

3. Place the COUT capacitor as close as possible to VOUT and VOUTN

4. Place the CIN and COUT capacitors such that their ground current flow directly adjacent to or underneath the LTM8067.

5. Connect all of the GND connections to as large a copper pour or plane area as possible on the top layer. Avoid breaking the ground connection between the external components and the LTM8067.

6. Use vias to connect the GND copper area to the board’s internal ground planes. Liberally distribute these GND vias to provide both a good ground connection and thermal path to the internal planes of the printed cir-cuit board. Pay attention to the location and density of the thermal vias in Figure 1. The LTM8067 can benefit from the heat sinking afforded by vias that connect to internal GND planes at these locations, due to their proximity to internal power handling components. The optimum number of thermal vias depends upon the printed circuit board design. For example, a board might use very small via holes. It should employ more thermal vias than a board that uses larger holes.

Figure 1. Layout Showing Suggested External Components, Planes and Thermal Vias

8067 F01

RUN

FB

LTM8067

COUT1

VOUTN

VIN

VOUT

CIN

THERMAL/INTERCONNECT VIAS


LTM8067

14Rev. D


APPLICATIONS INFORMATIONvoltage at the VIN pin of the LTM8067 can ring to more than twice the nominal input voltage, possibly exceeding the LTM8067’s rating and damaging the part. If the input supply is poorly controlled or the user will be plugging the LTM8067 into an energized supply, the input network should be designed to prevent this overshoot. This can be accomplished by installing a small resistor in series to VIN, but the most popular method of controlling input voltage overshoot is adding an electrolytic bulk capacitor to the VIN net. This capacitor’s relatively high equivalent series resistance damps the circuit and eliminates the voltage overshoot. The extra capacitor improves low frequency ripple filtering and can slightly improve the efficiency of the circuit, though it can be a large component in the circuit.

Thermal Considerations

The LTM8067 output current may need to be derated if it is required to operate in a high ambient temperature. The amount of current derating is dependent upon the input voltage, output power and ambient temperature. The temperature rise curves given in the Typical Performance Characteristics section can be used as a guide. These curves were generated by the LTM8067 mounted to a 58cm2 4-layer FR4 printed circuit board. Boards of other sizes and layer count can exhibit different thermal behavior, so it is incumbent upon the user to verify proper operation over the intended system’s line, load and envi-ronmental operating conditions.

For increased accuracy and fidelity to the actual applica-tion, many designers use FEA to predict thermal perfor-mance. To that end, the Pin Configuration section of the data sheet typically gives four thermal coefficients:

θJA: Thermal resistance from junction to ambient

θJCbottom: Thermal resistance from junction to the bot-tom of the product case

θJCtop: Thermal resistance from junction to top of the product case

θJCboard: Thermal resistance from junction to the printed circuit board.

While the meaning of each of these coefficients may seem to be intuitive, JEDEC has defined each to avoid

Minimum Load

Due to the nature of the flyback regulator in general, and the LTM8067 control scheme specifically, the LTM8067 requires a minimum load for proper operation. Otherwise, the output may go out of regulation if the load is too light. The most common way to address this is to place a resistor across the output. The Minimum Load Current vs VOUT Over Full Output Voltage Range graph in the Typical Performance Characteristics section may be used as a guide in selecting the resistor. Note that this graph describes room temperature operation. If the end application operates at a colder temperature, the mini-mum load requirement may be higher and the minimum load condition must be characterized for the lowest operating temperature.

If it is impractical to place a resistive load permanently across the output, a resistor and Zener diode may be used instead, as shown in Figure 2. While the minimum load resistor mentioned in the prior paragraph will always draw current while the LTM8067 output is powered, the series resistor-Zener diode combination will only draw current if the output is too high. When using this circuit, take care to ensure that the characteristics of the Zener diode are appro-priate for the intended application’s temperature range.

Figure 2. Use a Resistor and Zener Diode to Meet the Minimum Load Requirement

Hot-Plugging Safely

The small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitor of the LTM8067. However, these capaci-tors can cause problems if the LTM8067 is plugged into a live supply (see Analog Devices Application Note 88 for a complete discussion). The low loss ceramic capacitor combined with stray inductance in series with the power source forms an underdamped tank circuit, and the

LTM8067

VOUTP

VOUTN

8067 F02

https://www.analog.com/LTM8067?doc=LTM8067.pdfhttps://www.analog.comhttps://www.analog.com/media/en/technical-documentation/application-notes/an88f.pdf?doc=LTM8067.pdf

LTM8067

15Rev. D


APPLICATIONS INFORMATIONconfusion and inconsistency. These definitions are given in JESD 51-12, and are quoted or paraphrased as follows:

θJA is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as still air although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition.

θJCbottom is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. In the typical µModule con-verter, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test condi-tions don’t generally match the user’s application.

θJCtop is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule converter are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junc-tion to the top of the part. As in the case of θJCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application.

θJCboard is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule converter and into the board, and is really the

sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two-sided, two-layer board. This board is described in JESD 51-9.

Given these definitions, it should now be apparent that none of these thermal coefficients reflects an actual physical oper-ating condition of a µModule converter. Thus, none of them can be individually used to accurately predict the thermal performance of the product. Likewise, it would be inappro-priate to attempt to use any one coefficient to correlate to the junction temperature vs load graphs given in the product’s data sheet. The only appropriate way to use the coefficients is when running a detailed thermal analysis, such as FEA, which considers all of the thermal resistances simultaneously.

A graphical representation of these thermal resistances is given in Figure 3.

The blue resistances are contained within the µModule converter, and the green are outside.

The die temperature of the LTM8067 must be lower than the maximum rating of 125°C, so care should be taken in the layout of the circuit to ensure good heat sinking of the LTM8067. The bulk of the heat flow out of the LTM8067 is through the bottom of the module and the BGA pads into the printed circuit board. Consequently a poor printed cir-cuit board design can cause excessive heating, resulting in impaired performance or reliability. Please refer to the PCB Layout section for printed circuit board design suggestions.

Figure 3. Approximate Thermal Model of LTM8067

8067 F03

µMODULE DEVICE

JUNCTION-TO-CASE (TOP)RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

CASE (TOP)-TO-AMBIENTRESISTANCE

BOARD-TO-AMBIENTRESISTANCE

JUNCTION-TO-CASE(BOTTOM) RESISTANCE

JUNCTION AMBIENT

CASE (BOTTOM)-TO-BOARDRESISTANCE


LTM8067

16Rev. D


APPLICATIONS INFORMATION

–15V Inverting Regulator

12V Flyback Converter Maximum Load Current vs VIN

Maximum Load Current vs VIN

3.48k

4.7µF10µF

VIN

GND

VOUT

VOUTN

RUN

FB

VIN12V

VOUT12V

LTM8067

8067 TA03a

VIN (V)0 10 20 30 40

0

100

200

300

MAX

IMUM

LOA

D CU

RREN

T (m

A)

OUT

8067 TA03b

2.8k

4.7µF4.7µF

VIN

GND

VOUT

VOUTN

RUN

FB

VIN5V TO 31V

VOUT–15V

LTM8067

8067 TA04a

VIN (V)0 10 20 30 40

0

100

200

300

MAX

IMUM

LOA

D CU

RREN

T (m

A)

OUT

8067 TA04b


LTM8067

17Rev. D


PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTIONA1 VOUTN B1 VOUTN C1 – D1 – E1 GND F1 – G1 VIN H1 VINA2 VOUTN B2 VOUTN C2 – D2 – E2 GND F2 – G2 VIN H2 VINA3 VOUTN B3 VOUTN C3 – D3 – E3 GND F3 RUN G3 – H3 –A4 VOUTN B4 VOUTN C4 – D4 – E4 GND F4 GND G4 GND H4 GNDA5 VOUTN B5 VOUTN C5 – D5 – E5 GND F5 GND G5 GND H5 GNDA6 VOUT B6 VOUT C6 – D6 – E6 GND F6 GND G6 GND H6 GNDA7 VOUT B7 VOUT C7 – D7 – E7 GND F7 GND G7 FB H7 GND

Pin Assignment Table(Arranged by Pin Number)

PACKAGE DESCRIPTION

PACKAGE PHOTO


LTM8067

18Rev. D


PACKAGE DESCRIPTION

PACK

AGE

TOP

VIEW

4

PIN

“A1”

CORN

ER

YX

aaa

Z

aaa

Z

DETA

IL A

PACK

AGE

BOTT

OM V

IEW

3

SEE

NOTE

S

HGFEDCBA

12

34

56

7

PIN

1

BGA

38 0

517

REV

B

TRAY

PIN

1BE

VEL

PACK

AGE

IN T

RAY

LOAD

ING

ORIE

NTAT

ION

COM

PONE

NTPI

N “A

1”NOT

ES:

1. D

IMEN

SION

ING

AND

TOLE

RANC

ING

PER

ASM

E Y1

4.5M

-199

4

2. A

LL D

IMEN

SION

S AR

E IN

MIL

LIM

ETER

S

BAL

L DE

SIGN

ATIO

N PE

R JE

SD M

S-02

8 AN

D JE

P95

43

DETA

ILS

OF P

IN #

1 ID

ENTI

FIER

ARE

OPT

IONA

L,BU

T M

UST

BE L

OCAT

ED W

ITHI

N TH

E ZO

NE IN

DICA

TED.

THE

PIN

#1 ID

ENTI

FIER

MAY

BE

EITH

ER A

MOL

D OR

M

ARKE

D FE

ATUR

E

DETA

IL A

Øb (3

8 PL

ACES

)

A

DETA

IL B

PACK

AGE

SIDE

VIE

W

MX

YZ

ddd

MZ

eee

A2

D

E

e

b

F

G

SUGG

ESTE

D PC

B LA

YOUT

TOP

VIEW

0.00

00.

635

1.90

5

0.63

5

3.17

5

1.90

5

4.44

5

3.17

5

4.44

5

3.810

2.540

1.270

3.810

2.540

1.270

0.3175

0.31750.000

4.12

75

4.76

25

LTM

XXXX

XXµM

odul

e

BGA

Pack

age

38-L

ead

(11.

25m

m ×

9.0

0mm

× 4

.92m

m)

(Ref

eren

ce L

TC D

WG

# 05

-08-

1925

Rev

B)

6

SEE

NOTE

S

SYM

BOL

A A1 A2 b b1 D E e F G H1 H2 aaa

bbb

ccc

ddd

eee

MIN

4.72

0.50

4.22

0.60

0.60

0.27

3.95

NOM

4.92

0.60

4.32

0.75

0.63

11.2

59.

01.

278.

897.

620.

324.

00

MAX

5.12

0.70

4.42

0.90

0.66

0.37

4.05

0.15

0.10

0.20

0.30

0.15

TOTA

L NU

MBE

R OF

BAL

LS: 3

8

DIM

ENSI

ONS

NOTE

S

BALL

HT

BALL

DIM

ENSI

ONPA

D DI

MEN

SION

SUBS

TRAT

E TH

KM

OLD

CAP

HT

Z

DETA

IL B

SUBS

TRAT

E

A1

ccc

Z

Z

// bbb Z

H2H1

b1M

OLD

CAP

5. P

RIM

ARY

DATU

M -Z

- IS

SEAT

ING

PLAN

E

6PA

CKAG

E RO

W A

ND C

OLUM

N LA

BELI

NG M

AY V

ARY

AMON

G µM

odul

e PR

ODUC

TS. R

EVIE

W E

ACH

PACK

AGE

LAYO

UT C

AREF

ULLY

!


LTM8067

19Rev. D


Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORYREV DATE DESCRIPTION PAGE NUMBER

A 05/16 Corrected symbol of internal switch in block diagram from NPN transistor to N-channel MOSFET 9

B 11/16 Corrected VOUT on Maximum Load Current vs VIN from 12VOUT to 24VOUT and from 15VOUT to 12VOUTCorrected minimum metal to metal space from 0.75mm to 1mmUpdated the Related Parts Table

61220

C 07/17 Added Minimum Load section 14

D 11/20 Minimum VIN changed from 2.8V to 3V Updated Derating graph Updated text about operating frequency

1, 3, 10, 11 6, 7 10


LTM8067

20Rev. D

For more information www.analog.com © ANALOG DEVICES, INC. 2016-2020

11/20www.analog.com

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PART NUMBER DESCRIPTION COMMENTS

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DESIGN RESOURCES

SUBJECT DESCRIPTION

µModule Design and Manufacturing Resources Design: • Selector Guides • Demo Boards and Gerber Files • Free Simulation Tools

Manufacturing: • Quick Start Guide • PCB Design, Assembly and Manufacturing Guidelines • Package and Board Level Reliability

µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet.2. Search using the Quick Power Search parametric table.

Digital Power System Management Analog Devices’ family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging.

https://www.analog.com/LTM8067?doc=LTM8067.pdfhttps://www.analog.comhttps://www.analog.comhttps://www.analog.com/LTM8068?doc=LTM8067.pdfhttps://www.analog.com/LTM8047?doc=LTM8067.pdfhttps://www.analog.com/LTM8048?doc=LTM8067.pdfhttps://www.analog.com/LTM8045?doc=LTM8067.pdfhttps://www.analog.com/LT8300?doc=LTM8067.pdfhttps://www.analog.com/LT8301?doc=LTM8067.pdfhttps://www.analog.com/LT8302?doc=LTM8067.pdfhttps://www.analog.com/LTM8049?doc=LTM8067.pdfhttps://www.analog.com/en/products/landing-pages/001/umodule-design-manufacturing-resources.htmlhttps://www.analog.com/en/parametricsearch/11524https://www.analog.com/en/products/monitor-control-protection/digital-power-system-management.html

FeaturesApplicationsTypical Application DescriptionAbsolute Maximum RatingsOrder InformationPin ConfigurationElectrical CharacteristicsTypical Performance CharacteristicsPin FunctionsBlock DiagramApplications InformationPackage DescriptionPackage PhotoPackage DescriptionRevision HistoryTypical ApplicationDesign ResourcesRelated Parts

ltm8067 (rev. d) · 2020. 11. 23. · mimm ld cnt deratn v t 8067 7 0lm il vin v vin v vin 4v vin...

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