lte physical layer
DESCRIPTION
presentation for implementation of lte physical layer it contatins a blocks and how each block is ?it may be also a good overview on revolution of mobile communication 2g, 3g, 4g.the physical layer is implemented using fpga and vhdlTRANSCRIPT
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LTE Physical Layer
:Supervised By Prof
AHMED YAHIA04/17/2023
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Prepared by
• Ahmed Abdel-kader Mahmoud• Ahmed Mahmoud Abdel-rahman• Sabry Abdullah Mohamed• Mahmoud Mohsen Mohamed• Hesham Mohamed Refaat• Yaser Mohamd Osman
04/17/2023
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Acknowledgement
Any attempt at any level cannot be satisfactorily completed without the will of God and the support and guidance of learned people. We would like to express our immense gratitude to Dr. Ahmed Yahia for his constant support and motivation that has encouraged us to come up with this project.
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CONTENTS Introduction. Mobile Communication Evolution. LTE “Long Term Evolution”. Physical Layer Implementation. VHDL. Simulation. Future work. Conclusion.
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Introduction To Mobile Communication
Cellular concept. Access techniques. Switching techniques. 1st generation. Why 2nd generation ?
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Cellular Concept
• Frequency reuse• Reuse distance• Increasing capacity• Clusters
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Cell TypesCell classifications:
Macro cell……. ( 1 Km: 35km)
Micro cell……..(100m –to- 1Km)
Pico cell…….....(10m)
Umbrella cell….(random)
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Multiple Access TechniquesCDMATDMA
FDMAOFDMA
ff
f
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Switching techniques:
Circuit Switching Packet Switching
Channel for one user Channel for multiple users
One path Multiple path
Fixed bit rate Variable bit rat
Billing by time Billing by volume
Used for real time application Used for data transfer
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1st generation features:
Introduced to commercial uses in early of 1979 & late of 1980
Analog technology
Not compatible system : such as American system (AMPS) uses 800 MHZ and Germany system (c450) used 450 MHZ so no roaming• Access technique (FDMA)• Duplex technique (FDD)
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Mobile Communication Evolutions
GSM
GPRS
EDGEUMTS
LTE
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GSMGlobal System For Mobile Communication
Features. Frequency band. Network architecture.
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Features:
Access techniques:
FDMA / TDMA.FDD.
Operating frequency: (900 –
1800 – 1900) MHz .
8 time slot / carrier.
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Features:
Cellular concept: frequency reuse. Circuit switching.
Data rate: 9.6 Kb/s.
Hard handover
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GSM frequency band:
890 MHz 915 MHz 935MHz 960 MHz
Uplink Guard band Downlink
Channel B.W= 200 KHz
carriers = 25 MHz / 200 KHz = 125 carrier
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GSM Spectrum Allocation :
CH 1 54321 6 70 0 1
Time
CH 3 54321 6 70 0 1
CH 2 54321 6 70 0 1
CH 124 54321 6 70 0 1
Time slot = 0.577 ms Frame duration = 0.577 ms * 8 = 4.616 ms
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Network Architecture GSM
GMSC
MSC
EIR AUC VLR HLR
BSC BSC
Other PLMNs
BTS
BTS
BTS
BTS
IWFSMC
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GPRSGeneral Packet Radio Services:
Features. New services. Network Architecture. Network service area.
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:Features
Various new coding schemes with transmission rates up to 21.4 Kb/s
per physical channel.
Theoretical transmission rate up to
171.2 Kb/s.
Packet & circuit switching.
GPRS enables point-to-point transmission and volume
dependent charging.
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Features
Access techniques :
TDMA/FDMA.
Duplex techniques :
FDD.
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Services offered
“Always on” internet access. Multimedia messaging service (MMS). Internet applications for smart devices through
wireless application protocol (WAP). Point-to-point (PTP) service : inter-networking
with the internet (IP).
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Network Architecture Of GPRS
SGSN
GMSC
MSC
EIR
AUC
VLR
HLR
GGSN
Backbone Network
IP
IPNetwork
BTS/BTS/
BSC/PCU
Other PLMNs
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CDMACode Division Multiple Access
Types Of Spread Spectrum Power Control
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Types Of Spread Spectrum
Direct sequence spread spectrumFrequency hopping spread spectrumTime hopping spread spectrum
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Direct sequence spread spectrum
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UMTSUniversal Mobile Telecommunication System
Features.Frequency band.Network architecture.
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UMTS Features
Wide band CDMA
Frequency band 2100 MHz
Channel bandwidth 5MHz
Chip rate 3.84 Mc/s
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UMTS Features
Channelization codes (4x4 512 x512)
OVSF codes
Rake receiver Soft and softer hand over
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UMTS Features
Inter system hand over
Macro diversity
Variable rate (AMR)
Vo-coder
Closed loop power control
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Network Architecture UMTS
SGSN
GMSC
MSC
EIR
AUC
VLR
HLR
GGSN
IPNetwork
Node BNode BRNC
CGF Billing System
BTSBTSBSC
Node BNode BRNC
GSM BSS
UTRAN Core Network
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Long Term Evolution
LTE Specifications Frequency BandLTE TargetsLTE Network ArchitectureOrthogonal Frequency Division Multiplexing
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LTE Specifications
Digital technology
Cellular concept
OFDMA
Downlink.
SC-FDMA Uplink.
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LTE Specifications
VOIP Technology. Frequency Band 2600MHz
Channel Bandwidth Up To
20MHz
MIMO Technology (2 x 2) or (4 x 4)
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LTE Specifications
Packet Switching.
IP V6
FDD or TDD
New applications
“IP-TV, video streaming, HD
video”
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LTE Frequency Band
• Channel bandwidth 5MHZ to 20 MHZ • Bit Rate 100 Mbps up to 1 Gbps • Sub carrier spacing 15 KHZ
2500MHz 2570MHz 2620MHz 2690MHz
FDD Uplink TDD band FDD Downlink
15 KHZ
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LTE Network Architecture
External networks:Operator services (e.g. IMS) and internet
Services
E-UTRAN
eNode BeNode B
HSSPCRF P-GW
S-GW MMEEPC
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LTE Targets Increasing User Throughput
Increasing Spectral Efficiency
Increasing Number Of Subcarrier15 KHZ
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LTE TargetsDecreasing Latency Factor
MSC
BSC
BTS
MSC
BSC
BTS
MSC
RNC
Node B
MSC
RNC
Node B
S-GW
eNode B
S-GW
eNode B
GSM UMTS LTE
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Basic channel access modesTransmitAntennas
ReceiveAntennas
SISO
The Radio Channel
MISO
Single Input Single Output
Multiple Input Single Output
(Transmit diversity)
ReceiveAntennas
TransmitAntennas
MIMO
The Radio Channel
SIMO
Single Input Multiple Output
(Receive diversity)
Multiple Input Multiple Output(Multiple data streams)
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MIMO
• Transmitting multiple data streams in the same space and time used to be called interference!
• So how does MIMO work?1. MIMO capacity gains come from taking advantage of
spatial diversity in the radio channel
2. The performance can be optimized using precoding
Multiple Input Multiple Output(Multiple data streams)
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OFDMAOrthogonal Frequency Division Multiplexing
OFDM is a spectrally efficient modulation technique ,It is conveniently implemented using IFFT and FFT operations
Bandwidth W being divided into K sub-carriers, leading to carrier spacing Δf, satisfying Δf =W/K
Symbol duration T satisfying T = 1/Δf
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SC-FDMA
For the LTE uplink, a different concept is used for the access technique. Although still using a form of OFDMA technology, the implementation is called Single Carrier Frequency Division Multiple Access (SC-FDMA).One of the key parameters that affects all mobiles is that of battery life. Even though battery performance is improving all the time, it is still necessary to ensure that the mobiles use as little battery power as possible
Sc-Fdma
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Multi Path Propgation
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Cyclic prefix insertion
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FAST FOUREER TRANSFORM
• X(m)
• For An 8-point DFT We Would To Have To Perform complex Multiplication i.e. 64 complex Multiplication
• For An 8-point FFT We Would To Have To Perform complex Multiplication i.e. 12 complex Multiplication
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4 minutes
30 seconds
48 seconds
1 second
8 seconds
LTE100
Mbps
HSDPA
WCDMA
EDGE
GPRS
Mobile technology competition
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Data format
CP Insertion
S/P IFFTConvolutional Encoder
Channel interface
Channel
Channelinterface
Interleaver
Channel coding Modules
p/s
s/p
CP REMOVa
FFTp/sViterbiDecoder
DE- Interleaver
Data deformat
OFDM Tx And Rx
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DATA FORMATION
10110100
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Data format
CP Insertion
S/P IFFTConvolutional Encoder
Channel interface
Channel
Channelinterface
Interleaver
Channel coding Modules
p/s
s/p
CP REMOVa
FFTp/sViterbiDecoder
DE- Interleaver
Data deformat
OFDM Tx And Rx
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Convolutional Encoder
0 0
+
+
Input Output
1
1
c1
c2
1
1 1
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1 0
+
+
Input Output
1
0
c1
c2
0
101 1
Convolutional Encoder
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0 1
+
+
Input Output
0
0
c1
c2
1
101 100
Convolutional Encoder
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1 0
+
+
Input Output
0
1
c1
c2
1
101 100010
Convolutional Encoder
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1 1
+
+
Input Output
1
0
c1
c2
0
101 10001010
Convolutional Encoder
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0 1
+
+
Input Output
0
0
c1
c2
1
101 100010100 0
Convolutional Encoder
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1 0
+
+
Input Output
1
0
c1
c2
0
101 100010100 001
Convolutional Encoder
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0 1
+
+
Input Output
1
1
c1
c2
0
101 100010100 00111000 000000000 00000
Convolutional Encoder
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Data format
CP Insertion
S/P IFFTConvolutional Encoder
Channel interface
Channel
Channelinterface
Interleaver
Channel coding Modules
p/s
s/p
CP REMOVa
FFTp/sViterbiDecoder
DE- Interleaver
Data deformat
OFDM Tx And Rx
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INTERLAEVER
101 1
00
1
10
000
0111
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INTERLAEVER
101 1
00
1
10
000
0111
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OFDM Transmitter
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Data format
Convolutional Encoder
Channel interface
Channel
Channelinterface
Interleaver
Channel coding Modules
s/p
CP REMOVa
FFTp/sViterbiDecoder
DE- Interleaver
Data deformat
OFDM Tx And Rx
CP Insertion
S/P IFFT
p/s
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OFDM Transmitter
CP Insertio
n
S/P IFFTS/P
p/s
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Data format
CP Insertion
S/P IFFTConvolutional Encoder
Channel interface
Channel
Channelinterface
Interleaver
Channel coding Modules
p/s
s/p
CP REMOVa
FFTp/sViterbiDecoder
DE- Interleaver
Data deformat
OFDM Tx And Rx
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OFDM Receiver
CP removals/p
FFT S/P
1
0
1
1
0
01
0
101 10010
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Data format
CP Insertion
S/P IFFTConvolutional Encoder
Channel interface
Channel
Channelinterface
Interleaver
Channel coding Modules
p/s
s/p
CP REMOVa
FFTp/sViterbiDecoder
DE- Interleaver
Data deformat
OFDM Tx And Rx
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DE-INTERLEAVER
101 1
00
1
10
000
0111
1010
1111
0111
101 0
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Data format
CP Insertion
S/P IFFTConvolutional Encoder
Channel interface
Channel
Channelinterface
Interleaver
Channel coding Modules
p/s
s/p
CP REMOVa
FFTp/sViterbiDecoder
DE- Interleaver
Data deformat
OFDM Tx And Rx
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VITERBI DECODER
00 00 00
a (00)
b (01)
c (10)
d (11)
11 11 11
01
10 10
10
01 01
11
00
00 00 00 00 00
11 11 11
01 01 01
10 10 10
10 10 10
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11 11 11
00 00 00
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11010010100011 01
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Viterbi decoder with error
00 00 00
a (00)
b (01)
c (10)
d (11)
11 11 11
01
10 10
10
01 01
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00 00 00 00 00
11 11 11
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10 10 10
10 10 10
01 01 01
11 11 11
00 00 00
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11010110100010 01
1
1
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1 11 10 0 0 0
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Data format
CP Insertion
S/P IFFTConvolutional Encoder
Channel interface
Channel
Channelinterface
Interleaver
Channel coding Modules
p/s
s/p
CP REMOVa
FFTp/sViterbiDecoder
DE- Interleaver
Data deformat
OFDM Tx And Rx
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DATA DE-FORMATION
1011010000000000
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VHDLVHSIC Hardware
Description Language
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VHDL’s Organization
• The basic VHDL model is known as a Design Entity and has two parts• Interface - denoted by keyword entity • defines I/O signals for the model
• Body - denoted by keyword architecture• describes how the model works
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VHDL (Xor) Exampleentity XOR2_OP is -- Input/Output ports port (A, B : in BIT; Z : out BIT);end XOR2_OP;
architecture EXD of XOR2_OP is -- declarations go before beginbegin Z <= A xor B;end EXD
Interface
Body
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Interleaver code
entity interleaver is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC);
end inter;
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Architecture partarchitecture Behavioral of interleaver is
signal temp1 : std_logic_vector (3 downto 0);
signal temp2 : std_logic_vector (3 downto 0);
signal temp3 : std_logic_vector (3 downto 0);
signal temp4 : std_logic_vector (3 downto 0);
signal x1 : std_logic_vector (3 downto 0);
signal x2 : std_logic_vector (3 downto 0);
signal x3 : std_logic_vector (3 downto 0);
signal x4 :std_logic_vector (3 downto 0);
signal y : std_logic_vector (15 downto 0);
signal count1 : std_logic_vector (4 downto 0);
signal count2 : std_logic_vector (4 downto 0);
temp1
temp2
temp3
temp4
x1 x2 x3 x4
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Architecture part
begin
process (clk,rst,input)
begin
if rst = '1' then
output <= '0';
count1 <= "00000";
count2 <= "00000";
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Architecture partelsif rising_edge (clk) then
if count1 < "10001" then
temp1 <= input & temp1 (3 downto 1);
temp2 <= temp1(0) & temp2 (3 downto 1);
temp3 <= temp2(0) & temp3 (3 downto 1);
temp4 <= temp3(0) & temp4 (3 downto 1);
x1 <= temp1(0) & temp2(0) & temp3(0) & temp4(0);
x2 <= temp1(1) & temp2(1) & temp3(1) & temp4(1);
x3 <= temp1(2) & temp2(2) & temp3(2) & temp4(2);
x4 <= temp1(3) & temp2(3) & temp3(3) & temp4(3);
count1 <= count1 + 1 ;
end if;
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Architecture partif count1 = "10001" then
y <= x1 & x2 & x3 & x4 ;
count1 <= "00000";
end if;
if count2 < "10001" then
output <= y(0);
y <= '0' & y (15 downto 1);
count2 <= count2 + 1 ;
else
count2 <= "00000";
end if;
end if;
end process;
end Behavioral;
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•Data Format block behave as parallel in serial out (PISO) register which converts the input with parallel form to the output with serial form.• It adds tail of Zeros to the input data.• It generates the required signals for convolutional encoder.
Data formation PISO
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Data formation
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Parallel to serial module
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Convolutional encoder• We have used R = ½ , K=3.• It is used to encode each 1 bit into 2 bits for error detection
and correction purposes.
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Convolutional encoder simulation
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InterleaverRandomizes The Sequence of Data By Storing It Row by Row & Retrieving It Column by Column For Error Isolation
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Interleaver Simulation
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Data deformation SIPO
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serial to Parallel module
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Data de-formation
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FPGA
• Xilinx XC3S500E Spartan-3E FPGA• • Up to 232 user-I/O pins• • Over 10,000 logic cells• 2-line,16-character LCD screen• 50MHz clock oscillator
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Future work Suggestions
Channel Estimation Improvement
The next step in improvement would be use a channel estimator that utilizes channel statistics,which known as minimum mean-squared error estimation (MMSE).
Developing other modules
For the future works, it is suggested to develop other modules such as advanced error correction teqniques, QAM or QPSK modulation RF part. These modules will make a complete set of OFDM system for transmitter and receiver.
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Conculosion• Presenting the way for people in the past to communicate• Presenting the creation of mobile phone starting from the 2nd Generation which
is called Global system for mobile communication (GSM)• The progresses that happened to make it better by using the General Packet
Radio Service (GPRS).• Presenting the birth of the 3rd Generation that enables all subscribers to send
and receive lager amount of data than GSM including pictures, faxes, e-mails and internet browsing.
• The real revolution of mobile communications occurs by the invention of the CDMA in USA and the Universal Mobile Telecommunication System (UMTS) in Europe.
• Enabling all subscribers to hold video calls and support them by offering larger capacity for data rate and multimedia messages.
• Finally, Presenting the 4th generation including LTE, and UMB increases the transmission rate with much higher quality.
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Thanks all
To Parctical Part….