lsi verilator eda linux hdl verilator - shimizu lab./tokai...
TRANSCRIPT
LSIEDA Linux
������� ��� � ������������������� ��� �� �� !��#" $ %�&('*)�+-, .0/1���2�
RTL 3-465�7 869 :;5�< = > ?�52@ A#3-465 BDCE�F G 3-4IHKJ6L;M N�O-PRQ JTS�U�V + A�L;W >X1Y�ZEDA Linux J�[�5 SFL 5 Verilog 5 VHDL\ L^]�_ U�V + A�`�C /ba+�c�d0+#e Lgf�h X 5i�j�k�l�m 3-4�9 :�BDC E�F Gon ?pHKJ6LrqtsIuM N Z EDA Linux
v w x y z { |}�~T�6� �����
�T��� � �
���*� �(�r�I� �
VDEC Jb� � X1Y TEG ���#��L;� � X1Y�� � Z� /2�K�6, B +-a [ 31 �6Jb� 100MHz Jbs � Z� �Iu0�-] X1Y �*�g@ e [ ROHM0.35 m
EDA Linux [�¡�¢*£�¤�¥6¦*V + A�5� &0+ G � E A�§�¨�©�ª�« e G L;W > X 5 CD ¬ + G ¤�¥6¦ Live Linux P X®¯ ? X1Y�ZK°�± J m FPGA 3-465 ��c�² C /(� ©�] \ u�³-_ Y ,be ª ´ LSI W >�µ�¶�· ¸6J-¹-U Z
SFL º�» RTL ¼r½�¾*¿�À�Á ���p� � �  ¼�½ ÃRÄVHDL Å�Æ�º �(�r�I� �oÇ�È Â�É6Ê Ã(Ë-ÌÍrÎTÏ
SFL º�¼r½ Ã(Ë TEG�T�p� � �pÂbÐ�Ñ Ò2Ó ËÔ�Õ Ì�Ö 14,000
�®×�Ø ��ÙIÚ º�Ä#ÛTÜ Â�Ý6Þ Ã(Ë�Ì14}6~I�6� �ß���
(AND,OR,NOT, etc)4 à � �âá���Ø Ú (
}�~T�6� �ß��� »�ã�º Ý6Þ )31 ä å Ø æ#ç�è �(� ÚAES érê SBOX À�Á ( ë Ê���� �ß��� º Ý6Þ )RS-232C ì Ø �1í�I×2 î ír� îbï6ð ×T�bñ À�Á
ò · ¸�L^]�_ 3-4 X1Y#ó2ô L^õö X1Y t ���#�6P÷-+ ø ZFPGA µ�¶�§ ASIC µ�¶Tu�]�_ U6O-PRQ JTS�U Z
SFLsource
VHDLbehaviour
sfl2vh
xsch
adder.sfl
adder.vhdl
LSI structureVHDL
sxlibdataflow lib
vasy VHDLdata flow
adder.vbe
boom
boog
VHDLstructure
adder.vst
dataflow optimizer
logic synthesizer
behaviour converter
ocp
nero
coresymbolic layout
adder.ap
circuit view
cell placer
router
ring lsi symboliclayout
chip.ap
s2r
lsi physicallayout
chip.cifchip.vstchip.rin
sxlibcell library
Alliance tools
Alliance library
cmosdesign rule
Verilog - C++ ù�ú ¾Tû�ü#ý � î �p��þ � �(� ���ÿ � è�� � �(��è �bØ�Â������ ü Verilator� � Ã(Ä SFL � ������º���� è�� � �;��è �2Ø��ÿ � Â��*Þ�� ü�� ������ Ì
SFL SourceC++ basetest script
TranslatedVerilog source
TranslatedC++ source
Executable
sfl2vl
verilator
gcc
gcc
Logic and Simulation entry
� � ! " # $
% & ' ( $ % ) !* � +
sfl2vl , Verilator - . / 0 1 2 3 4 5 1 6 7HDL 8�9;:=<?> Verilator @BA�C DFE�G H�I=JK<?G L�9FM�NPO�QSR / T�U�@WV XYE[Z Verilator \]O_^�`=ab�c�d�e fSg=h
Verilog iY<�j�8k< lnm?o p sfl2vl qBOYr�sutwvSx�yzZT�U�{ua}|�~�� IP O MP3 �=< l����Y�S��9[8k<?�Pq i8086 �u� ���B� ���P@W�?C DFE[Z
100Hz
1KHz
10KHz
100KHz
1MHz
10MHz
100MHz
Speed
Turn Around Time0.1Hz
1Hz
10Hz � ��������
�Gate level
HDL level
Cycle level
Emulator
Prototype
�����¡ £¢¥¤¦¨§ª© ¬«�®¥¯¡°¥±³² ´¶µ¶·¹¸»º½¼¿¾ÁÀÂÁÃÅÄ(C/C++ Æ )
Real
Virtu
al
ÇÉÈ1 Ê
10 Ê100 Ê
17 Ë2.8 ÌÎÍ
28 Ì�Í11.6 Ï
116 Ï3.2 Ð
ѶÒÔÓ�Õ ¸»º½¼
ÖØ×ÚÙÜÛ;ÝÞÖß×ØàØáâäã¥å¨æèçäéÉêÎëíìäîðï¥ñ�òôó"2002 õ¨öø÷¥ù¨ú¨û LSI üÉý - ÷ªùèú¨ûªüèý�þ (2)-" ÿ�� �������� � �� � �� ���������������� �"!�#%$�&
SFL '�(�)+*�(-,/.�02123546"7�8Verilog '9(�):*�(-,/;<2=�>�?�@�A�B5C�D
0215324 6�7�8 Verilog '9( )*�(E,/. C++ FHG IKJ SystemC; <5=�>�?�@5A�B�C�D
LNMPORQEDA Linux SUTWVYX[Z]\_^a` http://www.ip-arch.jp/ bc`[d_e_fNgihkj�lUm
HDL nporqisutwvyxuzr{�|y}~y�]���N�r� q-s
FreeDOS �w�u���������
i8086 �9�9�9������������"���������������� "¡9¢�£¥¤�¦ §�¨ IcarusVerilog
[S]Verilator
[S] ©Kª�«¬¥�®�¯¥°¥±
for ²³�´%µ¥¶K·¹¸¥º�»
295.030
76.01
1079.36
2.860
3.31
48.76
103.2
22.9
22.1
FreeDOS ¼�½�¾ ¿ 14400 ¿ 500 28.8
FreeDOS ÀÂÁ�ÃÅÄÇÆÉÈÉÊËÁÇÄ�ÌÎÍÐÏÒÑÔÓÂÕ Icarus VerilogÖÇ×ÎØ4 ÙÒÚÔÛ 1.1KHz ÜÒÝ ÖÇÞàßÎáÔâ ÏÐã�äËÛ Verilator
ÖÇ×Ø8 åàÛ 25KHz ÜÒÝ Öçæ�èÉéÂèÉêÔáçë
Case1:8086
8hz-mp3 MP3 Encoder
main( ){
}
L3_compress( ){
}
Vfilter *filter = new Vfilterextern "C" filtertest( ){
}
ììì
ììì
Hardware Simulation
filtertest( )
C++ Code
íïîÐðÎñóòÅôÂõÅöÂ÷ËøúùÎûÎüÂýÿþ������������ �� � ��������������������� û��� �� � ���� ð� �!ËûÎüÂý ñ�"��#�$�%'&�(*)�+ ��, û8hz-mp3 MP3 Encoder
main( ){
}
L3_compress( ){
}
filtertest( ){
}
---
---
Hardware Simulation
filtertest( )
C program
command_to_seconds( )
command_to_seconds( )
command_to_seconds( )
command_to_seconds( )
SECONDS
method simulation time[h:m:s]
runseconds
Verilator
18:43:41
00:02:45
.0/2143652.87:9<;>=2?A@ABDC>EFHG4 I ? WAV J4KMLON2P 9RQS5UTWV
340~446 XIntel Cereron 2.2GHz, 512MB RAM, Redhat Linux 8 Y @AB
Case2:MP3
i8086
MP3
i8086 Z\[^] g`_^acb ,MP3 d hkj+efehgji flkph]dmhnpo20 qsrstvu HDL w\[vxlyfzlu|{~}p��j�\�����f��� h ��� f o ^��E\ HDL w\[��s� Qh�� u�{j�l����� Xp���
main()
SCE_MIHardware
Side
��� QSCE_MI
Software Side(UI)
m�� \����
�s QVerilator¡s¢�£ � } HW¤s¥ � ¡ ���f�� h �¦� f MPOmv� \j���
§©¨ �«ª¬¯®j°��©±² �v³<´¶µc·c¸c¹"�µpº¼»«½©¾¿·c¸c¹"�µpº¼»ÁÀ¼Â¶Ã¶ÄÆÅ
ÇÉÈËÊÍÌÏÎÍÐÒÑÔÓÖÕ ÊØ×
ÙÖÚ ÛÍÜ ÊÞÝ
ÎÍÐ
ßáà
C++ code C++ code
GCC(compile)
object object
G++(link)
SFL code
Verilog code
executablebinary
GCC(compile)sfl2vl
Verilator
simulation nvironment
hardwaresource code
Simulation
Emulation
C â¶ã�äÁå�æèçléhêìë~íïîéfðÁñ¼ò`ó�ä~ôöõ runseconds ÷�øèù|ôöõ�úUûcü¿ý 100 þjÿ����Uÿ � î��¶å¿éhêìëíïîìé�ð���¿úõ���� ����� ÷���ôïý��¶ù����øèùü���ô����©û��
FPGA etc..PC
HWC++
SFL �! "$#&%('*)!+-,/.10324+ 56 87:9<;>=@? A8B*CDFE-G@H-I +-,/.10324+ 56 G@HKJ$L A&M*NPO J6Q RTSVUPW:X1Y +-,/.10324+ 56 [Z4\^]`_Fa4bc2d (e4f4gh ibPj:k JFI$l*m A YKn Co +-,/.10324bdp[%$q@rKZ I Verilog +-,/.10324b Icarus Verilog sut 22 v@w@xya SFL +-,/.10[zcb SECONDS sut300 v@w@xy%('*)!+-,/.10324+ 56 [{}|c~ A8B*C � B@a^�12 i�g/�$e6�:�<; C++ �$2}�*� p DFEK�1� BF�u�}� "�g/�$eTp[%$�@�u+-,/.10324+ 56 P�6�h�hZ4\ � CR1�6J ~:�:�:�d�:% SCE-MI |c� �@�}�y�(� "�Z Ic� � "�� [�4%}�P�F d% UI pKA&M C++API ;¢¡ n M4£ t¥¤c¦d%§:¨ ¡u©^ju «ªK2c�! [{¬h¡h®P¯ JPYK�[°@± Z4\ � C
²´³¶µ¸·º¹¼»sfl2vl
(SFL-Verilog)
Verilator(Verilog-C++)
gcc(C++-Executable)
½¿¾ÁÀâĞÁÀÃÂ2718 3667
ÆÈÇÊɸË[s]
0.15
3667 11048 3.42
11048 --- 15.33
Ì´ÍÊθϺмÑsfl2vl
(SFL-Verilog)
Verilator(Verilog-C++)
gcc(C++-Executable)
Ò¿ÓÅÔÃÕ$ÖÅÓÅÔÃÕ3909 6176
×ÈØÊÙ¸Ú[s]
0.500
6176 20708 4.402
20708 --- 18.67
Û Ü Ý& Þ
4.402ß(à
á 24 â
ãåä ñçæhî�èlñ Séê òèó åìë`ø¿ù
4.402ß(à
á 19 â