lpc2148 microcontroller architecture and programming

LPC2148 Microcontroller

Architecture and Programming

Dr. N. Mathivanan Visiting Professor,

Department of Instrumentation & Control Engineering

National Institute of Technology

Trichy

LPC2148

• Provided by NXP Semiconductor Ltd.

• Based on ARM v4T architecture version,

• Based on ARM7-TDMI processor

• Integrated Real-Time Emulation and Embedded Trace support.

• Topics discussed:

o Specification list

o LPC2148 – Internal architecture diagram

o Pin diagram, Pin connect block,

o Memory map

o GPIO, PLL

o Interrupt structure, Vectored Interrupt Controller (VIC)

o Peripherals: ADC, DAC, Timer, PWM,

o Serial Communication Interfaces:

Dr. N. Mathivanan

Processor

Architecture

Processor

Instructions

Debug support

: ARM v4T

: ARM7-TDMI-S

: 32-bit ARM and 16-bit Thumb

: RT EmbeddedICE, Embedded Trace interface

Static RAM

(On-chip)

Size

Additional

: 32 KB

: 8 KB for USB DMA

Flash Program

Mem. (On-chip)

Size

Programming

: 512 KB

: ISP/IAP via on-chip boot-loader program.

GPIO No. of pins

Features

: up to 45 (fast GPIO lines, 5V tolerant)

: Configurable to fast GPIO

External

Interrupts

Interrupts

No. of pins

Sensitivity

: Four

: Nine

: Rising/falling edge or low/high level sensitive

Timer/Counter

No. of Timers

Operation

Compare & Cap

: Two, 32-bit

: Counter or timer operation

: Four channels for each timer

• LPC2148 - Specifications

Dr. N. Mathivanan

PWM No. of outputs

If not enabled

: 6 single edge / 3 double edge controlled or mix

: Used as a standard 32-bit timer/counter

Watchdog

Timer Timer

32-bit counter, divide by 4 fixed pre-scaler

Internally resets the chip

RTC Features

Maintains calendar, clock,

Provides Seconds, Minutes, Hours, day of week, day

of Month, Month, day of Year, Year.

Consumes very low power,

Dedicated power pin, can use battery

Uses dedicated 32 kHz clock

ADC

No. of ADC

No. of channel

Resolution

Conversion time

VREF

: Two, Successive approximation type

: 14 (ADC0 – 6 channels, ADC1 – 8 channels)

: 10-bit

: 2.44 ms per channel

: >2.5V, <3.3 V

DAC

No. of DAC

Resolution

VREF

: One

: 10-bit

: 3.3 V Dr. N. Mathivanan

UART No. of channels

Modem Interface

: Two (16C550 compliant), UART0 and UART1

: UART1 with full modem interface

SPI No. of channels : One

: Full Duplex, Multiple master and slaves support

SSP Compatibility : Motorola SPI, 4-wire TI SSI, and

National Semiconductor Microwire

I2C No. of buses : Two

USB

USB ports

Compliant

Data transfer rate

Controller

Special feature

: One

: USB 2.0

: Full-speed (12 Mbps)

: USB Device

: 2 KB endpoint RAM

Package : LQFP64 (Low profile Quad Flat Package)

Features

128-bit memory interface

60 MHz operation

PLL, VIC, Power Control

Configurable interrupt priorities and vector addresses Dr. N. Mathivanan

Architecture Diagram

Dr. N. Mathivanan

Pins & Signals

LQFP64 package,

64 (physical) pins,

Multiple functions assigned

By default I/O function

Power supply, ground, osc pins not multiplexed

Dr. N. Mathivanan

Pin Connect Block

• 64 pins are attached to two 32-bit I/O ports, Port-0 & Port-1.

• Port-0, Port-1 pins are designated as P0.0 – P0.31 & P1.0 - P1.31.

• Pins P0.24, P0.26, P0.27, P1.0-P1.15 are unavailable.

• Pin functions are multiplexed, up to 4 functions assigned to each pin.

o Port-0 pins multiplex peripheral pin, & comm. interface pin functions

o Port-1 pins multiplex JTAG interface, Trace function

o Advantages: keeps size small, adds more functionalities to devices

o Disadvantages: if functions not carefully selected, some can’t be availed

• Pin function select Registers: PINSEL0, PINSEL1, PINSEL2

o PINSEL0 selects functions of pins P0.0 to P0.15,

o PINSEL1 selects functions of pins P0.16 to P0.31

o PINSEL2 selects functions of pins P1.16 to P1.31

Refer to technical manual for physical pin no., I/O

port no., and functions assigned for each pin Dr. N. Mathivanan

• Pin function selection – Examples

1. Configuring P0.0 and P0.1 of Port-0 I/O pins for TxD0 and RxD0 functions of UART0 in ‘C’:

PINSEL0 &= ~(0xF); //clear bits[3:2], [1:0] of PINSEL0 register, hence

//assign P0.0, P0.1 general purpose I/O function

PINSEL0 |=(1<<2)|(01); //place 01 in bits[3:2], [1:0] of PINSEL0 register

//which selects TxD0 for P0.0 & RxD0 for P0.1 pins

//configuration of other pins remains same

2. For using DAC, select Aout function for P0.25 pin.

PINSEL1 &= ~(0x3<<18); //clear bits[19:18] of PINSEL1 register

PINSEL1 |= (0x2<<18); //place 10 into bits[19:18] of PINSEL1 reg.

//select Aout function for P0.25

• Questions:

How are LPC2148 pins configured for the following?

(i) PINSEL0 = 0x0000 0000; (Ans. I/O pins P0.0 to P0.15 are configured for GPIO function)

(ii) (a) PINSEL0 = 0x0001 0000; (b) PINSEL0 = 0x0002 0000; (c) PINSEL0 = 0x0003 0000;

(iii) PINSEL1 &= ~(0x03); PINSEL1 |= (0x03); Dr. N. Mathivanan

Memory Map

Dr. N. Mathivanan

No. Peripheral Base Address No. Peripheral Base Address

0 Watchdog

Timer 0xE000 0000 12 Not used 0xE003 0000

1 Timer0 0xE000 4000 13 ADC0 0xE003 4000

2 Timer1 0xE000 8000 14 – 22 Not used 0xE003 8000 –

0xE005 8000

3 UART0 0xE000 C000 23 I2C1 0xE005 C000

4 UART1 0xE001 0000 24 ADC1 0xE006 0000

5 PWM 0xE001 4000 25 Not used 0xE006 4000

6 Not used 0xE001 8000 26 SSP 0xE006 8000

7 I2C0 0xE001 C000 27 DAC 0xE006 C000

8 SPI0 0xE002 0000 28 – 35 Not used 0xE007 0000 –

0xE008 C000

9 RTC 0xE002 4000 36 USB 0xE009 0000

10 GPIO 0xE002 8000 37 – 126 Not used 0xE009 4000 –

0xE01F 8000

11 Pin Connect

Block 0xE002 C000 127

System Control

Block 0xE01F C000

Dr. N. Mathivanan

GPIO

• Pins not selected for peripheral functions are GP I/O port pin

• I/O port pins dynamically configured as input/output using GPIO reg.

• Two sets of GPIO registers –

o Both control same I/O pins

o One set on APB, provides legacy (normal) GPIO functionality

o Another set on ARM local bus, provides enhanced (fast) GPIO function

In enhanced mode, registers are byte addressable

Includes mask registers to treat bits in groups

• GPIO registers

• IOxPIN – To get logic value on a I/O pin

• IOxSET – To set an output configured pin (by writing 1 in corresponding bit)

• IOxCLR - To reset an output configured pin (by writing 1 in corresponding bit)

• IOxDIR – To select input /output function (by placing 0/1) for an I/O pin

(x = 0/1, i.e. Port-0 or Port-1) Dr. N. Mathivanan

• Examples: Configuring & initializing GPIO pins

PINSEL1 &= ~(0xFF); // configure pins from P0.16 to P0.19 as GPIO

IO0DIR |= (0xF<<16); // set pins P0.16 – P0.19 to output function

IO0SET |= (1<<16)|(1<<18); // set pins P0.16 & P0.18 of Port-0 HIGH

IO0CLR |= (1<<16); // reset logic level of pin P0.16 of Port-0 LOW

(Demo: ‘C’ Program to illustrate configuring, setting / resetting I/O pins using

Keil mVision - Debugger/Simulator)

Dr. N. Mathivanan

Phase Locked Loop (PLL)

• LPC214x has two PLLs: PLL0 and PLL1

• PLL1 is used for USB.

• PLL0 is used to generate clock for CPU (CCLK) & peripherals (PCLK)

• Uses crystal oscillator input frequency (FOSC) 10–25 MHz and

generates output up to 60 MHz

• Parameters m & p determine output frequency, CCLK = m x FOSC

• In the feedback path of PLL there is current controlled osc (CCO)

whose frequency should be kept within 156 – 320 MHz.

Computing m and p values for generating

CCLK of 60 MHz from FOSC 12 MHz

m = CCLK/FOSC = 60/12 = 5

If p is chosen to be 2, CCO (= 2 x p x 60) is within

156 – 320 MHz.

Dr. N. Mathivanan

• PLL Registers

PLLxCON – Controls PLL activation; used to enable and connect PLL

PLLxCFG – Multiplier value (bits [4:0]) and divider value (bits [6:5] are configured

PLLxSTAT – Shows current enable & connect status, m & p values, lock status

PLLxFEED – Writing feed sequence, i.e. ‘0xAA’ and ‘0x55’ in sequence, to this register

– It enables changes made to PLLCON, PLLCFG registers to take effect

APBDIV – Sets PCLK freq to 1/4, same or 1/2 of CCLK (by writing 0x00, 0x01, 0x02),

• PLL configuration sequence

• Determine m and p values for desired CCLK and PCLK from FOSC

• Enter (m-1) in bits [4:0] and enter 00/01/10/11 for p values 1/2/4/8 in

bits [6:5] of PLLCFG register.

• Enable PLL using PLLCON register (by setting bit[0]).

• Issue feed sequence, i.e. write constants 0xAA, 0x55 into PLLFEED reg

• Wait for PLL to lock (by checking bit[10],

• Connect & enable PLL using PLLCON reg. (by setting bits[1:0])

• Issue again feed sequence Dr. N. Mathivanan

• Examples

o Configuring PLL0 for generating 60 MHz CCLK from 12 MHz FOSC

multiplier = CCLK / FOSC = 60 / 12 = 5; (m-1) = 4 is placed in bits [4:0]

o ‘p’ is chosen as 2, since CCO (= 2 x p x 60) is to be within 156 – 300 MHz

The m value is 4 and p value is 2 as explained above.

configword = (p<<4)|(m-1); // frame configuration word with m & p values

PLL0CFG = configword; // write into configuration register

Enabling but not connecting PLL0, enabling and connecting:

Bit [0] of PLL0CON register is set for only enabling and bits[1:0] are set for enabling and

connecting.

PLL0CON = 0x01; // enable PLL but not connect

PLL0CON = 0x03; // enable PLL and connect

Issue of PLL feed sequence: PLL0FEED = 0xAA; // first fixed value

PLL0FEED = 0x55; // second fixed value

Dr. N. Mathivanan

Checking PLL0 lock status & waiting till PLL0 locks onto the target

frequency:

PLOCK, the bit [10] of PLL0STAT register, is polled and checked for lock status.

PLOCK = 0x40;

while(!(PLLSTAT & PLOCK)); // poll lock status & wait till PLL0 locks

Programming APB divider for desired PCLK frequency:

Value 0x00, 0x01 or 0x02 in APBDIV register sets the PCLK frequency to one-

fourth, same as or half of CCLK frequency.

APBDIV = 0x02 // set PCLK frequency to (CCLK/2)

Dr. N. Mathivanan

Interrupt Structure

• ARM7 Processor hardware interrupt inputs: 2, (FIQ. IRQ)

• LPC2148 external interrupt inputs: 4 (available on 9 pins)

• Processor and on-chip user peripherals generate interrupts

• LPC2148 uses ARM PrimeCell (PL190) Vectored Interrupt Controller

for managing interrupts.

• PL190 is interfaced to ARM core through the fast AHB bus

• When interrupt occurs,

o VIC identifies the source of interrupts

o Passes requests on interrupt request pins as per the configuration

o If more than one interrupt occurs at a time, VIC resolves priority

Dr. N. Mathivanan

Vectored Interrupt Controller (VIC) • 32 interrupt request inputs, LPC2148 uses 22 of 32 interrupts

• Categorizes into FIQ, VIRQ, NVIRQ interrupts

• Any of the 22 interrupts can be assigned to FIQ / VIRQ / NVIRQ

o FIQ: Generally, only one interrupt is assigned, VIC provides ISR address.

If more than one is assigned to FIQ, VIC combines all, generates VICFIQ,

provides only one ISR address for all FIQ (Non-Vectored FIQ) .

o VIRQ & NVIRQ

VIC has 16 VIRQ slots, Slot-0 to Slot-15. Any IRQ configured interrupts can be

assigned to any slot. Priorities are in the order of slot number.

Interrupts configured as IRQ, not assigned any VIRQ slot, is assigned as

NVIRQ

VIRQ & NVIRQ interrupts are combined and VICIRQ is generated

o Programs can handle 1 FIQ, 16 VIRQ, 1 NVIRQ (total 18) interrupts Dr. N. Mathivanan

Interrupt request logic

NVFIQ logic

Vectored IRQ blocks

NVIRQ logic

Priority block

VICFIQ, VICIRQ

External interrupt inputs

Many 32-bit registers

• ARM PrimeCell Vectored Interrupt Controller (PL190)

Dr. N. Mathivanan

• Bit allocation for sources of interrupts in VIC registers

Bit allocation of bits for various sources of interrupts in VIC registers

Bit-7

(Channel-7)

Bit-6

(Channel-6)

Bit-5

(Channel-5)

Bit-4

(Channel-4)

Bit-3

(Channel-3)

Bit-2

(Channel-2)

Bit-1

(Channel-1)

Bit-0

(Channel-0)

UART1 UART0 Timer1 Timer0 ARMC1 ARMC0 ----- WDT

Bit-15

Channel-15

Bit-14

Channel-14

Bit-13

Channel-13

Bit-12

Channel-12

Bit-11

Channel-11

Bit-10

Channel-10

Bit-9

(Channel-9)

Bit-8

(Channel-8)

EINT1 EINT0 RTC PLL SPI1 (SSP) SPI0 I2C0 PWM

Bit-23

Channel-23

Bit-22

Channel-22

Bit-21

Channel-21

Bit-20

Channel-20

Bit-19

Channel-19

Bit-18

Channel-18

Bit-17

Channel-17

Bit-16

Channel-16

--- USB ADC1 BOD I2C1 ADC0 EINT3 EINT2

Bit-31

Channel-31

Bit-30

Channel-30

Bit-29

Channel-29

Bit-28

Channel-28

Bit-27

Channel-27

Bit-26

Channel-26

Bit-25

Channel-25

Bit-24

Channel-24

---- ---- ---- ---- ---- ----- ---- ----

Dr. N. Mathivanan

• VIC Registers (not all listed)

VICIntSelect: High, Low bits select interrupts as FIQ, IRQ respectively

VICIntEnable: High bit enables FIQ or IRQ classified interrupts

VICIntEnClr: High bit disables FIQ or IRQ classified, enabled interrupts

VICSoftInt: Generates any interrupt by software. High bit generates corresponding interrupt

VICSoftIntClr: Clears a bit in Software Interrupt register

VICIRQStatus: A high bit indicates corresponding IRQ classified, enabled IRQ interrupt is active

VICFIQStatus: A high bit indicates corresponding FIQ classified, enabled IRQ interrupt is active

VICVectAddr: Holds ISR addr of active interrupt. Writing any value indicates End of Interrupt

VICVectAddr0 – VICVectAddr15: Hold ISR addresses for slots 0 to 15

VICVectCntl0 – VICVectCntl15: Control 16 IRQ slots, assigns sources to each slot.

Bit [4:0] selects VIC channel, bit [5] select VIRQ / NVIRQ,

high / low bit provides dedicated / default ISR addr.

Dr. N. Mathivanan

• Programming VIC registers:

o Program VICIntSelect: Set / reset the bits for FIQ / IRQ classification

o Program VICVectCtrlx: Assign VIRQ slot ‘x’ to IRQ classified interrupt

o Program VICVectAddrx: Write ISR addr of VIRQ interrupt assigned to slot ‘x’

o Program VICIntEnable: Enable interrupts

• Handling FIQ interrupts:

o Branch instruction at 0x0000001C uses address of FIQ handler directly and

goes to FIQ routine. This reduces interrupt latency.

o If more than one interrupt are assigned as FIQ, the handler routine identifies

the source of interrupt. This increases interrupt latency.

o Executes codes respective of identified interrupts.

o Clears flags set by peripherals in their interrupt registers

o End of interrupt.

Dr. N. Mathivanan

• Handling IRQ interrupts:

o On interrupt, processor executes branch instruction from interrupt vector

table at 0x 00000018 and branches to IRQ handler routine

o Reads VICVectAddr reg that holds address of highest priority pending VIRQ

Slot-x interrupt. If no slot is assigned, it holds address of default vect address

o Branches to handler routine.

o Reads interrupt register of the peripheral, identifies actual source, executes

codes respective of the interrupt.

o Clears interrupt flags set by peripherals in their interrupt registers.

o Writes a dummy word into VICVectAddr register to indicate EoI, to clear

respective interrupt in VIC interrupt priority hardware.

o Returns back to interrupted program, re-enables interrupts.

Dr. N. Mathivanan

Programming VIC registers: Examples

o Programming VICIntSelect register

VICIntSelect = 0x0000 0010; // enable VIC Timer-0 channel as VFIQ interrupt

// (by default all interrupts are VIRQ enabled)

o Programming VICVectCntlx register

VICVectCntl0=(0x01<<5)|0x04; // assign VIRQ Slot-0 to Timer-0, enable Slot-0

// (bit[4:0] is channel no. bit[5] enables slot)

o Programming VICVectAddrx register

void Timer0ISR(void) __irq; // declare prototype for ISR

unsigned long int T0vectaddr; // declare variable to hold Timer-0 ISR address

T0vectaddr=(unsigned)Timer0ISR; // place ISR address in variable

VICVectAddr0 = T0vectaddr; // write ISR address into Slot-0 VectAddr reg

o Programming VICIntEnable register

VICIntEnable = 0x00000010; // enable Timer-0 interrupt

Dr. N. Mathivanan

• Questions:

Write C statements for the following.

i. Program VICIntSelect register to configure TIMER1 as FIQ interrupt and

ADC0, UART1 and SPI as IRQ interrupts without disturbing the

configuration of other VIC channels.

ii. Program VICVectCntl0 register to assign ADC0 interrupt (channel-18) to

VIRQ Slot-0 and VICVectCntl1 register to assign UART1 interrupt (channel-

7) to VIRQ Slot-1.

iii. Place address of ADC0 interrupt handler routine in VICVectAddr0 register

and address of UART1 interrupt service routine in VICVectAddr1 register.

iv. Program VICIntEnable register to enable TIMER1, ADC0, UART1 and SPI

interrupts.

Dr. N. Mathivanan

External interrupt inputs

• Interrupt inputs: EINT0, EINT1, EINT2 (2 pins to each), EINT3 (3 pins)

• Registers: 4 – Bit allocation Bit[0] – EINT0, bit[1] – EINT1, ………….

EXTINT: Interrupts set flags, writing ‘1’ in respective bits clears interrupts

INTWAKE: Interrupts enabled by this reg wakesup CPU from power down mode

EXTMODE: Sets edge/level sensitivity to interrupt inputs

EXTPOLAR: Sets polarity for edge/level sensitivity

Block Symbol Description I/O

*Port

I/O

No.

@Pin Configuration Pin

No PSR Bits Val

External

Interrupts

EINT0 External interrupt input 0 I P0.1 0 3:2 11 21

P0.16 1 1:0 01 46


P0.14 0 29:28 10 41


P0.15 0 31:30 10 45

EINT3 External interrupt input 3 I

P0.30 1 29:28 10 15

P0.9 0 19:18 11 34

P0.20 1 9:8 11 55 Dr. N. Mathivanan

Programming EINT registers: Examples

1.EXTINT=0x00000001; // clear interrupt flag set by EINT0 interrupt

2.EXTMODE &= 0 << 3; // set level sensitivity to external interrupt EINT3 pin

3.EXTMODE &= 0 << 2;

EXTMODE |= 1 << 2; // set edge sensitivity to external interrupt EINT2 pin

EXTPOLAR &= 0 << 2;

EXTPOLAR |= 1 << 2; // set rising edge sensitivity to EINT2 pin

Dr. N. Mathivanan

Timer

• No. of Timers : 2, (Timer0 and Timer1)

• Applications

• PWM, data acquisition, measurements of freq, speed, velocity, position

• Functional Block Diagram

Dr. N. Mathivanan

• Timer Operation:

o Uses PCLK clock

o Prescale Counter (PC) increments on each PCLK clock input pulse

o Prescale Register (PR) holds 32-bit value

o When PC = PR, increments Timer/Counter (TC) and resets PC

o Hence, TC counting rate is controlled by PR

o Each timer has 4 capture channels, 4 capture inputs (CAPx.0-CAPx.3)

A transition on capture input, copies TC value into Capture Reg (CR)

Can optionally generate interrupt also

CCR configures capturing event (rising, falling or both edges)

o Each timer has 4 match channels, 4 match outputs (MATx.0-MATx.3)

o For each match channel, there is a MR that holds 32-bit value

o When TC = MR, an event (reset or stop TC, generate int) is triggered

o MCR configures type of event to generate

Dr. N. Mathivanan

• Timer Registers

Timer Counter (TC): Incremented when PC = PR

Timer Control Register (TCR): Enables / disables, resets TC

Prescale Register (PR): Holds max value for PC to count up to. Controls counting rate

Prescale Counter (PC): Increments on every PCLK clock

Capture Registers 0 – 3: Transition on cap inputs copy TC into respective reg

Capture Control Register (CCR): Prescribes active event (rising/falling edge), int

Match Registers 0 – 3 (MR): Holds a value, matched with TC, matching triggers event

Match Control Register (MCR): Prescribes action (enabling/ disabling interrupt

generation, resetting/disabling TC, or stopping TC and PC) to be triggered on match

Count Control Register (CTCR): Selects Timer or Counter mode;

Interrupt Register (IR): Has 4 bits for match interrupt, 4 bits for capture interrupt.

When interrupt occurs corresponding bit is set. Writing high in a bit resets

corresponding interrupt

Dr. N. Mathivanan

• Programming Timer Registers:

The registers for a typical application are configured in the following order

i. TxCTCR and TxIR registers are programmed.

ii. TxPR and TxMRy are initialized with appropriate values.

iii. TxMCR and TxCCR are programmed.

iv. TC and PR are reset by programming TxTCR register.

v. Timer is enabled by programming TxTCR register.

• Examples

1. Programming Prescale Register of Timer0 for incrementing the Timer/Counter

on every one ms. (Assume PCLK is 30 MHz. )

unsigned long int prescaleval; // variable defining Timer resolution

prescaleval = 0x0000 7530; // max. count by PC is set to 30,000

T0PR = prescaleval – 1; // as PC starts counting from zero

// PR is set to (max. count–1) Dr. N. Mathivanan

2. Initialize Timer0 match register and match control register for generating

interrupt at regular interval of 1 s.

Assume PCLK is set to 30 MHz and PR is initialized with a value (30,000-1) so that

TC is incremented at one ms interval.

T0MR0 = 0x0000 03E8; // load 1000 into MRO

T0MCR = 0x0000 0003; // When TC = MR0, reset TC and generate interrupt

T0TCR = 0x0000 0002; // reset TC and PC

T0TCR = 0x0000 0001; // enable TC

3. Initialize Timer0 capture control register for capturing TC on rising edge of

signal applied to CAP0.0 pin.

T0CCR = 0x0000 0005; // capture TC value on rising edge of CAP0.0 channel

// and generate interrupt

Dr. N. Mathivanan

PWM

• Reduces power delivered to load without power loss

• Extensively used in industrial control (e.g. DC motor control), volume

control of audio amplifiers, brightness control, power control.

• It is special type of Timer

• PWM signals – pulses with variable widths,

• Two parameters – period of pulse and duty cycle

• Examples of 10 kHz PWM signal with 25%, 50%, 75% duty cycles

Dr. N. Mathivanan

• PWM peripheral in LPC2148

o Has a Timer Counter, Prescale register and 7 match registers

o 6 PWM outputs and 6 corresponding match registers (MR1-MR6)

o MR0 is used by all PWM channels, used to control period of PWM cycle

o MR1-MR6 hold values that control pulse width (ON period)

o PWM outputs are set HIGH when a PWM cycle begins.

o When TC matches with a MRx corresponding PWM output goes LOW

and remains low till a next PWM cycle begins.

Dr. N. Mathivanan

• PWM registers:

PWMPR: Prescale Register. Specifies a max value for PC to count up to.

PWMPC: Prescale Counter. Counts on every PCLK clock pulse. When PC = PR, PC is

reset and TC increments.

PWMTC: Timer Counter. Incremented by PC when PC = PR.

PWMTCR: Timer Control Register. Controls Timer Bit[0] enables/disables (1/0) TC,

bit[1] resets both PC and TC.

PWMMR0 – PWMMR6: Match Registers. When TC = MRx, an action is triggered.

PWMMCR: Match Control Register: Action to be triggered on TC=MRx is prescribed,

3 bits for each MRx. Bit[0:2] for MR0, bit[5:3] for MR1, ………., bit[20:18] for MR6. Bit-

0, 1, 2 are set to generate interrupt, to reset TC, & to stop TC when TC=MR0.

Dr. N. Mathivanan

PWMPCR: Selects PWM channel type as single or double edge controlled

PWMLER: Latch Enable Register. It is used to control update of PWM match

register, bits[6:0] are set to latch of corresponding match register.

PWMIR: Interrupt register. When interrupt is generated corresponding bit is set.

Bit[3:0] flags for MR3-MR0, bit[10:8] are flags for MR6-MR4.

PWM Registers Programming Sequence:

PWMPCR = 0x00; // select single edge mode

PWMPR = 60 – 1; // set resolution to 1 ms (if PCLK=60 MHz)

PWMMR0 = 20000; // set Period to 20 ms (if resolution=1 ms)

PWMMR1 = 1000; // set pulse width to 1 ms (if period=20 ms)

PWMMCR = 0x0000 0002; // reset TC on TC matching with MR0

PWMLER = 0x0000 0003; // update MR0 and MR1

PWMPCR = 0x0000 0200; // enable PWM1 output

PWMTCR = 0x0000 0002; // reset TC

PWMTCR = 0x0000 0001; // enable TC

Dr. N. Mathivanan

• PWM programming example:

Configure PWM channels 1 & 2 for generating 1 kHz PWM signals with

25% & 50% duty cycles and 1 ms resolution. Assume PCLK is 30 MHz.

PWMPCR = 0x00; // select single edge controlled PWM

PWMPR = 30 – 1; // set resolution of PWM signal to 1 ms

PWMMR0 = 1000; // set PWM period as 1 ms (frequency 1 kHz)

PWMMR1 = 250; // set PWM1 pulse width as 0.250 ms (25% DC)

PWMMR2 = 500; // set PWM2 pulse width as 0.500 ms (50% DC)

PWMMCR = 0x00000002; // reset TC on TC matching with MR0

PWMLER = 0x00000007; // enable updated MR0, MR1, MR2 to take effect

PWMPCR = 0x00000600; // enable PWM1 and PWM2 outputs

PWMTCR = 0x00000002; // reset TC and PR

PWMTCR = 0x00000001; // enable TC

Dr. N. Mathivanan

• Functional Block Diagram

Dr. N. Mathivanan

ADC

• ADC0 (6 Ch), ADC1 (8 Ch)

• Type: 10-bit, SA type,

• Supports burst mode (repeated conversion at 3-bit to 10-bit resolution)

• Supports simultaneous conversion of both ADCs

• Conversion time: 2.44 ms,

• SoC by software control, on timer match, transition on a pin

• Range: 0 V – VREF (+3.3 V)

• Max. clock freq is 4.5 MHz, (by programming ADCCON)

Dr. N. Mathivanan

• Pin configuration

Block Symbol Description I/O

*Port

I/O

No.

@Pin Configuration Pin

No PSR Bits Val

ADC0

AD0.1 ADC – 0 Channel – 1 analog input AI P0.28 1 25:24 01 13






ADC1









Dr. N. Mathivanan

• Block diagram

Dr. N. Mathivanan

• ADC Registers

o Control Register:

Selects channel, clock freq, resolution, conversion mode, method of

issue of SoC, edge for conversion

o Global Start Register:

Used to initiate simultaneous conversion on both ADCs

o Status Register:

Allows simultaneous checking of status of all A/D channels,

Contains done, overrun, interrupt flags

o Data Registers (DR0 – DR7):

Contains most recent converted data and EoC status on respected ch,

o Global Data Register:

Contains done bit, most converted data, ch number

o Interrupt Enable Register:

Enables interrupt on Eoc by each channel

Dr. N. Mathivanan

• Programming ADC registers – Examples (Construction of control words)

Select ADC-0, Channel-1, Clock frequency 4 MHz (let PCLK is 60 MHz), Software

controlled mode and 10-bit resolution. Power-up ADC and issue start of conversion.

unsigned long int ctrlwordAD0 = 0x0;

crtlwordAD0 = 1<<21|0x0<<15|0x0E<<8|0x02; // configure SEL, CLKDIV, BURST

// CLKS & PDN bit fields

crtlwordAD0 |= 1<<24; //set START, signal start of conversion

AD0CR = crtlwordAD0; // write into ADC0 control register

Select ADC–1, Channels 0 to 7, clock frequency 4.5 MHz (assume PCLK is 30

MHz), burst mode repeated conversion, 8-bit resolution.

unsigned long int ctrlwordAD1 = 0;

crtlwordAD1 = 2<<17|1<<16|0x06<<8|0xFF; // select chs, freq, mode & resolution

crtlwordAD1 |= 1<<21; // power-up ADC

crtlwordAD1 |= 1<<24; // issue start of conversion

AD1CR = crtlwordAD1; // write control word into ADC1 CR

Dr. N. Mathivanan

Monitoring end of conversion and reading converted data:

Initiate software controlled conversion of analog signal applied to ADC-0 Channel–

1 and monitor end of conversion. On completion, read converted data. Set ADC

clock frequency to 4 MHz with 24 MHz PCLK.

unsigned long int crtlword, done;

unsigned int ADCdata;

unsigned char channel;

crtlword = 0x00200502; // power-up,CLKS:10-bit, SWctrl,CLKDIV:6,Ch:1

AD0CR = crtlword |1<<24;// SoC – Start conversion immediately

do

{

done = AD0DR1 & 0x8000 0000; // read ADC0 DR1 and find ‘DONE’ bit

}while(!done); // poll till DONE is set

ADCdata = (AD0DR1>>6)&0x3FF; // A to D converted data

Dr. N. Mathivanan

DAC

• LPC2148 has one 10-bit DAC

• Settling time software selectable

• DAC output can drive max of 700 mA or 350 mA

• DAC peripheral has only one register, DACR

• It contains 10-bit value for conversion in bit[15:6] position

• Bit[16] selects settling time, ‘1’ selects 700 ms, ‘0’ selects 350 ms

• Example: Configure DAC register for generating (i) 0V, (ii) 1.65V, (iii) 3.3V

with 3.3V VREF. Select 700 ms settling time.

DACR = 0x00010000; // AOUT = 0 V

DACR = 0x00018000; // AOUT = 1.65 V

DACR = 0x0001FFC0; // 𝐴𝑂𝑈𝑇 = 3.3 ×1023

1024 𝑉

Dr. N. Mathivanan

Review Questions

1. Illustrate pin function selection in LPC2148 with an example

2. How are the LPC2148 pins configured for “PINSEL0=0x00000000;”?

3. Write down the GPIO registers and their function.

4. Write a ‘C’ program fragment to select GPIO function for I/O pin P0.0,

configure the pin as output port and set the pin to HIGH.

5. Write down the range of memory space allocated for APB & AHP peripherals

6. Describe the PLL configuration sequence.

7. How do you program PLL0CFG register for generating 60 MHz CCLK from 12

MHz FOSC?

8. How do you issue PLL feed sequence?

9. Discuss in detail the interrupt processing by LPC2148 with ARM PrimeCell

Vectored Interrupt Controller.

10. Describe the operation of ARM Primecell VIC.

11. List various VIC registers and outline their functions.

Dr. N. Mathivanan

12. Program VICVectCntl0 register to assign ADC0 interrupt (Channel -18) to

VIRQ Slot-0.

13. Illustrate programming of VIC registers in a sequence for a typical interrupt

application.

14. Discuss External Interrupt Inputs control block and processing of external

interrupts in LPC2148.

15. What are the applications for the Timer peripheral?

16. Draw the functional block diagram of a Timer peripheral in LPC214x

microcontroller and explain the functionalities supported by the Timer.

17. List various registers of a Timer peripheral and mention their functions.

18. Explain the sequence of programming of Timer registers for typical

applications.

19. Write a C program fragment for programming PR of Timer0 for incrementing

the TC on every one ms and for initializing MR0 and MCR for generating

interrupt at regular interval of 1 s. (Assume PCLK is 30 MHz. )

Dr. N. Mathivanan

20. Write down typical applications of PWM peripheral.

21. List registers of PWM peripheral and mention about their functions.

22. Illustrate with suitable example, the programming sequence of PWM

registers.

23. Draw the functional block diagram of a ADC peripheral in LPC2148.

24. Write down the specifications of ADC peripherals in LPC2148.

25. List various ADC registers and mention their functions.

26. Initiate software controlled conversion of analog signal applied to ADC-0

Channel–1 and monitor end of conversion. On completion, read converted

data. Set ADC clock frequency to 4 MHz with 24 MHz PCLK.

27. Write a C program fragment to generate a triangular waveform on Aout pin

using on-chip DAC peripheral.

Dr. N. Mathivanan

Textbooks & Reference books

• Andrew N. Sloss, Dominic Symes, and Chris Wright, ARM

System Developer’s Guide: Designing and Optimizing System

Software, Morgan Kaufmann Publishers, 2004.

• Trevor Martin, The Insider’s Guide to the Philips ARM7-Based

Microcontrollers, Hitex (UK) Ltd., 2005.

• Reference Books:

• ARM Architecture Reference Manual: ARM DDI 01 001,

• LPC214x User Manual, UM10139: NXP Ltd. (2012)

• N. Mathivanan, PC Based Instrumentation: Concepts and

Practice, PHI Learning, 2007.

Dr. N. Mathivanan