low power techniques for soc design: basic concepts and...

Motivation Basic Concepts Standard Low Power Design Techniques Advanced Low Power Design Techniques References

Low Power Techniques for SoC Design:basic concepts and techniques

Estagiario de DocenciaM.Sc. Vinıcius dos Santos Livramento

Prof. Dr. Luiz Claudio Villar dos Santos

Embedded Systems - INE 5439Federal University of Santa Catarina

September, 2014

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Outline

1. Motivation

2. Basic ConceptsPower vs. EnergyDynamic and Static PowerTrends on Total Power Consumption

3. Standard Low Power Design TechniquesClock GatingGate Level OptimizationMulti Vth

Multi Vdd

4. Advanced Low Power Design TechniquesPower GatingVoltage and Frequency Scaling

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Motivation

I Portable mobile devices (PMDs)comprise one of the fastest growingsegments of the electonics market

I PMDs integrate a number ofcomputationally-intensivefunctionalities

I Since PMDs are powered by batteries,energy is a major problem

I To tackle the energy issue a numberof techniques are used throughoutsoftware and hardware design flow

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Motivation

(SAMSUNG, 2014)

I PMDs are complex systems ofhardware and software known asSystem-on-Chip (SoC)

I An example of contemporary SoC isthe Samsung Exynos 5 Dual used byGoogle Nexus 10 and SamsungGalaxy Tab II

I The Exynos 5 Soc is implemented inCMOS 32 nm and comprises 2x ARMCortex-A15 processor and otherscomplexes blocks

I This course focuses on low powerdesign techniques for embeddedhardware

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Embedded hardware design flow

(CHINNERY; KEUTZER, 2008)

I The embedded hardware design flowis based on libraries ofpre-characterized gates known asstandard cell libraries

I It starts from a RTL description andends up with a layout ready formanufacturing

I Several steps are performed (someiterativelly) so as to achieve thedesign functional and non-functionalobjectives as area, delay and power

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Power vs. Energy

Power vs. Energy

(KEATING et al., 2007)

I Delay (s)I Performance metric

I Energy (Joule)I Efficiency metric: effort to perform

a task

I Power (J/s or Watt)I Energy consumed per unit time

I Power Density (W /cm2)I Power dissipated per unit of area

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Dynamic and Static Power

Dynamic (switching) Power


I Energy / transition (J)I CL × V 2

dd consumed from sourceI 1

2× CL × V 2

dd dissipated duringoutput transition 0→ 1

I 12× CL × V 2

dd dissipated duringoutput transition 1→ 0

I Pdyn (W )I 1

2× CL × V 2

dd × fclock × αI Switching activity (α)

I 0 ≤ α ≤ 1

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Dynamic (short circuit) Power


I Energy / transition (J)I Short circuit power occurs when

both the NMOS and PMOStransistors are on

I Psc = tsc × Vdd × Ipeak × fclock × αI tsc is the time duration of the

short circuit currentI Ipeak is the total switching

current

I As long as the ramp time (slew) ofthe input signal is kept short, theshort circuit current occurs for onlya short time during each transition

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Static (leakage) Power

(RABAEY, 2009)

I Transistors are imperfect switches

I Main sources of static power are gateand sub-threshold leakage

I Gate leakageI Tunneling currents through thin

gate oxide (SiO2)

I Sub-threshold leakageI Current that flows from drain to

source when transistor is off

I Isub = µCoxV2t

WL.e

Vgs−VthnVt

I Threshold voltage vth dependsexponentially on Vgs − Vth

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Trends on Total Power Consumption


(KIM et al., 2003)

I Dynamic power slightly increasesI Power per transistor has reducedI Number of transistor in a chip has

increased

I Gate leakage increases exponentiallyI Controlled through the use of

high-k transistors from 45nm on

I Sub-threshold leakageI Threshold voltage vth depends

exponentially on Vgs − Vth

I Vgs − Vth has reduced in recenttechnologies

I Multi Vth

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Trends on Power Requirements for Mobile on 2004

(NEUVO, 2004)

I There is a gap between battery capacityand power consumption

I Power consumption limit fixed: 3W

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Trends on Power Requirements for Mobile on 2011

(CARBALLO; B., 2011)

I A SoC with 48.8M logic gatesusing low-power techniquesdissipates 3.5W in 2011

I In 2026 the number of gatesgrows to 1995.5M and the powerincreases to 8.22W

I Power consumption limitreviewed: fixed at 2W until 2026

I LOW POWER DESIGNTECHNIQUES ARE OFUTMOST IMPORTANCE!

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Low Power Design Techniques

I Dynamic Power ReductionI Clock gatingI Gate Level Optimization

I Static Power ReductionI Multi Vth

I Total Power ReductionI Multi Vdd

I Power gatingI Dynamic Voltage and Frequency Scaling

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Clock Gating

Impact of Clock Gating


I Pdyn : 12 × CL × V 2

dd × fclock × αI 50% or more dynamic power can be

spent in the clock tree buffers sincethey have high switching activity

I A significant ammount of dynamicpower is dissipated by flip-flops

I Clock gating turns clocks to idlemodules resulting in ZERO activity

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Clock Gating

Clock Gating Within the Synthesis Flow


I Most standard cell libraries includeclock gating cells

I Modern design tools supportautomatic clock gating e.g., SynopsysDesign Compiler

I Small area overhead

I No change to RTL is required toimplement clock gating

I Clock gating is inserted withoutchanging the logic function

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Clock Gating



I Clock tree consumes a lot of dynamicpower

I Trade off between fine andcoarse-grain clock gating

I Fine-grain allows for turning offspecific blocks. It comes at theexpense of more area and skew

I Coarse-grain allows for higherpower savings due to clock buffers.On the other hand, modules cannotbe turned off as often

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Clock Gating



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Clock Gating

Exampe of Clock Gating

(RABAEY, 2009)

I Use of clock gating on an MPEG4decoder

I Gating 90% of flip-flops

I From 30.6mW to 8.5mW: 70% ofdynamic power reduction

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Gate Level Optimization

Impact of Gate Level Optimization


I A number of logic optimizations areperformed during the design flow

I Modern design tools (e.g., SynopsysDesign Compiler) perform a numberof logic optimization so as tooptimize area, power or delay

I Example of techniques are:Technology mapping, logicrestructuring, gate sizing and buffer

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Technology Mapping and logic restructuring

I An AND gate with high activityfollowed by a nor gate can bereplaced by a complex AND-OR gateplus an inverter

I Total number of transistors reducedfrom 10 to 6

I Complex gates present intrinsiccapacitances substantially smallerthat inter-gate routing capacitancesof a network of simple gates.

I A smaller output capacitance reducesthe gate dynamic power

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Reducing Switching Activity

(RABAEY; CHANDRAKASAN; NIKOLIC, 2002)

I Input reordering can effectively reduceswitching activity (for pins with hightransition rate) and thereby dynamicpower

I Even though the activity at pin Z isthe same for both cases, a simplyreordering of inputs can reduceswitching activity by ≈ 78%

I In the first circuit, activity is equal(1− 0.5× 0.2)(0.5× 0.2) = 0.09

I In the second circuit, activity is equal(1− 0.2× 0.1)(0.2× 0.1) = 0.0016

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Gate Sizing and Buffer Insertion


I Gate sizing is an importantoptimization technique used fordifferent objectives. The idea is toselect the size (increase or decreasedrive strength) of the gates so as toreduce the delay on critical paths orreduce power on non critical paths

I In buffer insertion, the tool can insertbuffers rather than increasing thedrive strength of the gate itself

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Gate Sizing and Buffer Insertion


I For example, suppose a target delayof 0.11 ns. Since the initial synthesisachieved a delay of 0.11 ns, somegates can be sized to reduce power

I In the example, simply sizing 4 gatesreduced power by 55%

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Gate Level Optimization Withing the Synthesis Flow


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Multi Vth

Impact of Multi Vth


I Isub = µCoxV2t

WL .e

Vgs−VthnVt

I Ids = µCoxWL .

(Vgs−Vth)2

2

I Sub-threshold leakage dependsexponentially on Vth

I Delay has a much weaker dependence onVth

I Standard cell libraries offer two or threeversions of cells with different Vth

I Modern design tools support automaticVth assignment e.g., Synopsys DesignCompiler

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Multi Vth

Multi Vth Withing the Synthesis Flow


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Multi Vth

Example of Multi Vth

(RABAEY, 2009)

I In a circuit, different paths havedifferent delays.

I A positive slack means that the signalis ready at input of FF before thetarget delay

I One approach would be synthesize forhigh performance using low Vth gatesand then swapping non-critical gatesfor high Vth

I Another approach would besynthesize for low power using highVth gates and then swapping criticalgates for low Vth

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Multi Vth

Example of Multi Vth

(RABAEY, 2009)

I Experiment performed jointly byToshiba and Synopsys to evaluate theimpact of two different Vth

I Using only high-Vth degrades theperformance

I Using only low-Vth increases staticpower 4.2x w.r.t. high-Vth

I The dual-Vth strategy leaves timingand dynamic power unchanged, whilereducing the static power by half w.r.tlow-Vth

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Multi Vdd

Impact of Multi Vdd


I Pdyn = 12 × CL × V 2

dd × fclock × α

I Ids = µCoxWL .

(Vgs−Vth)2

2

I Reducing Vdd provides a quadraticreduction on Pdyn but increases thedelay of gates

I Reduce Vdd on non-critical paths

I Power benefit without compromisingthe system performance

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Multi Vdd

Impact of Multi Vdd


I One challenge of power gating isinterfacing signals between blocks

I A signal from a low-Vdd to ahigh-Vdd block may cause a veryslow transition thereby resulting inlarge short-circuit currents

I A logic ’1’ in low-Vdd may not beenough to achieve ’1’ in high-Vdd

I To overcome such problems, levelshifters are placed between thevoltage islands

I Contemporary standard cell librariesoffer level shifters cells

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Multi Vdd

Impact of Multi Vdd


I Multi Vdd is not performedautomatically by modern design tools

I The choice of voltage islands, as wellas insertion of must be decided by thedesigners

I Other challenges of Multi Vdd includepower planning, timing analysis,voltage regulators, etc

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Multi Vdd

Multi Vdd Withing the Synthesis Flow


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Power Gating

Impact of Power Gating

(RABAEY, 2009)

I Pstat = µCoxV2t

WL .e

Vgs−VthnVt

I Pdyn = 12 × CL × V 2

dd × fclock × αI Static power

I Dissipated even on standby or sleepmode

I Even more important on batterypowered portable devices

I Turning off the power of an idle blockreduces static power to ≈ ZERO

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Power Gating


(RABAEY, 2009)

I The idea is to use on-off switches todisconnect the module from thesupply rails

I Header (PMOS) transistor isconnected to Vdd

I Footer (NMOS) transistor isconnected to GND and is morearea-efficient than PMOS

I Using botyh is more effective inreducing leakage since it exploitsstacking effect independently of theinput patterns

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Power Gating



I Activity profile for a sub-system usingpower gating

I Some information must be retainedduring sleep

I Some flip-flops must retain dataduring sleep mode

I After wakeup the data must berestored

I There is a leakage overhead toretain data during sleep

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Power Gating

Example of Power Gating


I A simplified view of an SoC that usesinternal power gating

I In this example only Vdd is switched,whereas GND is directly provided tothe entire chip

I The power gating controller controlsswitches that provide power to thepower gated block

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Power Gating



I One challenge of power gating isinterfacing signals between blocks

I The signal from/to a power up/downblock must be isolated

I To overcome such problems, isolationcells are placed between the blocks

I Contemporary standard cell librariesprovide isolation cells

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Power Gating



I Another challenge of power gating ishow to retain the internal state of theblock during power down/up

I It is common to use retentionregisters to store the internal state

I The choice of a retention strategyis crucial to determine the amountof time to power down/up, as wellas the leakage consumption duringsleep mode

I Contemporary standard cell librariesprovide retention registers

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Power Gating



I In practice, power gating is achallenging task during the designflow

I Designers must clearly define whichblocks can powered down as well asdefine the power up and power downsequence

I The state retention plan must becarefully studied

I Modern design tools do not placeautomatically isolation cells nor insertretention registers

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Power Gating

Power Gating Withing the Synthesis Flow


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Power Gating

A Real Use Case Example of Power Gating: Salt 90nm


I Implemented in 90nm and containtsan ARM processor

I The idea is to evaluate the impact onpower and performance of using:

I Clock gatingI Power gatingI Different Vdds

I Different clock frequencies

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Power Gating

The Salt SoC


I The project uses four low-powermodes

I Halt turns off the clocks to theprocessor

I Snooze turns off the internal powersupply to the processor with stateretention, but cache memoriesremain powered up. This modeallows fast power up

I Hibernate turns off the externalpower supply to the processor butcache memories remain powered up

I Shutdown turns off the externalpower supply to the processor andcaches

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Power Gating

Power State Machine for Salt

I The project uses four low-powermodes

I Halt turns off the clocks to theprocessor

I Snooze turns off the internal powersupply to the processor with stateretention, but cache memoriesremain powered up. This modeallows fast power up

I Hibernate turns off the externalpower supply to the processor butcache memories remain powered up

I Shutdown turns off the externalpower supply to the processor andcaches

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Power Gating

Measurement and Analysis Post-Silicon of Salt Project


I Evaluate power at different operationmodes

I Nominal Vdd is 1.0v.

I Vdd steps in 10%: from 110% to 70%

I Three different clock frequenciesbeing the nominal 300MHz

I The first three measurements showthe dynamic power for differentfrequencies/Vdds

I Clock gate and Save Restore PowerGating measurements show theleakage power

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Voltage and Frequency Scaling

Dynamic Voltage and Frequency Scaling

(RABAEY, 2009)

I Workload can vary a lot over time

I For instance, the motioncompensation block of a videocompression that computes how mucha video frame differs from theprevious one

I A fast moving car chase scene has alot of computation

I A nature landscape varies little overtime

I The IDCT histogram shows that thecomputational effort can vary 2-3orders of magnitude

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Dynamic Voltage and Frequency Scaling

(RABAEY, 2009)

I Adjusting only the frequency reducespower but leaves the energy peroperation unchanged

I Therefore, the amount of work thatcan be performed by the batteryremains the same

I A more effective way of exploiting theworkload variation is to adjustsimultaneously frequency and supplyvoltage

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Dynamic Voltage and Frequency Scaling (DVFS)

(RABAEY, 2009)

I Impact on dynamic and static powerI Pdyn : 1

2× CL × V 2

dd × fclock × αI Isub = µCoxV

2t

WL.e

Vgs−VthnVt

I Ids = µCoxWL.

(Vgs−Vth)2

2

I The idea is to dynamically adjust thevoltage and frequency of blockaccording to the workload

I Dynamic Voltage and FrequencyScaling has a set of voltage andfrequency values that are dynamicallyswitched

I DVFS not only reduces power butreduces the energy per operation aswell

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Voltage and Frequency Scaling Opportunity using DVFS)


I Pdyn : 12 × CL × V 2

dd × fclock × αI There is a a region of operation where

frequency increases monotonicallyover voltage within some limits

I Maximum voltage specified for thetechnology (process)

I Minimum voltage in which thecircuitry runs safe

I Therefore, the designer can exploredifferent pairs (Vdd , fclock) duringdesign time

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Power and Energy Reduction Oportunities using DVFS)


I Pdyn : 12 × CL × V 2

dd × fclock × αI There is a different power dissipation

relationship between reducingfrequency with and without reducingsupply voltage

I The gap between the two curvesequals the power saving achievablebetween the minimum and maximumoperating voltages

I DVFS allows more than a liner powerreduction

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Power and Energy Reduction Oportunities using DVFS)


I Pdyn : 12 × CL × V 2

dd × fclock × αI Energy is the integration of power

over the time taken to complete atask

I Ignoring leakage, reducing frequencyat half, halves the dynamic power buttakes twice as long to complete thetask

I Scaling voltage reduces quadraticallythe dynamic power, allowing toreduce energy as well

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A Real Use Case Example of DVFS: ULTRA926 130nm


I A chip using an ARM processordeveloped in conjuction with Synopsys

I It uses a nominal supply voltage of1.2V

I The idea is to evaluate the energysavings of applying DVFS

I Other low power techniques are alsoused such as power gating and clockgating

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A Real Use Case Example of DVFS: ULTRA926 130nm


I Histogram plotting the energyconsumption data for different pairs(Vdd , fclock)

I From 60% to 110% of max 1.2V.From 50% to 100% of max 288MHz

I Some pairs fail to attend the requiredperformance e.g., (0.72V, 192MHz),(0.78V, 240MHz)

I Note only scaling frequency results inalmost the same energy value

I It is possible to observe aclose-to-linear energy relationship fordifferent voltage ranges

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References I

CARBALLO, J.-A.; B., K. A. Itrs chapters: Design and system drivers. In: Future FabInternational (36). [S.l.: s.n.], 2011. p. 45–48.

CHINNERY, D.; KEUTZER, K. Closing the power gap between ASIC & custom: toolsand techniques for low power design. [S.l.]: Springer, 2008.

KEATING, M. et al. Low power methodology manual: for system-on-chip design. [S.l.]:Springer Publishing Company, Incorporated, 2007.

KIM, N. S. et al. Leakage current: Moore’s law meets static power. Computer, v. 36, p.68–75, December 2003.

NEUVO, Y. Cellular phones as embedded systems. In: IEEE. Solid-State CircuitsConference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International. [S.l.], 2004.p. 32–37.

RABAEY, J. Low power design essentials. [S.l.]: Springer, 2009.

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References II

RABAEY, J. M.; CHANDRAKASAN, A. P.; NIKOLIC, B. Digital integrated circuits.[S.l.]: Prentice hall Englewood Cliffs, 2002.

SAMSUNG. Exynos 5 Dual. 2014. Disponıvel em: 〈http://www.samsung.com/global/business/semiconductor/product/application/detail?productId=7668〉.

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http://www.samsung.com/global/business/semiconductor/product/application/detail?productId=7668

http://www.samsung.com/global/business/semiconductor/product/application/detail?productId=7668


Low Power Techniques for SoC Design:basic concepts and techniques

Estagiario de DocenciaM.Sc. Vinıcius dos Santos Livramento

Prof. Dr. Luiz Claudio Villar dos Santos

Embedded Systems - INE 5439Federal University of Santa Catarina

September, 2014

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low power techniques for soc design: basic concepts and...

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