low power, multi-gigabit dram cell design issues using soi technology

Fred Chen & Lixin Su Fred Chen & Lixin Su SOI DRAMSOI DRAM

Low Power, Multi-Gigabit DRAM Cell Low Power, Multi-Gigabit DRAM Cell Design Issues Using SOI TechnologyDesign Issues Using SOI Technology

Fred Chen & Lixin Su

May 12, 1999

A Presentation for EE241 Term ProjectDepartment of Electrical Engineering and Computer Sciences

University of California at Berkeley


Outline of the ProjectOutline of the Project

• Background Study– SOI Technology– Low Power DRAM Design

• DRAM Conceptual Design Using SOI– Spice3 for SOI Simulation– Simulations/Results/Conclusions

• Summary and Future Work


SOI Technology for DRAMSOI Technology for DRAM

Fully Depleted (FD) Partially Depleted (PD)

Dynamically Depleted (DD)

Tbox

Substrate

Body

Source DrainDepletion

GateVs

Vg Vd

Tox

TsiVbVp

Vbg



Low Power• Small channel leak for same drivability (1)

• Junction leak reduction (3)

• Charge/discharge current reduction (2)

• Body control current reduction (6)

Related SOI Features

(1) Small S-factor (4) Small substrate bias effect

(2) Small Junction Cap. (5) Complete body isolation

(3) Small Junction Area (6) Small Body Cap.

Low Voltage • High drive capability for same leak (1)

• Large cell readout signal (2)

• High speed operation (2) (4)

• Large high-data write margin (4)

• Easy to apply body control (5)

Source: Shimomura et al., JSSC vol. 32, No. 11, Nov. 1997



What Else? There’s more? :

• Reduced Second Order Effects– Radiation hardened: Almost Soft Error Free

• Cs reduced AREA reduced

– Free from latchup

• Disadvantages:– Floating body effect

– Self-heating effect

• Solution: – Body control through body contact schemes

– Fully depleted SOI


Spice3 for SOI SimulationSpice3 for SOI Simulation

• Source: UC Berkeley Device Group

• Versions: BSIMPD2.0 & BSIMPD2.0.1 & BSIMFD2.0 & BSIMDD2.0

BSIM3SOI1.3

• Model Card: {PD,DD,FD} x {PMOS, NMOS}

• Spice3 Limitations: – Restricted .subckt & !.param => ! Sweep/Change MOS Parameter

– !.measure => Extra Data Processing

• Need to Improve Work Efficiency!


Spice3 for SOI SimulationSpice3 for SOI Simulation

• Simulation Flow:

Perl

Spice Deck

Parameters

Results

Spice

Model Card

Script Switch

PD DD FDSpice 3 Simulation Engine


Ids vs. Vgs vs. Technology

1.00E-29

1.00E-27

1.00E-25

1.00E-23

1.00E-21

1.00E-19

1.00E-17

1.00E-15

1.00E-13

1.00E-11

1.00E-09

1.00E-07

1.00E-05

1.00E-03

1.00E-01-1.00E+00 -5.00E-01 0.00E+00 5.00E-01 1.00E+00 1.50E+00 2.00E+00

Vgs (V)

Ids

(A

)

Ids (FD)

Ids (PD)

Ids (PD Float)

Ids (Bulk)Bulk (S ~ 100mV/decade)

FD (S ~ 60mV/decade)

PD, Fixed body (S ~ 70mV/decade)

PD, f loating body (S ~ 70mV/decade)

Single Transistor SOI: The S-FactorSingle Transistor SOI: The S-Factor


Single Transistor SOI: The S-FactorSingle Transistor SOI: The S-Factor

SOI Ids vs. Vgs. Over Temperature

1.00E-29

1.00E-27

1.00E-25

1.00E-23

1.00E-21

1.00E-19

1.00E-17

1.00E-15

1.00E-13

1.00E-11

1.00E-09

1.00E-07

1.00E-05

1.00E-03

1.00E-01

1.00E+01

-1.00E+00 -5.00E-01 0.00E+00 5.00E-01 1.00E+00 1.50E+00 2.00E+00

Vgs (V)

Ids

(A

)

PD(27)

PD(100)

PD(200)

FD(27)

FD(100)

FD(200)

FD @ 27 C: S = 60mV/dec FD @ 100 C: S = 75mV/dec

FD @ 200 C: S = 100mV/dec

PD @ 27 C: S = 70mV/decPD @ 100 C: S = 95mV/dec

PD @ 200 C: S = 125mV/dec

BULK @ 27C: 100mV /dec!


Single Transistor SOI: The KinkSingle Transistor SOI: The KinkSOI PD Drain Current(Vbs) vs. Vgs

0.00E+00

5.00E-05

1.00E-04

1.50E-04

2.00E-04

2.50E-04

0.00E+00 2.00E-01 4.00E-01 6.00E-01 8.00E-01 1.00E+00 1.20E+00 1.40E+00 1.60E+00 1.80E+00 2.00E+00

Vgs (V)

Ids

(A

)

Ids (-1)

Ids (-0.5)

Ids (0)

Ids (0.5)

Ids (1)

Ids (float)Kink Effect !


Single Transistor SOI: Single Transistor SOI: Pass Gate Leakage Current Pass Gate Leakage Current

0v

1.5v

1.5v

0v

???


Low Power DRAM DesignLow Power DRAM Design

• Typical large scale low power architectures– Multi-divided data lines– Shared sense amplifiers– Divided word lines

• Reduce CB, reduce CB!

• Half-Vdd pre-charge

• Boosted sense ground

• SOI


DRAM: Comparison SchemeDRAM: Comparison Scheme

• Technology Comparison– Use identical architectures– Match relative performance of each technology

model– Use single cell comparison (with SA)– Compare DRAM metrics for each technology


DRAM SOI: Cell & Sense AmplifierDRAM SOI: Cell & Sense Amplifier

ar

p Vdd/2

D

Dbar

W

Wbar

Wr

WL CellDummy

Cell


DRAM SOI: Control SignalsDRAM SOI: Control Signals

phip

phia

phir

wr

w

wbar

wlWrite 0 Read/RestoreWrite 1


Reading a "0", Bulk vs. SOI (256 rows)

-2.00E-01

0.00E+00

2.00E-01

4.00E-01

6.00E-01

8.00E-01

1.00E+00

7.50E-08 8.00E-08 8.50E-08 9.00E-08 9.50E-08 1.00E-07

Time (s)

Vo

lta

ge

s (

V)

BL (FD SOI)

v(cnode)

v(phia)

v(phir)

v(w l)

BL (Bulk)

Cell node (Bulk)

BL (PD)

Cell Node (PD)

Bulk

FD SOI

Word Line

PD SOI

DRAM SOI: Bit-Line CapacitanceDRAM SOI: Bit-Line Capacitance


Simulation ResultsSimulation Results

Body Bias in PD SOI , Reading a "1"

-2.00E-01

0.00E+00

2.00E-01

4.00E-01

6.00E-01

8.00E-01

1.00E+00

3.00E-08 3.20E-08 3.40E-08 3.60E-08 3.80E-08 4.00E-08 4.20E-08 4.40E-08

Time (s)

Vo

lta

ge

s (

V)

Cell (Body Float)v(w l)v(phia)v(phir)Cell (Body Fixed)BL (Body Control)Cell (Body Control)BL (FD)Cell (FD)

FD

Body Control

Body Fixed

Floating Body

Cell

Bit Line


Round 1: Bulk vs. SOI

(Ind. Models) Bulk PD SOI FD SOI

Cs 25 fF 25 fF 25 fF

CB (256 Rows) 114 fF 42 fF 13fF!

Vsense 90 mV 186 mV 265 mV

VD 0.5V 0.5V 0.5V

CAS to DataOut 10ns 9.8ns 9.1ns

Ileakage (0V)/Cell 1.0034pA 1.634 pA 2.44pA

Ileakage (-.5V)/Cell 1pA 1e-14 A 9.1e-21A


Round 2: PD vs. FD

(Spice 1.3) PD (float) PD (fixed) PD (active) FD

CAS toDataOut

10.5ns 10.8ns 9.8ns 9.5ns

Pavg 7.5 uW 6.59 uW 9.27uW 3.97uW

Ileakage (0)/cell 2.91 pA 2.21 pA 2.21 pA 2.44 pA

Istandby (-0.5)/cell 8.93e-19 A 5.76e-19 A 5.76e-19 A 1.34 e-20 A


ConclusionsConclusions

Performance:

FD PD-ActB PD-FltB PD-FixB

High Low

Power:

FD PD-FixB PD-FltB PD-ActB

Low High


PD vs. FD Tradeoffs

• Which to choose for DRAM?– Fully Depleted SOI

• Pros: Low Power, Low CJ, low S-factor, no body contact needed, less sensitive to temperature variation

• Cons: Manufacturability, sensitivity to process variation

– Partially Depleted (floating body)• Pros: Easy to manufacture

• Cons: Floating body

– Inside PD: body contact tradeoffs, see last slide


Work Done & Future WorkWork Done & Future Work

• Work Done:– Single transistor characterization for SOI

– Comparison between bulk/different SOI body contact schemes for DRAM cell design

• Future Work:– More SOI simulation of each component of DRAM – More SOI simulation to study coupling effect, standby

current, & pass gate leakage current

– Voltage scaling & transistor sizing with SOI

low power, multi-gigabit dram cell design issues using soi technology

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