low noise amplifiers - cppsim · 2013-08-11 · bias i out source l deg 4. ... we now know the...

M.H. Perrott

High Speed Communication Circuits and SystemsLecture 9

Low Noise Amplifiers

Michael H. PerrottMarch 3, 2004

Copyright © 2004 by Michael H. PerrottAll rights reserved.

1

M.H. PerrottM.H. Perrott

Narrowband LNA Design for Wireless Systems

Design Issues- Noise Figure – impacts receiver sensitivity- Linearity (IIP3) – impacts receiver blocking performance- Gain – high gain reduces impact of noise from components

that follow the LNA (such as the mixer)- Power match – want Zin = Zo (usually = 50 Ohms) - Power – want low power dissipation- Bandwidth – need to pass the entire RF band for the

intended radio application (i.e., all of the relevant channels)- Sensitivity to process/temp variations – need to make it

manufacturable in high volume

Zin

Zo LNATo Mixer

From Antennaand Bandpass

Filter

PC boardtrace

PackageInterface

2


Our Focus in This Lecture

Designing for low Noise Figure Achieving a good power match Hints at getting good IIP3 Impact of power dissipation on design Tradeoff in gain versus bandwidth

Zin

Zo LNATo Mixer

From Antennaand Bandpass

Filter

PC boardtrace

PackageInterface

3


Our Focus: Inductor Degenerated Amp

Same as amp in Lecture 7 except for inductor degeneration- Note that noise analysis in Tom Lee’s book does not include

inductor degeneration (i.e., Table 11.1)

vgs gmvgsCgs indgZgs

Rsens

Sourceinout

Lg

M1

Ldeg

LgRs

vin

Vbias

IoutSource

Ldeg

4


Recall Small Signal Model for Noise Calculations

Iout

GD

Svgs gmvgsCgs indg

D

S

G

ZgsZg

Zdeg

iout

Zg Zdeg

5


Input impedance (from Lec 6)

Set to achieve pure resistance = Rs at frequency wo

Key Assumption: Design for Power Match

M1

Vbias

vinRs

Ldeg

ZinIout

Lg

Real!

6


Process and Topology Parameters for Noise Calculation

Process parameters- For 0.18 CMOS, we will assume the following

Circuit topology parameters Zg and Zdeg


Rsens

Sourceinout

Lg

Ldeg

7


Calculation of Zgs


Rsens

Sourceinout

Lg

Ldeg

8


Calculation of


Rsens

Sourceinout

Lg

Ldeg

= Rs

9


Calculation of Zgsw

By definition

Calculation

10


Calculation of Output Current Noise

Step 3: Plug in values to noise expression for indg

11


From Lecture 7, we derived for Ldeg = 0, wo2 = 1/(LgCgs)

We now have for (gm/Cgs)Ldeg = Rs, wo2 = 1/((Lg + Ldeg)Cgs)

Compare Noise With and Without Inductor Degeneration


Rsens

Sourceinout

Lg

Ldeg

12


Recall the alternate expression for Noise Factor derived in Lecture 8

We now know the output noise due to the transistor noise- We need to determine the output noise due to the source

resistance

Derive Noise Factor for Inductor Degenerated Amp


Rsens

Sourceinout

Lg

Ldeg

13


Output Noise Due to Source Resistance


Rsens

Sourceinout

Lg

Ldeg

Zin

14


Noise Factor for Inductor Degenerated Amplifier

Noise Factor scaling coefficient15


Noise Factor Scaling Coefficient Versus Q

1 1.5 2 2.5 3 3.5 4 4.5 52.5

3

3.5

4

4.5

5

5.5

6

6.5

7

Q

Noi

se F

acto

r Sca

ling

Coe

ffici

ent

Noise Factor Scaling Coefficient Versus Q for 0.18 μ NMOS Device

Achievable values asa function of Q underthe constraints that

(Lg+Ldeg)Cgs

1= wo

Ldeg = RsCgs

gm

2RswoCgs

1Q =Note:

c = -j0

c = -j0.55

c = -j1

16


Achievable Noise Figure in 0.18 with Power Match

Suppose we desire to build a narrowband LNA with center frequency of 1.8 GHz in 0.18 CMOS (c=-j0.55)- From Hspice – at Vgs = 1 V with NMOS (W=1.8, L=0.18)

measured gm =871 S, Cgs = 2.9 fF

- Looking at previous curve, with Q ≈ 2 we achieve a Noise Factor scaling coefficient ≈ 3.5

17


Component Values for Minimum NF with Power Match

Assume Rs = 50 Ohms, Q = 2, fo = 1.8 GHz, ft = 47.8 GHz- Cgs calculated as

- Ldeg calculated as

- Lg calculated as

18


Have We Chosen the Correct Bias Point? (Vgs = 1V)

M1

IdVgs

WL = 1.8μ

0.18μ

0 100 200 300 400 500 600 7000

0.5

1

1.5

2

2.5

3

3.5

4

4.5

Current Density (microAmps/micron)

g m a

nd g

do (m

illiA

mps

/Vol

ts) a

nd V

gs (V

olts

)

Vgs , gm , and gdo versus Current Density for 0.18μ NMOS

gm

gdo

Vgs

Chosen biaspoint is Vgs = 1 V

Lower powerLower ft

Lower IIP3

Higher powerHigher ft

Higher IIP3gdogm

gdogm

Lower Higher

Note: IIP3 is also a function of Q19


Calculation of Bias Current for Example Design

Calculate current density from previous plot

Calculate W from Hspice simulation (assume L=0.18 m)

- Could also compute this based on Cox value Calculate bias current

- Problem: this is not low power!!

20


We Have Two “Handles” to Lower Power Dissipation

Key formulas

Lower current density, Iden- Benefits

- Negatives

Lower W- Benefit: lower power- Negatives

21


First Step in Redesign – Lower Current Density, Iden

M1

IdVgs

WL = 1.8μ

0.18μ

0 100 200 300 400 500 600 7000

0.5

1

1.5

2

2.5

3

3.5

4

4.5

Current Density (microAmps/micron)

g m a

nd g

do (m

illiA

mps

/Vol

ts) a

nd V

gs (V

olts

)

Vgs , gm , and gdo versus Current Density for 0.18μ NMOS

gm

gdo

Vgs

New biaspoint is Vgs = 0.8 V

Need to verify that IIP3 still OK (once we know Q)22


Recalculate Process Parameters

Assume that the only thing that changes is gm/gdo and ft- From previous graph (Iden = 100 A/ m)

We now need to replot the Noise Factor scaling coefficient- Also plot over a wider range of Q

Noise Factor scaling coefficient

23


Update Plot of Noise Factor Scaling Coefficient

1 2 3 4 5 6 7 8 9 102

4

6

8

10

12

14

16

18

Q

Noi

se F

acto

r Sca

ling

Coe

ffici

ent

Noise Factor Scaling Coefficient Versus Q for 0.18 μ NMOS Device

Achievable values asa function of Q underthe constraints that

(Lg+Ldeg)Cgs

1= wo

Ldeg = RsCgs

gm

2RswoCgs

1Q =Note:c = -j0

c = -j0.55

c = -j1

24


Second Step in Redesign – Lower W

Recall

Ibias can be related to Q as

We previously chose Q = 2, let’s now choose Q = 6- Cuts power dissipation by a factor of 3!- New value of W is one third the old one

25


Power Dissipation and Noise Figure of New Design

Power dissipation

- At 1.8 V supply

Noise Figure- ft previously calculated, get scaling coeff. from plot

26


Updated Component Values

Assume Rs = 50 Ohms, Q = 6, fo = 1.8 GHz, ft = 42.8 GHz- Cgs calculated as

- Ldeg calculated as

- Lg calculated as

27


Inclusion of Load (Resonant Tank)

Add output load to achieve voltage gain- Note: in practice, use cascode device

We’re ignoring Cgd in this analysis

M1

Ldeg

LgRs

vin

Vbias

LL RL CL

VoutIout


Rsens

inout

Lg

Ldeg

vin

iout

LL RL CL

vout

Zin

28


Calculation of Gain

Assume Zin = Rs

Assume load tank resonates at frequency wo


Rsens

inout

Lg

Ldeg

vin

iout

LL RL CL

vout

Zin

29


Setting of Gain

Parameters gm and Q were set by Noise Figure and IIP3 considerations- Note that Q is of the input matching network, not the

amplifier load RL is the free parameter – use it to set the desired gain- Note that higher RL for a given resonant frequency and

capacitive load will increase QL (i.e., Q of the amplifier load) There is a tradeoff between amplifier bandwidth and gain

- Generally set RL according to overall receiver noise and IIP3 requirements (higher gain is better for noise) Very large gain (i.e., high QL) is generally avoided to

minimize sensitivity to process/temp variations that will shift the center frequency

30


The Issue of Package Parasitics

Bondwire (and package) inductance causes two issues- Value of degeneration inductor is altered- Noise from other circuits couples into LNA

M1

Ldeg

LextRs

vin

Vbias

LL RL CL

Vout

Lbondwire1

Mixer andOther Circuits

NoiseCurrent

NoiseCurrent

Lbondwire2

Lbondwire3

EquivalentSource

NoiseVoltage

NoiseVoltage

31


Differential LNA

Advantages- Value of Ldeg is now much better controlled- Much less sensitivity to noise from other circuits

Disadvantages- Twice the power as the single-ended version- Requires differential input at the chip

M1Ldeg

LgRs

vin

Vbias

LL RL CL

Vout

M2

LLRLCL

Vout

Ibias

Ldeg

Lg Rs

2-vin

2

32


Note: Be Generous with Substrate Contact Placement

Having an abundance of nearby substrate contacts helps in three ways- Reduces possibility of latch up issues- Lowers Rsub and its associated noise

Impacts LNA through backgate effect (gmb)- Absorbs stray electrons from other circuits that will otherwise inject noise into the LNA

Negative: takes up a bit extra area

S DG

SubstrateContact

SubstrateContact

GND

P-

GND

N+ N+

RsubRsub

To Ldeg To LgTo amplifer

load

Hot electrons andother noise

Hot electrons andother noise

enRsub enRsub

33


Another CMOS LNA Topology

Consider increasing gm for a given current by using both PMOS and NMOS devices- Key idea: re-use of current

Issues- PMOS device has poorer transconductance than NMOS for a given amount of current, and ft is lower- Not completely clear there is an advantage to using this technique, but published results are good See A. Karanicolas, “A 2.7 V 900-MHz CMOS LNA and

Mixer”, JSSC, Dec 1996

M1

M2

M1

Id

W/L

M2

Id/2

M1

Id/2

(1/2)W/L (1/2)W/L

Id

gm

gm1+gm2

gm1+gm2

Id/2

Id/2

(1/2)W/L

(1/2)W/L

34


Biasing for LNA Employing Current Re-Use

PMOS is biased using a current mirror NMOS current adjusted to match the PMOS current Note: not clear how the matching network is achieving

a 50 Ohm match- Perhaps parasitic bondwire inductance is degenerating

the PMOS or NMOS transistors?

M2

M1

Cbig2

Ibias

Rbig1M4

Rbig2

M3 opampVref

Cbig3Cbig1

MatchingNetwork

Vrf

Vout1 Vout2

Stage 1 Stage 2

35


Another Recent Approach

Feedback from output to base of transistor provides another degree of freedom

For details, check out:- Rossi, P. et. Al., “A 2.5 dB NF Direct-Conversion

Receiver Front-End for HiperLan2/IEEE802.11a”, ISSCC 2004, pp. 102-103

Q1

Ldeg

Rs

vin

LL RL CL

Vout

α

α < 1

Cbypass

36


Broadband LNA Design

Most broadband systems are not as stringent on their noise requirements as wireless counterparts

Equivalent input voltage is often specified rather than a Noise Figure

Typically use a resistor to achieve a broadband match to input source- We know from Lecture 8 that this will limit the noise figure

to be higher than 3 dB For those cases where low Noise Figure is important,

are there alternative ways to achieve a broadband match?

Zin

Zo LNA

PC boardtrace

PackageInterface

High SpeedBroadband

Signal

37


Recall Noise Factor Calculation for Resistor Load

Total output noise

Total output noise due to source

Noise Factor

vin

Rs

RL

Source

vout

enRs

enRL

Rs

RL

Source

vnout

38


Noise Figure For Amp with Resistor in Feedback

Total output noise (assume A is large)

Total output noise due to source (assume A is large)

Noise Factor

Vin

Rs

RfSource

Vout

enRs

AVref

Rs

RfSource

VnoutA

enRf

incrementalground

39


Input Impedance For Amp with Resistor in Feedback

Recall from Miller effect discussion that

If we choose Zin to match Rs, then

Therefore, Noise Figure lowered by being able to choose a large value for Rf since

enRsRs

RfSource

VnoutA

enRf

Zin

40


Example – Series-Shunt Amplifier

Recall that the above amplifier was analyzed in Lecture 5

Tom Lee points out that this amplifier topology is actually used in noise figure measurement systems such as the Hewlett-Packard 8970A- It is likely to be a much higher performance transistor

than a CMOS device, though

M1

Vbias

vinvout

Rf

R1

Rs

RL

Rin Rout

vx

41


Recent Broadband LNA Approaches

Can create broadband matching networks using LC-ladder filter design techniques

CMOS example:

See Bevilacqua et. al, “An Ultra-Wideband CMOS LNA for 3.1 to 10.6 GHz Wireless Receivers”, ISSC 2004, pp. 382-383

M1

Ldeg

LgRs

vin

Vbias

LL

RL

Cp

Vout

Vbias2M2

C2

C1

L2

L1

Ibias

M3

42


Recent Broadband LNA Approaches (Continued)

Bipolar example:

See Ismail et. al., “A 3 to 10 GHz LNA Using a Wideband LC-ladder Matching Network”, ISSCC 2004, pp. 384-385

Ldeg

Rs

vin

Vbias

LL

RL

VoutVbias2

C2

L1

M3

Q1Ldeg2

Vbias3

C3

Q2

C1

R1

C4

43

low noise amplifiers - cppsim · 2013-08-11 · bias i out source l deg 4. ... we now know the...

Documents