LoopBusterHardware Loop Detection in Fast

Mesh Ethernet Networks

Uriel Peled and Tal Kol

Guided by Boaz MizrahiAdvised by Gideon Kaempfer

Digital Systems LaboratoryDigital Systems LaboratoryFaculty of Electrical Engineering, TechnionFaculty of Electrical Engineering, TechnionWinter 2007 – Winter 2008Winter 2007 – Winter 2008

Mid-Semester PresentationMid-Semester Presentation

LoopBuster ReminderStop Ethernet Loops Without Tree Topology

A B

C

LoopBuster

Presentation OutlineMajor Status Updates

1. Software SimulationsSoftware simulation environmentParameter selection

2. General ArchitectureBlock diagram

3. Board selection

What’s Ahead?

Re-visit the project timeline

Preliminary step before diving into hardware

Implement algorithm in softwareProve that it works in concept

Simulate real traffic rates (2Gbps) and data

Recordings from real networks (PCAP)

Simulate connectivity to real computers

Virtual stations using VMWareLive real stations (over Ethernet)

Software SimulationGoals and Demands

Simulation Architecture

Software Simulation

Hosting PC

LoopBuster

LBP Switch

PCAP Generator Pinger

Physical Computer

VMWare Computer

PCAP ProxyPCAP Proxy

LBP Switch

LBP Switch

Pinger

Minimal HWOnly 1 PC

Written in C++

Fast

5K lines of code

SW TimelineSupports any desired rate

Flexible topology

Choose the devices and how they connect

Parameter Selection

Choose filter number and sizesFor example: 13,12,10,10,9,9,8,8,7,7,6

Empirical selection with generic algorithm

Genetic representation: filter size list

Fitness function: memory size, false positives in SW simulation

3 levels of mutation

Theoretical selectionMathematical probability analysis (occupancy problem)

Numerical solution in C++

Surprisingly similar results (15%-30%)

ArchitectureBoard Block Diagram

FPGAPHY

Rocket I/Ointerface

Ethernet RJ45 Rocket

I/OPHY

Ethernet RJ45Rocket

I/O

Rocket I/Ointerface

UARTRS232

UART Interface

ArchitectureGeneral Block Diagram

Packet Remover

Network Stack(in)

LoopBuster Array

LoopBuster Controller

Config and Statistics

Packet Remover

Network Stack(out)

Data Rx[2]

Control Rx[2]

Data Rx[2]

Control Rx[2]

Suspect[2][N+1]

Data Tx[2]

Control Tx[2]

Configs and Statistics[2]Configs and StatisticsConfigs and Statistics[2]

Control[X+1][N+1] Memory Reset[X+1][N+1]

Config[X+1][N+1]

LoopBuster Array has N LoobBustersEach LoopBuster has max X Filters

Configs and Statistics[2]

Ethernet RJ45

Ethernet RJ45

UARTRS232

FPGAPHY

Rocket I/Ointerface

Ethernet RJ45 Rocket

I/OPHY

Ethernet RJ45Rocket

I/O

Rocket I/Ointerface

UARTRS232

UART Interface

Network StackBlock Diagram

Packet Remover

Network Stack(in)

LoopBuster Array

LoopBuster Controller

Config and Statistics

Packet Remover

Network Stack(out)

Data Rx[2]

Control Rx[2]

Data Rx[2]

Control Rx[2]

Suspect[2][N+1]

Data Tx[2]

Control Tx[2]

Configs and Statistics[2]Configs and StatisticsConfigs and Statistics[2]

Control[X+1][N+1] Memory Reset[X+1][N+1]

Config[X+1][N+1]

LoopBuster Array has N LoobBustersEach LoopBuster has max X Filters

Configs and Statistics[2]

Ethernet RJ45

Ethernet RJ45

UARTRS232

PHY

Ethernet 1000BA

SE-X PCS/PMA

CORE

Rocket I/Ointerface

GMII

Control(MDIO)

Ethernet RJ45 Packet

Control

Data Rx

Control Rx

Data Tx

Control Tx

Statistics

RocketI/O

LoopBuster ArrayBlock Diagram

Packet Remover

Network Stack(in)

LoopBuster Array

LoopBuster Controller

Config and Statistics

Packet Remover

Network Stack(out)

Data Rx[2]

Control Rx[2]

Data Rx[2]

Control Rx[2]

Suspect[2][N+1]

Data Tx[2]

Control Tx[2]

Configs and Statistics[2]Configs and StatisticsConfigs and Statistics[2]

Control[X+1][N+1] Memory Reset[X+1][N+1]

Config[X+1][N+1]

LoopBuster Array has N LoobBustersEach LoopBuster has max X Filters

Configs and Statistics[2]

Ethernet RJ45

Ethernet RJ45

UARTRS232

Control

CRCCRC

LoopBuster MLTT 1..N

LoopBuster Broadcast

Data Pipe

Data Rx[2]

Control Rx[2]

Data Rx[2]

Control Rx[2]

Signature[2]

ControlControl Rx[2]

Data Rx[2]

Control Rx[2]

Enable[2]

Control[X+1][N]

Memory Reset[X+1][N]

Statistics[X+1][N]Config[X+1][N]

Statistics[1][1]Signature[2]

Enable[2]

Control[1][1]

Memory Reset[1][1]

Config[1][1]

Suspect[2]

Enable[2]

Suspect[2]

Enable[2]

LoopBusterBlock Diagram

Enable[2]

Filter1

Statistics

Control

MemoryReset

Config

Filter2 FilterX Hash

Suspect[2]

Statistics Statistics Statistics

Enable[2] Enable[2] Enable[2]

Control

MemoryReset

Config Control

MemoryReset

ConfigControl

MemoryReset

Config

Signature[2]

Suspect[2]

Signature[2]

Suspect[2]

Signature[2]

Suspect[2]

Signature[2]

Suspect[2]

Enable[2]

Control

CRCCRC

LoopBuster MLTT 1..N

LoopBuster Broadcast

Data Pipe

Data Rx[2]

Control Rx[2]

Data Rx[2]

Control Rx[2]

Signature[2]

ControlControl Rx[2]

Data Rx[2]

Control Rx[2]

Enable[2]

Control[X+1][N]

Memory Reset[X+1][N]

Statistics[X+1][N]

Config[X+1][N]

Statistics[1][1]Signature[2]

Enable[2]

Control[1][1]

Memory Reset[1][1]

Config[1][1]

Suspect[2]

Enable[2]

Suspect[2]

Enable[2]

LoopBuster ControlBlock Diagram

Packet Remover

Network Stack(in)

LoopBuster Array

LoopBuster Controller

Config and Statistics

Packet Remover

Network Stack(out)

Data Rx[2]

Control Rx[2]

Data Rx[2]

Control Rx[2]

Suspect[2][N+1]

Data Tx[2]

Control Tx[2]

Configs and Statistics[2]Configs and StatisticsConfigs and Statistics[2]

Control[X+1][N+1] Memory Reset[X+1][N+1]

Config[X+1][N+1]

LoopBuster Array has N LoobBustersEach LoopBuster has max X Filters

Configs and Statistics[2]

Ethernet RJ45

Ethernet RJ45

UARTRS232

Control Memory Reset

Config

Filter Control1

Filter Control2

Filter ControlX

Hash Control

Reset Control

Config

Control Control Control

Config Config Config

Config and StatisticsBlock Diagram

Packet Remover

Network Stack(in)

LoopBuster Array

LoopBuster Controller

Config and Statistics

Packet Remover

Network Stack(out)

Data Rx[2]

Control Rx[2]

Data Rx[2]

Control Rx[2]

Suspect[2][N+1]

Data Tx[2]

Control Tx[2]

Configs and Statistics[2]Configs and StatisticsConfigs and Statistics[2]

Control[X+1][N+1] Memory Reset[X+1][N+1]

Config[X+1][N+1]

LoopBuster Array has N LoobBustersEach LoopBuster has max X Filters

Configs and Statistics[2]

Ethernet RJ45

Ethernet RJ45

UARTRS232

UART Core

Config Statistics

UARTRS232

Write Read

Config Config Config Statistics Statistics Statistics

UART Interface

Identify problematic board requirements

Two 1Gbps Ethernet ports

Try to rely on existing equipment

Several alternatives exploredCompletely new board (~$1000)Daughter card for existing board (~$500)SFP modules for existing board (~$200)Develop daughter card (~$2000)

Board SelectionThe Process

Board SelectionSelected Board

Memec FF1152 Xilinx Virtex-II Pro

Existing in lab ($0)

2 SFP Modules1Gbps Eth. RJ45

Buy (~$200)

PCS/PMA CoreRequired for SFP

Free from Xilinx ($0)

Project MilestonesPRELIMINARY DESIGNsoftware simulation(50), LB parameters(50), architecture(50), hardware design(50), hardware layout(50)

1/12/07

1/11/08

1/2/08

1/5/08

1/7/08

250hr

300hr

200hr

500hr

DETAILED DESIGNmicro architecture(100), logic implementation(100), logic simulation(100)

PRODUCTIONsynthesis(100), circuit mechanics(50), circuit production(50)

BRINGUPLB software driver(100), chip debug(200), circuit debug(100)

Status

Today (10.1.08)Completing preliminary designStarting micro architecture

End-Semester PresentationExpecting middle of detailed design

Micro architecture ready

Logic implementation started