logical design of digital systems - uni-due.de · sn54173, sn54ls173a, sn74173, sn74ls173a 4-bit...

Copyright (C) 2016, Faculty of Engineering, Institute of Computer Engineering

Universität Duisburg-Essen

PRACTICAL TRAINING TO THE LECTURE

Experiment 1

Data-traffic in digital circuits Bus circuits

Logical Design of Digital Systems

Name: Matriculation-Number:

First Name: Group-Number:

Tutor: Date:

Antestat: Lab:

Dr.-Ing. Stefan Werner Universität Duisburg-Essen

Faculty of Engineering, Department Electrical Engineering and Information Technology Computer Engineering

All questions marked with Q1 to Qn must be answered before the lab begins. All tasks marked with T1 till Tn must be completed to finish the lab.

Logical Design of Digital Systems Experiment 1: data-traffic in digital circuits

Copyright (C) 2016, Faculty of Engineering, Institute of Computer Engineering 1/14

1.1 Introduction

Bus lines (BUS) are often used for handling data traffic between components in digital circuits. A bus is a theoretical summary of numerous individual lines that fulfill the same functions, e.g. 8 data lines in a microcomputer are considered as a bus. The notion BUS serves the easier handling of such line complexes. Several data transmitters and data receivers can be connected to a bus, which can communicate with each other via this bus. Figure 1.1 represents a simple system of a bus.

Figure 1.1: Simple system of a bus

The desirable direction of transmission for the transmitter and for the receiver need to be defined at all times by using additional output controls in order to achieve a faultless data communication on the bus. Several parties of the bus can receive data at the same time, but it needs to be ensured that at all times only one participant acts as a transmitter. A bus conflict emerges, if two or more parties send data on a bus. Because the outputs of parties with high impedance (for outputs with different logic level) a high current, which lows off through the outputs of the parties with low logical level.

The participants that are not supposed to send any data are therefore placed in a state of high-impedance. This means that the parties of a bus need to be able to realize the different logic states “high level = 1”, ”low level = 0” and “high impedance = Z” at their output.

If a member is in a high impedance state, it will not influence the bus in any way. The state of high-impedance represents a level in between high and low. This level can be reached at the outputs by taking suitable steps for the circuit design.



The output stage of the circuit can be realized as follows:

Figure 1.2: Tristate-output and open-collector

1. Tristate Outputs A tristate output enables the realization of the three states high, low and high impedance.

If the state “low” is at the output “OUT”, then the transistor T2 is connected through (i.e. collector-emitter-line is conductive) and T1 is barred (i.e. collector-emitter-line is non-conductive)

In the state “high” T2 is barred and T1 is connected through.

The high impedance state occurs when T1 and T2 are both barred.

Figure 1.3 demonstrates the symbolism of a tristate output.

Figure 1.3: Symbolism of a tristate output

2. Open Collector Outputs Open collector outputs without a “pullup-resistor” can only reach the levels “high impedance” and “low”, with a “pullup resistor” they can only reach the levels “high” and “low”. Their output stage solely has a npn-transistor, whose emitter is connected to ground. Such outputs can be parallel connected and have the same colletor-resistor (pullup resistor) as shown in figure 1.2. Open-Collector outputs can be inserted in a bus circuit, where it appoints the logic state of the signal line in one of several gates. This can be achieved by placing all outputs, except for one, in the state of high impedance.



1.2 Storing Data through a Bus

A tristate driver can be combined with a register in order to synchronize signals that are supposed to be transported through a bus. Such components can also be used as a 1-word storage.

The component 74LS374 is able to store data with 8 flip-flops and reading it out by using a control line (view appendix).

Q1: Draw the circuit for an output stage of the 74LS374 (from the data sheet)!

Now, only the two transistors on the right from the circuit in Q1 are supposed to be considered.

Q2: Which transistors are barred in the state “low” and which are connected through?

Q3: Which transistors are barred in the state ”high” and which are connected through?

Q4: Which transistors are barred in the “high impedance” state and which are connected through?



Following tasks can be answered by using the data sheet.

Q5: In which state of the output control is the output of the 74LS374 at a level of high impedance?

Q6: At which state of the output control and the clock does the D-flip-flop store data?

The below given circuit (figure 1.4) with the bus driver74LS374 represents a structure which can store an 8-bit word. The component 74LS374 disposes of a tristate output stage, so it is suitable for transferring data via a bus (view data sheet).

Figure 1.4: 8-bit bus driver with D-flip-flop

The simulation results given in figure 1.5 are supposed to clarify the functionality of the component.



Figure 1.5: Impulse diagram

D1, D2 are signals of the D[1:8] busses

Q1, Q2 are signals of the Q[1:8] busses

Explain the simulation steps by using the impulse diagram (Step size = 100ns) and the data sheet for the 74LS374.

Q7: In which time frame are the data stored in the component 74LS374?

Q8: In which time frame are the data read out of the component 74LS374?

Q9: Which input is responsible for the outputs Q[1:8] reaching the state of high impedance?

Q10: Why do the outputs Q[1:8] reach the state X in the frame of 121ns to 240ns?



1.3 Bi-directional Bus

A bi-directional bus is a bus where the flow of data can occur in both directions. This can be realized by e.g. placing the inputs and outputs of the component 74LS374 on a mutual bus (figure 1.6).

In this case, the data that is placed on the bus is supposed to be stored by the component and outputted in the next phase.

This can of course result in a bus conflict, e.g. when a data word is placed on the bus and simultaneously the bus is supposed to read out data which is stored in the component 74LS374. This would mean that two transmitters exist: the component 74LS374 on the one hand and the user of Workview who is trying to place data on the bus on the other hand.

In order to avoid a bus conflict, the bus needs to be placed into a state of high impedance by using the letter “Z” as an in put. Now, the data can be outputted from the component.

Figure 1.6: Bidirectional bus

The simulation results and the simulation steps for the circuit in figure 1.6 are presented in the figure 1.7 (Step size = 100ns).

The following input patterns were used for the simulation:

OC: 0s 1 400ns 0

G: 0s 0 100ns 1 200ns 0

D[1-8]: 0s 10101010 200ns zzzzzzzz 300ns 01010101 500ns zzzzzzzz



The following is the impulse diagram of the simulation:

Figure 1.7: Impulse Diagram

Explain the simulation steps by using the impulse diagram (Step size = 100ns) and the data sheet for the 74LS374.

Q11: In which time frame is the data placed on the bus?

Q12: In which time frame is the data stored in the component 74LS374?

Q13: In which time frame is the data read out of the component 74LS374?

Q14: In which time frame does the bus conflict take place? How could that have been avoided?



1.4 Storing Data via a bi-directional Bus

Now, a bi-directional bus, which is connected to components of the type 74LS374, is realized. The first driver is supposed to store the 8-bit word (10101010) (D1 D2 ... D7 D8), the second driver (10010010), the third driver (11100011) and the fourth driver (00100011) and afterwards it is supposed to be read out.

Figure 1.8: Data Transfer on a Bus

Q15: In which state of the output control can data be read out of the component?

Q16: Derive the required patterns for the inputs to solve the problem that was posed in the beginning of the chapter 1.4 and explain important simulation steps.

D[1..8] 0ns 10101010

C1 O1 C2 O2

C3 O3 C4 O4

(Noted: You are not allowed to do the lab without completed the table)



T1: Create a new project by navigating as follows: File New Project…

T2: Name the project as follows: Lab1(your group number)

T3: Make sure to select Analog or Mixed A/D to create the project to enable simulation.

T4: Used C:⁄OrCAD_DATA as the Location to store your project.

T5: Navigate from the schematic page editors’s Place menu to Part... OR press “P” to open the

place part window.

T6: Select Add Library and choose the required libraries, here: source.olb and 74sl.olb.

T7: The used sources can be found in the source.olb library and are called STIM(nr.) nr. Mewing

a number: 1, 4, 8, 16 for the amount of bits.

T8: Place all required parts and choose Place Wire OR press “W” to place a wire and choose

Place Bus OR press “B” to place a bus.

T9: Create the circuit in figure 1.8

T10: Enter the derived input patterns from question 16 in the respective input.

T11: Create a simulation profile by navigating as Follows: from the schematic page editor’s PSpice

menu choose New Simulation Profile.

T12: Enter the name of the new simulation as the name of your project and confirm by pressing

Create.

T13: The simulation Settings window pops up in which the duration of the simulation (Run to time)

can be adjusted.

T14: After editing confirm with ok and start the simulation by navigating to Pspice Run OR

pressing the “Play” button under the schematic page editor’s menu.

T15: Choose Pspice A/D as the suit and confirm with ok

T16: After Net-listing an empty Impulse diagram will appear if no errors were found.

T17: Return to the schematic page editor and place Voltage markers by navigating to Pspice

Markers Voltage Level. As you place the markers their data is displayed in the Impulse

diagram.



T18: Enter the simulation results in figure 1.9.

O[1:4]

C[1:4]

D[1:8]

Time

Figure 1.9: Impulse diagram



1.5 Storing Data in a RAM

For storing data a 4x4 bit register is used. The functionality and specification of the component can be found in the data sheets of the appendix. This 4x4 bit register is able to read and output words of 4-bit length at the same time. The component 74170 has an open-collector output!

The following circuit should be realized:

Figure 1.10: Storing data in a 4x4 bit register

Q17: Which pins are used for controlling the component?

Q18: What happens when a logical 1 is outputted? (Consider the behavior of open-collector-outputs with/without a pullup resistor!)



Q19: What are the inputs WA, WB, RA and RB for?

Q20: Can a data bus be used as bidirectional bus? Explain your answer.

Q21: Derive the input series, which stores the following 4-bit words in the register and outputs them afterwards. (Noted: You are not allowed to do lab without completed the following table)

D[1..4] GW WB WA RA RB GR Q[1..4] 1111 0000 1010 0011

D[1..4] 0ns 1111

GW WB WA RB RA GR

T19: Open a new Schematic named RAM(grnr1) page by right clicking on your project in the

project manager window and selecting New Page.

T20: Create the circuit according to figure 1.10. (The register can be found in the 74ls.olb library)

T21: Create a new simulation profile and simulate the circuit.



1.6 Data Transfer via a Bus

It is often necessary to transfer 8- or 16-bit words in 4-bit sections via the same conduction for processing and administering data in digital technique. This principle is e.g. used concerning input and output units for systems of processors.

The following circuit is supposed to be simulated. The components that are used are a RAM (74170, a 4x4 bit registers with open-collector) and two 4-bit D-type-registers with a tristate output 74LS173A.

Figure 1.11: Data transfer via a bus

Q22: Why are the pins 9, 10 (DE in the circuit) as well as 1, 2 (O1, O2 in the circuit) connected with each other? Which functions do the inputs have?

Q23: What is the task of pin 15 at the register?



The simulation should be performed as follows:

T22: An 8 bit word (10101010) (D1 D2 … D7 D8) is supposed to be placed at the bus IN[1..8].

T23: The data is supposed to be stored in the registers 1 and 2.

T24: The data from register 1 should be stored in the RAM.

T25: The data from register 2 should be stored in the RAM (under a different address).

T26: A second word (11110000) (D1 D2 … D7 D8) should be read out and stored in the RAM.

T27: The data is supposed to be read out in 4-bit words.

Q24: Which state should be at the output of the 4-bit register (register 1 or 2) to avoid that the 4x4 bit storage saves a wrong word? Which are the allocated inputs for this?

Q25: Which state does an output control need to have for storing data in register 1 and register 2?

Q26: Can O1 and O2 be simultaneously set to a logic1? Which inputs need to be set to a logic one for realizing part c)? In which state are D[1..4]?

Q27: Derive the input signals to accomplish the above given simulation. (Create the simulation table as in Q16 and Q21, Noted: You are not allowed to do the lab without answering this question)

T28: Create a new Schematic page named TRA(grnr1) and edit the circuit according to fig. 1.11.

T29: Enter the input signals from task 27 and simulate the circuit.

SN54173, SN54LS173A, SN74173, SN74LS173A4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTSSDLS067A – OCTOBER 1976 – REVISED JUNE 1999

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

� 3-State Outputs Interface Directly WithSystem Bus

� Gated Output-Control LInes for Enabling orDisabling the Outputs

� Fully Independent Clock VirtuallyEliminates Restrictions for Operating inOne of Two Modes:– Parallel Load– Do Nothing (Hold)

� For Application as Bus Buffer Registers� Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Flat(W) Packages, Ceramic Chip Carriers (FK),and Standard Plastic (N) and Ceramic (J)DIPs

TYPETYPICAL

PROPAGATIONDELAY TIME

MAXIMUMCLOCK

FREQUENCY’173 23 ns 35 MHz

’LS173A 18 ns 50 MHz

description

The ’173 and ’LS173A 4-bit registers includeD-type flip-flops featuring totem-pole 3-stateoutputs capable of driving highly capacitiveor relatively low-impedance loads. Thehigh-impedance third state and increasedhigh-logic-level drive provide these flip-flops withthe capability of being connected directly to anddriving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 ofthe SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs canbe connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load,respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logiclevels, the output control circuitry is designed so that the average output disable times are shorter than theaverage output enable times.

Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When bothdata-enable (G1, G2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the nextpositive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When bothare low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or buslines. The outputs are disabled independently from the level of the clock by a high logic level at eitheroutput-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailedoperation is given in the function table.

The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of–55°C to 125°C. The SN74173 and SN74LS173A are characterized for operation from 0°C to 70°C.

Copyright © 1999, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

12345678

161514131211109

MN

1Q2Q3Q4Q

CLKGND

VCCCLR1D2D3D4DG2G1

SN54173, SN54LS173A . . . J OR W PACKAGESN74173 . . . N PACKAGE

SN74LS173A . . . D or N PACKAGE(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

45678

1817161514

1D2DNC3D4D

1Q2QNC3Q4Q

SN54LS173A . . . FK PACKAGE(TOP VIEW)

N M NC

CLR

GN

DN

CC

CV

NC – No internal connection

G2

G1

CLK

On products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.

SN54173, SN54LS173A, SN74173, SN74LS173A4-BIT D-TYPE REGISTERSWITH 3-STATE OUTPUTSSDLS067A – OCTOBER 1976 – REVISED JUNE 1999

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLEINPUTS

OUTPUTCLR CLK

DATA ENABLE DATAOUTPUT

QCLR CLKG1 G2 D

Q

H X X X X L

L L X X X Q0L ↑ H X X Q0L ↑ X H X Q0

L ↑ L L L L

L ↑ L L H H

When either M or N (or both) is (are) high, the output isdisabled to the high-impedance state; however, sequentialoperation of the flip-flops is not affected.

logic symbol†

G2G1

G2G1

1Q3

R15

CLR

132D 2Q

4

123D 3Q

5

114D 4Q

6

1M

10

7CLK

&

† This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.Pin numbers shown are for D, J, N, and W packages.

&EN

C1

2N

9

1D14

1D 1Q3

R15

CLR

132D 2Q

4

123D 3Q

5

114D 4Q

6

1M

10

7CLK

&

&EN

C1

2N

9

1D14

1D

’173 ’LS173A




logic diagram (positive logic)

1D

C1

R

1D

C1

R

1D

C1

R

1D

C1

R

M

N

1D

CLR

CLK

2D

3D

4D

OutputControl

DataEnable

G1

G2

1

2

14

9

10

13

7

12

11

15

3

4

5

6

1Q

2Q

3Q

4Q

Pin numbers shown are for D, J, N, and W packages.



schematics of inputs and outputs

Equivalent of Each Input Equivalent of Each Input

Typical of All Outputs

VCC

Input

4 kΩ NOM

VCC

Input

20 kΩ NOM

VCC

Output

90 Ω NOM

VCC

Output

100 Ω NOM

’173 ’LS173A

Typical of All Outputs

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage, VCC (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage: ’173 –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

’LS173A –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-state output voltage –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect to network ground terminal.2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace

length of zero.




recommended operating conditions (see Note 3)SN54173 SN74173

UNITMIN NOM MAX MIN NOM MAX

UNIT

VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V

IOH High-level output current –2 –5.2 mA

IOL Low-level output current 16 16 mA

TA Operating free-air temperature –55 125 0 70 °C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)

PARAMETER TEST CONDITIONS†SN54173 SN74173

UNITPARAMETER TEST CONDITIONS†MIN TYP‡ MAX MIN TYP‡ MAX

UNIT

VIH High-level input voltage 2 2 V

VIL Low-level input voltage 0.8 0.8 V

VIK Input clamp voltage VCC = MIN, II = –12 mA –1.5 –1.5 V

VOH High-level output voltage VCC = MIN,VIL = 0.8 V,

VIH = 2 V,IOH = MAX 2.4 2.4 V

VOL Low-level output voltage VCC = MIN,VIL = 0.8 V,

VIH = 2 V,IOL = 16 mA 0.4 0.4 V

IO( ff)Off-state (high-impedance state) VCC = MAX, VO = 2.4 V 150 40

μAIO(off)( g )

output currentCC ,

VIH = 2 V VO = 0.4 V –150 –40μA

IIInput currentat maximum input voltage VCC = MAX, VI = 5.5 V 1 1 mA

IIH High-level input current VCC = MAX, VI = 2.4 V 40 40 μA

IIL Low-level input current VCC = MAX, VI = 0.4 V –1.6 –1.6 mA

IOS Short-circuit output current§ VCC = MAX –30 –70 –30 –70 mA

ICC Supply current VCC = MAX, See Note 4 50 72 50 72 mA† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values are at VCC = 5 V, TA = 25°C.§ Not more than one output should be shorted at a time.NOTE 4: ICC is measured with all outputs open; CLR grounded, following momentary connection to 4.5 V, N, G1, G2, and all data inputs grounded;

and CLK and M at 4.5 V.

timing requirements over recommended operating conditions (unless otherwise noted)SN54173 SN74173

UNITMIN MAX MIN MAX

UNIT

fclock Input clock frequency 25 25 MHz

tw Pulse duration CLK or CLR 20 20 ns

Data enable (G1, G2) 17 17

tsu Setup time Data 10 10 ns

CLR (inactive state) 10 10

th Hold timeData enable (G1, G2) 2 2

nsth Hold timeData 10 10

ns



switching characteristics, VCC = 5 V, TA = 25°C, RL = 400 Ω (see Figure 1)

PARAMETER TEST CONDITIONSSN54173 SN74173

UNITPARAMETER TEST CONDITIONSMIN TYP MAX MIN TYP MAX

UNIT

fmax Maximum clock frequency 25 35 25 35 MHz

tPHLPropagation delay time,high-to-low-level output from clear input 18 27 18 27 ns

tPLHPropagation delay time,low-to-high-level output from clock input CL = 50 pF

28 43 28 43ns

tPHLPropagation delay time,high-to-low-level output from clock input

L

19 31 19 31ns

tPZH Output enable time to high level 7 16 30 7 16 30ns

tPZL Output enable time to low level 7 21 30 7 21 30ns

tPHZ Output disable time from high levelCL = 5 pF

3 5 14 3 5 14ns

tPLZ Output disable time from low levelCL = 5 pF

3 11 20 3 11 20ns




recommended operating conditionsSN54LS173A SN74LS173A


UNIT






PARAMETER TEST CONDITIONS†SN54LS173A SN74LS173A UNIT

PARAMETER TEST CONDITIONS†MIN TYP‡ MAX MIN TYP‡ MAX UNIT




VOH High-level output voltage VCC = MIN,VIL = VILmax,

VIH = 2 V,IOH = MAX 2.4 3.4 2.4 3.1 V

VOL Low level output voltage VCC = MIN, IOL = 12 mA 0.25 0.4 0.25 0.4 VVOL Low-level output voltage CC ,

VIL = 0.8 V, IOL = 24 mA 0.35 0.5 V

IO( ff)Off-state (high-impedance state) VCC = MAX, VO = 2.7 V 20 20

VIO(off)( g )

output currentCC ,

VIH = 2 V VO = 0.4 V –20 –20V

IIInput currentat maximum input voltage VCC = MAX, VI = 7 V 0.1 0.1 mA

IIH High-level input current VCC = MAX, VI = 2.7 V 20 20 μA



ICC Supply current VCC = MAX, See Note 4 19 30 19 24 mA† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values are at VCC = 5 V, TA = 25°C.§ Not more than one output should be shorted at a time.NOTE 4: ICC is measured with all outputs open; CLR grounded, following momentary connection to 4.5 V, N, G1, G2, and all data inputs grounded;

and CLK and M at 4.5 V.

timing requirements over recommended operating conditions (unless otherwise noted)SN54LS173A SN74LS173A

UNITMIN MAX MIN MAX

UNIT

fclock Input clock frequency 30 25 MHz

tw Pulse duration CLK or CLR 25 25 ns

Data enable (G1, G2) 35 35

tsu Setup time Data 17 17 ns

CLR (inactive state) 10 10

th Hold timeData enable (G1, G2) 0 0

nsth Hold timeData 3 3

ns



switching characteristics, VCC = 5 V, TA = 25°C, RL = 667 Ω (see Figure 2)

PARAMETER TEST CONDITIONSSN54LS173A SN74LS173A

UNITPARAMETER TEST CONDITIONSMIN TYP MAX MIN TYP MAX

UNIT

fmax Maximum clock frequency 30 50 30 50 MHz

tPHLPropagation delay time,high-to-low-level output from clear input 26 35 26 35 ns

tPLHPropagation delay time,low-to-high-level output from clock input CL = 45 pF

17 25 17 25ns

tPHLPropagation delay time,high-to-low-level output from clock input

L

22 30 22 30ns

tPZH Output enable time to high level 15 23 15 23ns

tPZL Output enable time to low level 18 27 18 27ns

tPHZ Output disable time from high levelCL = 5 pF

11 20 11 20ns

tPLZ Output disable time from low levelCL = 5 pF

11 17 11 17ns




PARAMETER MEASUREMENT INFORMATIONSERIES 54/74 AND 54S/74S DEVICES

tPHL tPLH

tPLH tPHL

LOAD CIRCUITFOR 3-STATE OUTPUTS

High-LevelPulse

Low-LevelPulse

tw

VOLTAGE WAVEFORMSPULSE DURATIONS

Input

Out-of-PhaseOutput

(see Note D)

3 V

0 V

VOL

VOH

VOH

VOL

In-PhaseOutput

(see Note D)

VOLTAGE WAVEFORMSPROPAGATION DELAY TIMES

VCC

RL

Test Point

From OutputUnder Test

CL(see Note A)

LOAD CIRCUITFOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS

(see Note B)

VCC

RL


CL(see Note A)

TestPoint

(seeNote B)

VCC RL


CL(see Note A)

TestPoint

1 kΩ

NOTES: A. CL includes probe and jig capacitance.B. All diodes are 1N3064 or equivalent.C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr and tf ≤ 7 ns for Series

54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.F. The outputs are measured one at a time with one input transition per measurement.

S1

S2

tPHZ

tPLZtPZL

tPZH

3 V

3 V

0 V

0 V

thtsu

VOLTAGE WAVEFORMSSETUP AND HOLD TIMES

TimingInput

DataInput

3 V

0 V

OutputControl

(low-levelenabling)

Waveform 1(see Notes C

and D)


and D)≈1.5 V

VOH – 0.5 V

VOL + 0.5 V

≈1.5 V

VOLTAGE WAVEFORMSENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOL

VOH

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V

Figure 1. Load Circuits and Voltage Waveforms



PARAMETER MEASUREMENT INFORMATIONSERIES 54LS/74LS DEVICES

tPHL tPLH

tPLH tPHL


High-LevelPulse

Low-LevelPulse

tw


Input

Out-of-PhaseOutput

(see Note D)

3 V

0 V

VOL

VOH

VOH

VOL

In-PhaseOutput

(see Note D)


VCC

RL

Test Point


CL(see Note A)


LOAD CIRCUIT FOR2-STATE

TOTEM-POLE OUTPUTS

(see Note B)

VCC

RL


CL(see Note A)

TestPoint

(seeNote B)

VCC RL


CL(see Note A)

TestPoint

5 kΩ


Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 15 ns, tf ≤ 6 ns.G. The outputs are measured one at a time with one input transition per measurement.

S1

S2

tPHZ

tPLZtPZL

tPZH

3 V

3 V

0 V

0 V

thtsu


TimingInput

DataInput

3 V

0 V

OutputControl

(low-levelenabling)

Waveform 1S2 Open

(see Notes Cand D)

Waveform 2S2 Closed

(see Notes Cand D) ≈1.5 V

VOH – 0.3 V

VOL + 0.3 V

≈1.5 V


VOL

VOH

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V

1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V 1.3 V


PACKAGING INFORMATION

Orderable Device Status (1) PackageType

PackageDrawing

Pins PackageQty

Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

JM38510/36101B2A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NCJM38510/36101BEA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NCJM38510/36101BFA ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NCJM38510/36101SEA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NCJM38510/36101SFA ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC

SN54173J ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NCSN54LS173AJ ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC

SN74173N OBSOLETE PDIP N 16 TBD Call TI Call TISN74LS173AD ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM

SN74LS173ADE4 ACTIVE SOIC D 16 40 Green (RoHS &no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LS173ADR ACTIVE SOIC D 16 2500 Green (RoHS &no Sb/Br)


SN74LS173ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS &no Sb/Br)


SN74LS173AN ACTIVE PDIP N 16 25 Pb-Free(RoHS)

CU NIPDAU Level-NC-NC-NC

SN74LS173ANE4 ACTIVE PDIP N 16 25 Pb-Free(RoHS)


SN74LS173ANSR ACTIVE SO NS 16 2000 Green (RoHS &no Sb/Br)


SN74LS173ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS &no Sb/Br)


SNJ54173J ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NCSNJ54173W OBSOLETE CFP W 16 TBD Call TI Call TI

SNJ54LS173AFK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NCSNJ54LS173AJ ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NCSNJ54LS173AW ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please checkhttp://www.ti.com/productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flameretardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak soldertemperature.

PACKAGE OPTION ADDENDUM

www.ti.com 26-Sep-2005

Addendum-Page 1

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limitedinformation may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TIto Customer on an annual basis.



Addendum-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

4040140/D 10/96

28 TERMINAL SHOWN

B

0.358(9,09)

MAX

(11,63)

0.560(14,22)

0.560

0.458

0.858(21,8)

1.063(27,0)

(14,22)

ANO. OF

MINMAX

0.358

0.660

0.761

0.458

0.342(8,69)

MIN

(11,23)

(16,26)0.640

0.739

0.442

(9,09)

(11,63)

(16,76)

0.962

1.165

(23,83)0.938

(28,99)1.141

(24,43)

(29,59)

(19,32)(18,78)

**

20

28

52

44

68

84

0.020 (0,51)

TERMINALS

0.080 (2,03)0.064 (1,63)

(7,80)0.307

(10,31)0.406

(12,58)0.495

(12,58)0.495

(21,6)0.850

(26,6)1.047

0.045 (1,14)

0.045 (1,14)0.035 (0,89)

0.035 (0,89)

0.010 (0,25)

121314151618 17

11

10

8

9

7

5

432

0.020 (0,51)0.010 (0,25)

6

12826 27

19

21B SQ

A SQ22

23

24

25

20

0.055 (1,40)0.045 (1,14)

0.028 (0,71)0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. This package can be hermetically sealed with a metal lid.D. The terminals are gold plated.E. Falls within JEDEC MS-004

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI’s termsand conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. To minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third-party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual propertyof the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is withoutalteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproductionof this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable forsuch altered documentation.

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Mailing Address: Texas InstrumentsPost Office Box 655303 Dallas, Texas 75265

Copyright © 2005, Texas Instruments Incorporated

SN54LS373, SN54LS374, SN54S373, SN54S374,SN74LS373, SN74LS374, SN74S373, SN74S374

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002


� Choice of Eight Latches or Eight D-TypeFlip-Flops in a Single Package

� 3-State Bus-Driving Outputs� Full Parallel Access for Loading� Buffered Control Inputs� Clock-Enable Input Has Hysteresis to

Improve Noise Rejection (’S373 and ’S374)� P-N-P Inputs Reduce DC Loading on Data

Lines (’S373 and ’S374)

description

These 8-bit registers feature 3-state outputsdesigned specifically for driving highly capacitiveor relatively low-impedance loads. Thehigh-impedance 3-state and increasedhigh-logic-level drive provide these registers withthe capability of being connected directly to anddriving the bus lines in a bus-organized systemwithout need for interface or pullup components.These devices are particularly attractive forimplementing buffer registers, I/O ports,bidirectional bus drivers, and working registers.

The eight latches of the ’LS373 and ’S373 aretransparent D-type latches, meaning that whilethe enable (C or CLK) input is high, the Q outputsfollow the data (D) inputs. When C or CLK is takenlow, the output is latched at the level of the datathat was set up.

The eight flip-flops of the ’LS374 and ’S374 areedge-triggered D-type flip-flops. On the positivetransition of the clock, the Q outputs are set to thelogic states that were set up at the D inputs.

Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system designas ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A bufferedoutput-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logiclevels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus linessignificantly.

OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or newdata can be entered, even while the outputs are off.


Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54LS373, SN54LS374, SN54S373,SN54S374 . . . J OR W PACKAGE

SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGESN74LS374 . . . DB, DW, N, OR NS PACKAGE

SN74S373 . . . DW OR N PACKAGE(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

45678

1817161514

8D7D7Q6Q6D

2D2Q3Q3D4D

SN54LS373, SN54LS374, SN54S373,SN54S374 . . . FK PACKAGE

(TOP VIEW)

1D 1Q OC

5Q 5D8Q

4QG

ND C

V CC

12345678910

20191817161514131211

OC1Q1D2D2Q3Q3D4D4Q

GND

VCC8Q8D7D7Q6Q6D5D5QC†

† C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.

† C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.

†

PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

On products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.

SN54LS373, SN54LS374, SN54S373, SN54S374,SN74LS373, SN74LS374, SN74S373, SN74S374OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS



ORDERING INFORMATION

TA PACKAGE† ORDERABLEPART NUMBER

TOP-SIDEMARKING

Tube SN74LS373N SN74LS373N

PDIP NTube SN74LS374N SN74LS374N

PDIP – NTube SN74S373N SN74S373N

Tube SN74S374N SN74S374N

Tube SN74LS373DWLS373

Tape and reel SN74LS373DWRLS373

Tube SN74LS374DWLS374

0°C to 70°C SOIC DWTape and reel SN74LS374DWR

LS374

0°C to 70°C SOIC – DWTube SN74S373DW

S373Tape and reel SN74S373DWR

S373

Tube SN74S374DWS374

Tape and reel SN74S374DWRS374

Tape and reel SN74LS373NSR 74LS373

SOP – NS Tape and reel SN74LS374NSR 74LS374

Tape and reel SN74S374NSR 74S374

SSOP – DB Tape and reel SN74LS374DBR LS374A

Tube SN54LS373J SN54LS373J

Tube SNJ54LS373J SNJ54LS373J

Tube SN54LS374J SN54LS374J

CDIP JTube SNJ54LS374J SNJ54LS374J

CDIP – JTube SN54S373J SN54S373J

Tube SNJ54S373J SNJ54S373J

Tube SN54S374J SN54S374J

–55°C to 125°C Tube SNJ54S374J SNJ54S374J

Tube SNJ54LS373W SNJ54LS373W

CFP – W Tube SNJ54LS374W SNJ54LS374W

Tube SNJ54S374W SNJ54S374W

Tube SNJ54LS373FK SNJ54LS373FK

LCCC FKTube SNJ54LS374FK SNJ54LS374FK

LCCC – FKTube SNJ54S373FK SNJ54S373FK

Tube SNJ54S374FK SNJ54S374FK† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.





Function Tables

’LS373, ’S373(each latch)

INPUTS OUTPUTOC C D Q

L H H H

L H L L

L L X Q0H X X Z

’LS374, ’S374(each latch)

INPUTS OUTPUTOC CLK D Q

L ↑ H H

L ↑ L L

L L X Q0H X X Z




logic diagrams (positive logic)

OC

for ’S373 Only

1

11

32

C

1D

C1

1D1Q

45

2D

C1

1D2Q

76

3D

C1

1D3Q

89

4D

C1

1D4Q

1312

5D

C1

1D5Q

1415

6D

C1

1D6Q

1716

7D

C1

1D7Q

1819

8D

C1

1D8Q

Pin numbers shown are for DB, DW, J, N, NS, and W packages.

OC

for ’S374 Only

1

11

32

CLK

1D

C1

1D1Q

45

2D 1D2Q

76

3D 1D3Q

89

4D 1D4Q

1312

5D 1D5Q

1415

6D 1D6Q

1716

7D 1D7Q

1819

8D 1D8Q

’LS373, ’S373Transparent Latches

’LS374, ’S374Positive-Edge-Triggered Flip-Flops

C1

C1

C1

C1

C1

C1

C1





schematic of inputs and outputs

Output

TYPICAL OF ALL OUTPUTS

VCC

100 Ω NOM

VCC

Req = 20 kΩ NOM

Input

Input

VCC

17 kΩ NOM

’LS373

EQUIVALENT OF DATA INPUTS EQUIVALENT OF ENABLE- ANDOUTPUT-CONTROL INPUTS

EQUIVALENT OF CLOCK- ANDOUTPUT-CONTROL INPUTS

’LS374

EQUIVALENT OF DATA INPUTS

30 kΩ NOM

Input

VCC

17 kΩ NOM

VCC

Input

Output


VCC

100 Ω NOM




absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†(’LS devices)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-state output voltage 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect to network ground terminal.2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditionsSN54LS’ SN74LS’


UNIT

VCC Supply voltage 4.5 5 5 4.75 5 5.25 V

VOH High-level output voltage 5.5 5.5 V



t Pulse durationCLK high 15 15

nstw Pulse durationCLK low 15 15

ns

t Data setup time’LS373 5↓ 5↓

nstsu Data setup time’LS374 20↑ 20↑

ns

th Data hold time’LS373 20↓ 20↓

nsth Data hold time’LS374‡ 5↑ 0↑

ns

TA Operating free-air temperature –55 125 0 70 °C‡ The th specification applies only for data frequency below 10 MHz. Designs above 10 MHz should use a minimum of 5 ns (commercial only).






PARAMETER TEST CONDITIONS†SN54LS’ SN74LS’

UNITPARAMETER TEST CONDITIONS†MIN TYP‡ MAX MIN TYP‡ MAX

UNIT




VOH High level output voltage VCC = MIN, VIH = 2 V, 2 4 3 4 2 4 3 1 VVOH High-level output voltage CC ,VIL = VIL max,

IH ,IOH = MAX 2.4 3.4 2.4 3.1 V

VOL Low level output voltage VCC = MIN, VIH = 2 V, IOL = 12 mA 0.25 0.4 0.25 0.4VVOL Low-level output voltage CC ,

VIL = VIL maxIH ,

IOL = 24 mA 0.35 0.5V

IOZHOff-state output current, VCC = MAX, VIH = 2 V, 20 20 �AIOZH

,high-level voltage applied

CC ,VO = 2.7 V

IH , 20 20 �A

IOZLOff-state output current, VCC = MAX, VIH = 2 V, 20 20 �AIOZL

,low-level voltage applied

CC ,VO = 0.4 V

IH , –20 –20 �A

IIInput current at maximum VCC = MAX VI = 7 V 0 1 0 1 mAII input voltage VCC = MAX, VI = 7 V 0.1 0.1 mA

IIH High-level input current VCC = MAX, VI = 2.7 V 20 20 �A



ICC Supply current VCC = MAX, ’LS373 24 40 24 40mAICC Supply current CC ,

Output control at 4.5 V ’LS374 27 40 27 40mA

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values are at VCC = 5 V, TA = 25°C.§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)

PARAMETER FROM TO TEST CONDITIONS’LS373 ’LS374

UNITPARAMETER (INPUT) (OUTPUT) TEST CONDITIONSMIN TYP MAX MIN TYP MAX

UNIT

fmaxRL = 667 Ω� CL = 45 pF,

See Note 3 35 50 MHz

tPLH Data Any Q RL = 667 Ω� CL = 45 pF, 12 18ns

tPHLData Any Q L � L ,

See Note 3 12 18ns

tPLH C or CLK Any Q RL = 667 Ω� CL = 45 pF, 20 30 15 28ns

tPHLC or CLK Any Q L � L ,

See Note 3 18 30 19 28ns

tPZHOC Any Q RL = 667 Ω� CL = 45 pF, 15 28 20 26

nstPZL

OC Any Q L � L ,See Note 3 25 36 21 28

ns

tPHZ 15 25 15 28tPHZOC Any Q RL 667 Ω CL 5 pF

15 25 15 28ns

tPLZOC Any Q RL = 667 Ω� CL = 5 pF

12 20 12 20ns

tPLZ 12 20 12 20

NOTE 3: Maximum clock frequency is tested with all outputs loaded.fmax = maximum clock frequencytPLH = propagation delay time, low-to-high-level outputtPHL = propagation delay time, high-to-low-level outputtPZH = output enable time to high leveltPZL = output enable time to low leveltPHZ = output disable time from high leveltPLZ = output disable time from low level




schematic of inputs and outputs

EQUIVALENT OF EACH INPUT

VCC

Input

2.8 kΩ NOM

Output


VCC

50 Ω NOM

’S373 and ’S374 ’S373 and ’S374





absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†(’S devices)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage, VI 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-state output voltage 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 2): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect to network ground terminal.2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditionsSN54S’ SN74S’


UNIT


VOH High-level output voltage 5.5 5.5 V


t Pulse duration clock/enableHigh 6 6

nstw Pulse duration, clock/enableLow 7.3 7.3

ns

t Data setup time’S373 0↓ 0↓

nstsu Data setup time’S374 5↑ 5↑

ns

th Data hold time’S373 10↓ 10↓

nsth Data hold time’S374 2↑ 2↑

ns





electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted) (SN54S373, SN54S374, SN74S373, SN74S374)

PARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT

VIH 2 V

VIL 0.8 V

VIK VCC = MIN, II = –18 mA –1.2 V

VOHSN54S’

VCC = MIN VIH = 2 V VIL = 0 8 V IOH = MAX2.4 3.4

VVOH SN74S’VCC = MIN, VIH = 2 V, VIL = 0.8 V, IOH = MAX

2.4 3.1V

VOL VCC = MIN, VIH = 2 V, VIL = 0.8 V, IOL = 20 mA 0.5 V

IOZH VCC = MAX, VIH = 2 V, VO = 2.4 V 50 �A

IOZL VCC = MAX, VIH = 2 V, VO = 0.5 V –50 �A

II VCC = MAX, VI = 5.5 V 1 mA

IIH VCC = MAX, VI = 2.7 V 50 �A

IIL VCC = MAX, VI = 0.5 V –250 �A

IOS§ VCC = MAX –40 –100 mA

Outputs high 160

’S373 Outputs low 160

Outputs disabled 190

ICC VCC = MAX Outputs high 110 mA

’S374Outputs low 140

’S374Outputs disabled 160

CLK and OC at 4 V, D inputs at 0 V 180† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values are at VCC= 5 V, TA = 25°C.§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2)

PARAMETER FROM TO TEST CONDITIONS’S373 ’S374

UNITPARAMETER (INPUT) (OUTPUT) TEST CONDITIONSMIN TYP MAX MIN TYP MAX

UNIT

fmaxRL = 280 Ω� CL = 15 pF,

See Note 3 75 100 MHz

tPLH Data Any Q RL = 280 Ω� CL = 15 pF, 7 12ns

tPHLData Any Q L � L ,

See Note 3 7 12ns

tPLH C or CLK Any Q RL = 280 Ω� CL = 15 pF, 7 14 8 15ns

tPHLC or CLK Any Q L � L ,

See Note 3 12 18 11 17ns

tPZHOC Any Q RL = 280 Ω� CL = 15 pF, 8 15 8 15

nstPZL

OC Any Q L � L ,See Note 3 11 18 11 18

ns

tPHZOC Any Q RL = 280 Ω CL = 5 pF

6 9 5 9ns

tPLZOC Any Q RL = 280 Ω� CL = 5 pF

8 12 7 12ns

NOTE 3. Maximum clock frequency is tested with all outputs loaded.fmax = maximum clock frequencytPLH = propagation delay time, low-to-high-level outputtPHL = propagation delay time, high-to-low-level outputtPZH = output enable time to high leveltPZL = output enable time to low leveltPHZ = output disable time from high leveltPLZ = output disable time from low level





PARAMETER MEASUREMENT INFORMATIONSERIES 54LS/74LS DEVICES

tPHL tPLH

tPLH tPHL


High-LevelPulse

Low-LevelPulse


Input

Out-of-PhaseOutput

(see Note D)

3 V

0 V

VOL

VOH

VOH

VOL

In-PhaseOutput

(see Note D)


VCC

RLTest Point


CL(see Note A)


LOAD CIRCUITFOR 2-STATE TOTEM-POLE OUTPUTS

(see Note B)

VCC

RLFrom Output

Under Test

CL(see Note A)

TestPoint

(see Note B)

VCCRL


CL(see Note A)

TestPoint

5 kΩ


Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.G. The outputs are measured one at a time with one input transition per measurement.H. All parameters and waveforms are not applicable to all devices .

S1

S2

tPHZ

tPLZtPZL

tPZH

3 V

3 V

0 V

0 V

thtsu


TimingInput

DataInput

3 V

0 V

OutputControl

(low-levelenabling)


and D)


and D) ≈1.5 V

VOH – 0.5 V

VOL + 0.5 V

≈1.5 V


1.3 V 1.3 V

1.3 V 1.3 V

1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V

1.3 V

tw

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

VOL

VOH





PARAMETER MEASUREMENT INFORMATIONSERIES 54S/74S DEVICES

tPHL tPLH

tPLH tPHL


High-LevelPulse

Low-LevelPulse


Input

Out-of-PhaseOutput

(see Note D)

3 V

0 V

VOL

VOH

VOH

VOL

In-PhaseOutput

(see Note D)


VCC

RLTest Point


CL(see Note A)


LOAD CIRCUITFOR 2-STATE TOTEM-POLE OUTPUTS

(see Note B)

VCC

RLFrom Output

Under Test

CL(see Note A)

TestPoint

(see Note B)

VCCRL


CL(see Note A)

TestPoint

1 kΩ


Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series

54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.F. The outputs are measured one at a time with one input transition per measurement.G. All parameters and waveforms are not applicable to all devices .

S1

S2

tPHZ

tPLZtPZL

tPZH

3 V

3 V

0 V

0 V

thtsu


TimingInput

DataInput

3 V

0 V

OutputControl

(low-levelenabling)


and D)


and D)≈1.5 VVOH – 0.5 V

VOL + 0.5 V

≈1.5 V


1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V

tw

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

VOH

VOL






TYPICAL APPLICATION DATA

BidirectionalData Bus 2

OutputControl 2

Clock 2Clock 1

BidirectionalData Bus 1

OutputControl 1

Clock 1

Clock 2

HBus

ExchangeClock

H

Clock Circuit for Bus Exchange

AB

Expandable 4-Word by 8-Bit General Register File

Enable Select

1/2 SN74LS139or SN74S139

’LS374 or ’S374

’LS374 or ’S374

’LS374 or ’S374

’LS374 or ’S374

1/2 SN74LS139or SN74S139

Y0Y1Y2Y3

Y0 Y1 Y2 Y3A B G

ClockSelect Clock

’LS374or

’S374

’LS374or

’S374

G

1D2D3D4D5D6D7D8D

1Q2Q3Q4Q5Q6Q7Q8Q

1D2D3D4D5D6D7D8D

1Q2Q3Q4Q5Q6Q7Q8Q

C

C

Bidirectional Bus Driver

PACKAGING INFORMATION


PackageDrawing

Pins PackageQty


5962-7801102VRA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC5962-7801102VSA ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NC

78011022A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC7801102RA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC7801102SA ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NC

JM38510/32502B2A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NCJM38510/32502BRA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NCJM38510/32502BSA ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NCJM38510/32502SRA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NCJM38510/32502SSA ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NCJM38510/32503B2A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NCJM38510/32503BRA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NCJM38510/32503BSA ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NC

SN54LS373J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NCSN54LS374J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NCSN54S373J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NCSN54S374J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC

SN74LS373DW ACTIVE SOIC DW 20 25 Green (RoHS &no Sb/Br)


SN74LS373DWE4 ACTIVE SOIC DW 20 25 Green (RoHS &no Sb/Br)


SN74LS373DWR ACTIVE SOIC DW 20 2000 Green (RoHS &no Sb/Br)


SN74LS373DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS &no Sb/Br)


SN74LS373N ACTIVE PDIP N 20 20 Pb-Free(RoHS)


SN74LS373N3 OBSOLETE PDIP N 20 TBD Call TI Call TISN74LS373NSR ACTIVE SO NS 20 2000 Green (RoHS &


SN74LS373NSRE4 ACTIVE SO NS 20 2000 Green (RoHS &no Sb/Br)


SN74LS374DBR ACTIVE SSOP DB 20 2000 Green (RoHS &no Sb/Br)


SN74LS374DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS &no Sb/Br)


SN74LS374DW ACTIVE SOIC DW 20 25 Green (RoHS &no Sb/Br)


SN74LS374DWG4 ACTIVE SOIC DW 20 25 Green (RoHS &no Sb/Br)


SN74LS374DWR ACTIVE SOIC DW 20 2000 Green (RoHS &no Sb/Br)


SN74LS374DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &no Sb/Br)


SN74LS374J OBSOLETE CDIP J 20 TBD Call TI Call TISN74LS374N ACTIVE PDIP N 20 20 Pb-Free CU NIPDAU Level-NC-NC-NC



Addendum-Page 1


PackageDrawing

Pins PackageQty


(RoHS)SN74LS374N3 OBSOLETE PDIP N 20 TBD Call TI Call TI

SN74LS374NE4 ACTIVE PDIP N 20 20 Pb-Free(RoHS)


SN74LS374NSR ACTIVE SO NS 20 2000 Green (RoHS &no Sb/Br)


SN74LS374NSRE4 ACTIVE SO NS 20 2000 Green (RoHS &no Sb/Br)


SN74S373DW ACTIVE SOIC DW 20 25 Green (RoHS &no Sb/Br)


SN74S373DWE4 ACTIVE SOIC DW 20 25 Green (RoHS &no Sb/Br)


SN74S373DWR ACTIVE SOIC DW 20 2000 Green (RoHS &no Sb/Br)


SN74S373DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS &no Sb/Br)


SN74S373J OBSOLETE CDIP J 20 TBD Call TI Call TISN74S373N ACTIVE PDIP N 20 20 Pb-Free

(RoHS)CU NIPDAU Level-NC-NC-NC

SN74S373N3 OBSOLETE PDIP N 20 TBD Call TI Call TISN74S374DW ACTIVE SOIC DW 20 25 Green (RoHS &


SN74S374DWE4 ACTIVE SOIC DW 20 25 Green (RoHS &no Sb/Br)


SN74S374DWR ACTIVE SOIC DW 20 2000 Green (RoHS &no Sb/Br)


SN74S374DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS &no Sb/Br)


SN74S374J OBSOLETE CDIP J 20 TBD Call TI Call TISN74S374N ACTIVE PDIP N 20 20 Pb-Free


SN74S374N3 OBSOLETE PDIP N 20 TBD Call TI Call TISN74S374NE4 ACTIVE PDIP N 20 20 Pb-Free


SN74S374NSR ACTIVE SO NS 20 2000 Green (RoHS &no Sb/Br)


SN74S374NSRE4 ACTIVE SO NS 20 2000 Green (RoHS &no Sb/Br)


SNJ54LS373FK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NCSNJ54LS373J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NCSNJ54LS373W ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NCSNJ54LS374FK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NCSNJ54LS374J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NCSNJ54LS374W ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NCSNJ54S373FK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NCSNJ54S373J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC

SNJ54S374FK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NCSNJ54S374J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC



Addendum-Page 2


PackageDrawing

Pins PackageQty


SNJ54S374W ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NC

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please checkhttp://www.ti.com/productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flameretardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak soldertemperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limitedinformation may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TIto Customer on an annual basis.



Addendum-Page 3

MECHANICAL DATA

MLCC006B – OCTOBER 1996


FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

4040140/D 10/96

28 TERMINAL SHOWN

B

0.358(9,09)

MAX

(11,63)

0.560(14,22)

0.560

0.458

0.858(21,8)

1.063(27,0)

(14,22)

ANO. OF

MINMAX

0.358

0.660

0.761

0.458

0.342(8,69)

MIN

(11,23)

(16,26)0.640

0.739

0.442

(9,09)

(11,63)

(16,76)

0.962

1.165

(23,83)0.938

(28,99)1.141

(24,43)

(29,59)

(19,32)(18,78)

**

20

28

52

44

68

84

0.020 (0,51)

TERMINALS

0.080 (2,03)0.064 (1,63)

(7,80)0.307

(10,31)0.406

(12,58)0.495

(12,58)0.495

(21,6)0.850

(26,6)1.047

0.045 (1,14)

0.045 (1,14)0.035 (0,89)

0.035 (0,89)

0.010 (0,25)

121314151618 17

11

10

8

9

7

5

432

0.020 (0,51)0.010 (0,25)

6

12826 27

19

21B SQ

A SQ22

23

24

25

20

0.055 (1,40)0.045 (1,14)

0.028 (0,71)0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. This package can be hermetically sealed with a metal lid.D. The terminals are gold plated.E. Falls within JEDEC MS-004

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001


DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,207,40

0,550,95

0,25

38

12,90

12,30

28

10,50

24

8,50

Seating Plane

9,907,90

30

10,50

9,90

0,38

5,605,00

15

0,22

14

A

28

1

2016

6,506,50

14

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M0,15

0°–�8°

0,10

0,090,25

NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.D. Falls within JEDEC MO-150

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