logic gates ghader kurdi adapted from the slides prepared by department of preparatory year
DESCRIPTION
Design of Logic Gates The basic logic gates are: AND OR NAND NOR XOR XNOR Inverter (NOT) BufferTRANSCRIPT
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Logic Gates
Ghader Kurdi
Adapted from the slides prepared by DEPARTMENT OF PREPARATORY YEAR.
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Introduction to Digital Logic Basics
Hardware consists of a few simple building blocks These are called logic gates
AND, OR, NOT, … NAND, NOR, XOR, …
Both the inputs and output to/from logic gates are expressed in terms of 1s and 0s
Logic gatePerforms logical
operationoutputInput/s
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Design of Logic Gates The basic logic gates are:
AND OR NAND NOR XOR XNOR Inverter (NOT) Buffer
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Design of Logic Gates Logic gates are built using transistors
NOT gate can be implemented by a single transistor AND requires 3 transistors
Transistors are the fundamental devices that any electronic system consists of
Pentium consists of 3 million transistors Compaq Alpha consists of 9 million transistors Now we can build chips with more than 100 million
transistors
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AND gate
A B F0 0 00 1 01 0 01 1 1
AND function finds the minimum between two binary digits
AND gate outputs a 1 only if all the inputs are 1.
Truth table
Graphical representation
F = A . B or F = AB
Logical representation
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OR gate
A B F0 0 00 1 11 0 11 1 1
Truth table
F = A + B
Logical representation
OR finds the maximum between two binary digits
OR gate outputs a 1 if any one of the inputs is1.
Graphical representation
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NAND gate
A B F0 0 10 1 11 0 11 1 0
NAND = AND + NOT The output is "false" if both inputs are "true."
Otherwise, the output is "true."
Truth table
Graphical representation
F = A . B
Logical representation
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NOR gate
A B F0 0 10 1 01 0 01 1 0
NOR = OR + NOT The output is "true" if both inputs are "false."
Otherwise, the output is "false."
Truth table
Graphical representation
F = A + B
Logical representation
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XOR gate
A B F0 0 00 1 11 0 11 1 0
XOR implements exclusive-OR function The output is "true" if either, but not both, of the
inputs are "true." The output is "false" if both inputs are "false" or if both inputs are "true."
Truth table
Graphical representation
A + B = A · B + A · B
Logical representation
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XNOR gate The output is true when both inputs A and B are
true and when neither A nor B is true.
A B F0 0 10 1 01 0 01 1 1
Truth table
Graphical representation
A + BLogical representation
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NOT (Inventer) gate
A F0 11 0
Has only one input Outputs the inverse of the value inputted
Truth table
Graphical representation
F = A or A’
Logical representation
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Buffer
A Y0 01 1
Has only one input Outputs the same value inputted
Truth table
Graphical representation
Y = ALogical representation
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Integration levels
SSI (small scale integration) Introduced in late 1960s 1-10 gates (previous examples)
MSI (medium scale integration) Introduced in late 1960s 10-100 gates
LSI (large scale integration) Introduced in early 1970s 100-10,000 gates
VLSI (very large scale integration) Introduced in late 1970s More than 10,000 gates
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Logic Functions Logical functions can be expressed in several
ways: Truth table Logical expressions Graphical form
Example: Majority function
Output is 1 whenever majority of inputs is 1 We use 3-input majority function
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Truth Table
A B C …. F0 0 0 ….0 0 1 ….0 1 0 ….0 1 1 ….1 0 0 ….1 0 1 ….1 1 0 ….1 1 1 ….
…. …. …. …. ….
In a truth table, the number of rows = (number of inputs)2
The truth table has a column foe each input on the left hand side
The outputs are listed in columns on the right hand side
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Logic Functions (cont.)3-input majority function
A B C F
0 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1
Logical expression formF = A B + B C + A C
0 0 00
0
00
0
0
0
0
0
0
0 0 0 0
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Logic Functions (cont.) Logical expression: Q= A’B + AB’A B A’ B’ A’B AB’ Q
0
0
1
1
0
1
0
1
1
1
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
1
1
0
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Logic Circuit Design Process A simple logic design process involves
Problem specification Truth table derivation Derivation of logical expression Simplification of logical expression Implementation
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Logical Equivalence All three circuits implement F = A B function
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Logical Equivalence (cont.) Proving logical equivalence of two circuits
1. Derive the logical expression for the output of each circuit
2. Show that these two expressions are equivalent Two ways:
You can use the truth table method For every combination of inputs, if both expressions
yield the same output, they are equivalent Good for logical expressions with small number of
variables You can also use algebraic manipulation
Need Boolean identities
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Logical Equivalence (cont.)
A
B
A+B
Derivation of logical expression from a circuit Trace from the input to output Write down intermediate logical expressions along the path
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Logical Equivalence (cont.) Proving logical equivalence: Truth table method
A B A B (A + B) F2 = (A + B)0011
0101
1100
1010
1110
0001
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Logical Equivalence (cont.) Derivation of logical expression from a circuit
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Logical Equivalence (cont.) Proving logical equivalence: Truth table method
A B F1 = A B F3 = (A + B) (A + B) (A + B)
0 0 0 00 1 0 01 0 0 01 1 1 1
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The Universal NAND Gate NAND gate is the main fundamental universal gate
for being easier in manufacturing process.
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The Universal NAND Gate (cont.)
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The Universal NAND Gate (cont.)
A B F0 00 11 01 1
A B F0 0 10 1 11 0 11 1 0
0
01
1
10
0
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The Universal NAND Gate (cont.)
A B F0 0 00 11 01 1
A B F0 0 10 1 11 0 11 1 0
0
11
1
10
0
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The Universal NAND Gate (cont.)
A B F0 0 00 1 01 01 1
A B F0 0 10 1 11 0 11 1 0
1
01
1
10
0
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The Universal NAND Gate (cont.)
A B F0 0 00 1 01 0 01 1
A B F0 0 10 1 11 0 11 1 0
1
10
0
01
1
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The Universal NAND Gate (cont.)
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The Universal NAND Gate (cont.)
A F01
A B F0 0 10 1 11 0 11 1 0
0
01
1
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The Universal NAND Gate (cont.)
A F0 11
A B F0 0 10 1 11 0 11 1 0
1
10
0
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The Universal NOR Gate NOR gate is also another main fundamental
universal gate
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Deriving Logical Expressions Derivation of logical expressions from truth tables
sum-of-products (SOP) form product-of-sums (POS) form
SOP form Write an AND term for each input combination that
produces a 1 output Write the variable if its value is 1; complement
otherwise OR the AND terms to get the final expression
POS form Dual of the SOP form
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Deriving Logical Expressions (cont.)
3-input majority function
A B C F0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1
SOP logical expression Four product terms
Because there are 4 rows with a 1 output
F = A B C + A B C + A B C + A B C
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Deriving Logical Expressions (cont.)
3-input majority function
A B C F0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1
POS logical expression Four sum terms
Because there are 4 rows with a 0 output
F = (A + B + C) (A + B + C) (A + B + C) (A + B + C)
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Boolean Algebra Boolean algebra can be used to formalize
the combinations of binary logic states. In these relations A and B are binary
quantities, they can be either logical true (T or 1) or
logical false (F or 0).
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Boolean Algebra
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Boolean Algebra (cont.)
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Logical Expression SimplificationProve that: A B = (A + B) (A + B) (A + B)
Used rules
(A + B) (A + B) (A + B) Distribution
(A + BB) (A + B) Complement
(A + 0) (A + B) Identity
A (A + B) Distribution
AA + AB Complement
0 + AB Identity
AB
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Logical Expression SimplificationProve that: A B = (A + B) (A + B) (A + B)
Used
rules
(A + B) (A + B) (A + B)
Idempotent
(A + B) (A + B) (A + B) (A + B)
((A + B) (A + B)) ((A + B) (A + B)) Distribution
(A + BB) (B + AA) Complement
(A + 0) (B + 0) Identity
(A)(B)
AB
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Logical Expression Simplification (cont.)
Prove that: X+XY = XUsed rules
X+XY X(1+Y) NullX(1) IdentityX
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Logical Expression Simplification (cont.)
Prove that: X(X+Y) = XUsed rules
X(X+Y) Distribution
XX+XY Idempotent
X+XY
X(1+Y) Null
X(1) Identity
X
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Logical Expression Simplification (cont.)
Prove that: X.(Y+Z) = X.Y + X.ZUsed rules
X.Y + X.Z Distribution
(X.Y + X) (X.Y + Z) Absorption
X . (X.Y + Z) Distribution
X . (Z+X . Z+Y) Associative
(X . X+Z) . (Y+Z) Absorption
X . (Y+Z)
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Logical Expression Simplification (cont.)
Prove that: X(X+X') = XUsed rules
X(X+X') Distribution XX + XX’ IdempotentX + XX’ ComplementX + 0 Identity X
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Logical Expression Simplification (cont.)
Majority function exampleA B C + A B C + A B C + A B C =
A B C + A B C + A B C + A B C + A B C + A B C
We can now simplify this expression as
B C + A C + A B
A difficult method to use for complex expressions
Added extra
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Logical Expression Simplification (cont.)
Simplify the next:WY + XY + WZ + XZ = (W + X) (Y + Z)
Used rules
WY + XY + WZ + XZ Distribution
Y(W + X) + Z(W + X)
(W + X) (Y + Z)
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Logical Expression Simplification (cont.)
Simplify the next: (X + Y) + (X + Y) = 0Used Rules
(X + Y) + (X + Y) Associative
(X + X) + ( Y + Y) Complement,
Idempotent
1 + Y Null10
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Logical Expression Simplification (cont.)
Simplify the next: (X + Y) + (X + Y) = 0Used Rules
(X + Y) . (X + Y) De Morgan(X . Y) . ( X . Y) De Morgan (X . Y) . ( X . Y) Associative
(X . X) . (Y . Y) Idempotent
(X . X) . (Y) Complement
0 . Y Null0
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Simplification Using Boolean Algebra
AB+A(B+C)+B(B+C) (distributive law)
AB+AB+AC+BB+BC (Idempotent; BB=B)
AB+AB+AC+B+BC (Idempotent; AB+AB=AB)
AB+AC+B+BC (Absorption; B+BC=B)
AB+AC+B (Absorption; AB+B=B)
B+AC
A
B
C
B+AC
A
BC AB+A(B+C)+B(B+C)
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Logical Expression Simplification (cont.)
Two basic methods Algebraic manipulation
Use Boolean laws to simplify the expression Difficult to use Don’t know if you have the simplified form
Karnaugh map (K-map) method Graphical method Easy to use
limited to problems with up to 4 binary inputs. Let's start with a simple example
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Karnaugh Map Method
Karnaugh Map Of Two Variables
A = 0B = 0
A = 0B = 1
A = 1B = 0
A = 1B = 1
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Karnaugh Map Method (cont.)
Step 1: Find a truth table Step 2: Draw a K-map
A B A’
B’ A’B’
A’B
F
0 0 1 1 1 0 10 1 1 0 0 1 11 0 0 1 0 0 01 1 0 0 0 0 0
1 0 1 0
0 10 1
AB
F = A’B’ + A’B
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Karnaugh Map Method (cont.)
Step 3: Group adjacent 1’sStep 4: Read off a reduced expression
1 0 1 0
0 1
0 1
AB
1 0 1 0
0 10 1
AB
A’B’
A’B
A’B’ + A’B = A’
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Karnaugh Map Method (cont.)
1 0 1 0
0 1
0 1
AB
0 1 0 1
0 1
0 1
AB
1 1 0 0
0 10 1
AB
0 0 1 1
0 1
0 1
AB
1 1 1 0
0 1
0 1
AB
1 1 1 1
0 10 1
AB
How to group adjacent 1’s ?