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Fundamentals of Digital

Engineering:

Digital Logic

A Micro-Course

R. Katz

Grunt Engineer

Design Engineer (retired)

May 21, 2001



AbstractThe basics of Boolean algebra will be introduced, starting from

simple combinational logic functions and basic sequential logic

circuits such as latches and flip-flops. Based on these

fundamentals, more complex logic structures such as decoders,

adders, registers, and memories will constructed and their

performance analyzed. FET Transistor basics will be reviewedand circuits introduced that demonstrate implementations of the

basic logic elements in CMOS technology. The logic functions

used as the architectural basis for programmable devices used in

spaceborne electronics will be examined and analyzed.

Some common design problems found in flight circuits will be

introduced.



Micro-Course Outline

• Introduction

• Basic Logic

• Hardware

• Combinational Logic

• Sequential Logic• Module Design in Programmable Devices



Basic Digital Logic



Logic Values

• For binary hardware

– Either a „1‟ or a „0‟

– “Most of the time”

• Other types of hardware can be have more

than two values

• Simulation can use a multi-value logic

system

– VHDL Std_Logic uses a nine-valued logic



Binary Hardware Logic Values

• Logic „1‟

• Logic „0‟

• Undefined value



TTL Logic Levels

• Logic „1‟ threshold - VIH

2.0 V

• Logic „0‟ threshold - VIL

0.8 V

• Undefined

0.8 V < v < 2.0 V



TTL Logic Levels

Examples of Undefined Values• Floating signals may take on illegal values

• What happens during a signal transition?

0.8V

2.0V

Logic „0‟

Undefined

Logic „1‟



MIL-STD-1553

• Three physical values> +VTH

< - VTH -VTH < v < +VTH

• All values have meaning in MIL-STD-1553



1http://www.intel.com/design/flcomp/prodbref/298044.htm

Intel Flash Memory

• Intel® StrataFlash™ memory components

store two bits per cell for high density and

low cost.1

• Smaller margins for radiation.



Physical Logic Values

• Magnetic field (core memory, plated wire)

• Voltage (static CMOS logic)

• Charge (DRAM)• Position (contacts open/closed)

• Frequency of Sound (tones for a modem)

• Light (fiber optics - MIL-STD-1773)

• Etc.



Logic Values and Basic

Functions



Logic Values

• Levels

– '0' or '1'

• Pulses – Presence or absence of pulses

– Pulse widths

– Number of pulses

• Zero crossings



Switching Algebra

• Two-valued variable from {0,1}

• Two binary operations

– AND ( • )

– OR ( + )

• One unary operation

– NOT ( )



A Multi-valued Logic SystemUsed In VHDL Simulation

TYPE std_ulogic IS (

‘U’, -- Uninitialized

‘X’, -- Forcing Unknown

‘0’,-- Forcing 0

‘1’, -- Forcing 1

‘Z’, -- High Impedance

‘W’, -- Weak Unknown

‘L’, -- Weak ‘0’ ‘H’, -- Weak ‘1’

‘-’ -- Don’t Care

);



Unary Operation - NOT

A Y

0 1

1 0



Binary Operation - AND

A B Y

0 0 0

0 1 0

1 0 0

1 1 1



Binary Operation - [Inclusive] OR

A B Y

0 0 0

0 1 1

1 0 1

1 1 1



Binary Functions

• How many functions are there of two binary

variables?

– Basic combinatorics

– 4 positions or rows: 00, 01, 10, 11

– For each position you can select one of two

values {0, 1}

– Order counts since it is a function

– Number of functions = 2 x 2 x 2 x 2 = 24 = 16



Binary Functions - cont‟d • How many functions are there of n binary

variables? – 2n positions or rows

• for n = 2: 00, 01, 10, 11

• for n = 3: 000, 001, 010, 011, 100, 101, 110, 111 – For each position or row you can select one of two

values {0, 1}

– Number of functions = 2^2n

• for n = 2: 22 = 4; 2 x 2 x 2 x 2 = 24 = 16

• for n = 3: 23 = 8; 2 x 2 x 2 x 2 x 2 x 2 x 2 x 2 = 28 = 64

• for n = 4: 24 = 16; 216 = 65536



Fan-In

• Number of inputs to a logic gate

• Examples for AND function

• n = 2: Y = A • B

• n = 3: Y = A • B • C

• n = 4: Y = A • B • C • D



Logic Functions

• Any logic function can be implementedwith AND, OR, and NOT.

• One standard form is the sum of products

• Example: Y = (A • B + C • D)

Inputs AND gates OR gates Inverters Outputs



Universal Logic Element



Universal Logic Gate

Introduction

• Some other logic functions

– NOR ::= Negative OR

Y = ( A + B )´

– NAND ::= Negative AND

Y = ( A • B )´

– Multiplexor

Y = A • S + B • S´

– Look up table (LUT)

Small memory




NOR Function

• NOR ::= Negative ORY = ( A + B )´

NOT

OR

AND




NAND Function• NAND ::= Negative AND

Y = ( A • B )´

NOT

OR

AND




Multiplexor Function

• MultiplexorY = A • S + B • S´

NOT OR AND




Look up table (LUT)

• Look up table (LUT)Small memory

NOT OR AND

A X Y A B Y A B Y

0 0 1 0 0 0 0 0 0

0 1 1 0 1 1 0 1 0

1 0 0 1 0 1 1 0 0

1 1 0 1 1 1 1 1 1



Logic Assignments and DualityLogic Gate and Voltage

A B Y

0V 0V 0V

0V 5V 0V

5V 0V 0V

5V 5V 5V

Logic Gate - Positive Logic

A B Y 0 0 0

0 1 0

1 0 0

1 1 1

0 = 0V1 = 5V

Logic Gate - Negative Logic

A B Y

1 1 11 0 1

0 1 1

0 0 0

1 = 0V

0 = 5V

Logic Gate - Negative Logic

A B Y

0 0 00 1 1

1 0 1

1 1 1

1 = 0V

0 = 5V

Reorder Rows



Adders



Half-Adder

Logic Equations

C = x • y

S = x y

Truth Table

x y C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

Schematic



Full-Adder

Logic Equations

C = x’yz + xy’z + xyz’ + xyz

= z • (x’y+xy’) + xy • (z+z’)

= z • (x y) + x • y= MAJ (x,y,z)

S = x’y’z + x’yz’ + xy’z’ + xyz

= x’yz’ + xy’z’ + x’y’z + xyz = z’(x’y + xy’) + z(x’y’ + xy)

= z’(x y) + z(x y)’

= (x y) z

= x y z

Truth Table

x y z C S

0 0 0 0 0

0 0 1 0 10 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 01 1 0 1 0

1 1 1 1 1



Full Adder Schematic



Adding Two Numbers

• Many Types of Adders: Some examples:

• Bit Serial Adder

– Add time = n x f

• Cascade Stages – Ripple carry adder

– Add time = n x tPD

• Carry Look Ahead Adder – Generate carries in parallel

– e.g., 4- bit AM2902. Can have “look ahead” of

the “look ahead” units.



4-bit Ripple Carry Adder



Carry Lookahead Adder (CLA)



Sample CLA Timing Analysis

• Generate g and p: 1 gate delay

• Generate C: 2 gate delays

• Generate sum: 3 gate delays

• Total: 6 gate delays

Total is independent of word length



Transistors



Transistor Definitions

• MOS - Metal Oxide Semiconductor

• FET - Field Effect Transistor

• BJT - Bipolar Junction Transistor



MOSFET and BJT

n-channel MOSFET npn bipolar transistor

gate

source

body

drain collector

base

emitter



Basic MOSFET Construction



collector

base

emitter

BJT Symbols

collector

base

emitter

npn bipolar transistor pnp bipolar transistor



MOSFET Symbols

A circle is sometimes

used on the gate terminal

to show active low input



Basic MOSFET



Show how MOSFET can be used

as a switch



Basic CMOS Logic Technology

• Based on the fundamental inverter circuit

• Transistors (two) are enhancement-mode

MOSFETs

– N-channel with its source grounded

– P-channel with its source connected to +V

• Input: gates connected together

• Output: drains connected



CMOS Inverter

p

n

GND

VDD

A Y = A'



Since the gate is essentially an open circuit it draws no current, and theoutput voltage will be equal to either ground or to the power supply

voltage, depending on which transistor is conducting.

When input A is grounded (logic 0), the N-channel MOSFET is

unbiased, and therefore has no channel enhanced within itself. It is an

open circuit, and therefore leaves the output line disconnected from

ground. At the same time, the P-channel MOSFET is forward biased,

so it has a channel enhanced within itself, connecting the output line to

the +Vsupply. This pulls the output up to +V (logic 1).

When input A is at +V (logic 1), the P-channel MOSFET is off and theN-channel MOSFET is on, thus pulling the output down to ground

(logic 0). Thus, this circuit correctly performs logic inversion, and at

the same time provides active pull-up and pull-down, according to the

output state.

CMOS Inverter - Operation

CMOS 2 I NOR



CMOS 2-Input NOR



This basic CMOS inverter can be expanded into NOR andNAND structures by combining inverters in a partially series,

partially parallel structure. A practical example of a CMOS 2-

input NOR gate is shown in the figure.

In this circuit, if both inputs are low, both P-channel MOSFETs

will be turned on, thus providing a connection to +V. Both N-

channel MOSFETs will be off, so there will be no ground

connection. However, if either input goes high, that P-channel

MOSFET will turn off and disconnect the output from +V, while

that N-channel MOSFET will turn on, thus grounding the output.

Note the two p-channel FETs in series.

CMOS 2-Input NOR - Operation



CMOS 2-Input NAND



A two-input NAND gate: a logic 0 at either input will force the output tologic 1; both inputs at logic 1 will force the output to go to logic 0.

Note the two n-channel FETs in series and the two p-channel FETs in

parallel.

The pull-up and pull-down resistances at the output are never the same,

and can change significantly as the inputs change state, even if the output

does not change logic states. The result is uneven and unpredictable rise

and fall times for the output signal. This problem was addressed, and was

solved with the buffered, or B-series CMOS gates.

CMOS 2-Input NAND - Operation



CMOS 2-Input NAND: Buffered



The technique here is to follow the actual NAND gate with a pair of inverters. Thus,the output will always be driven by a single transistor, either P-channel or N-channel.

Since they are as closely matched as possible, the output resistance of the gate will

always be the same, and signal behavior is therefore more predictable. Typically, the p-

channel transistor is approximately twice as wide as the n-channel transistor, because of

the difference in conductivity between electronics and holes.

Note that we have not gone into all of the details of CMOS gate construction here. For

example, to avoid damage caused by static electricity, different manufacturers

developed a number of input protection circuits, to prevent input voltages from

becoming too high. However, these protection circuits do not affect the logical behavior

of the gates, so we will not go into the details here. This is not strictly true for most

CMOS devices for applications that are power-switched; special inputs are required for

power-off isolation between circuits.

CMOS 2-Input NAND: Buffered



Decoders



Encoding

Binary

Decimal Unencoded Encoded

0 0001 00

1 0010 012 0100 10

3 1000 11

Note: Finite state machines may be unencoded ("one-hot")

or binary encoded. If the all 0's state is used, then

one less bit is needed and it is called modified

one-hot coding.

Wh Encode?



Why Encode?

A Logarithmic Relationship

N

0 25 50 75 100 125 150

Log2(N)

0

1

2

3

4

5

6

7

8

2 4 D d



2:4 Decoder

1 1

1 0

0 1

00

What happens when the inputs goes from 01 to 10?

2 4 D d i h E bl



2:4 Decoder with Enable

1 1

1 0

0 1

00



Static Hazards

Static Hazard



Static Hazard

2:1 Mux implemented by

minimized Sum-of-Products

Idealized matched delays

Static Hazard



Static HazardIn real circuits, delays don't

exactly match; Added delayfor illustration

Static Hazard



Static Hazard

We now have a "glitch."

Same waveform, zoomed in.

Static Hazard



Static Hazard

S=0

S=1

0 0 0 1 1 1 1 0

A B

0 0 1 1

0 1 1 0

Illustrating the minimized function on a Karnaugh map.

Only two 2-input AND gates are needed for the product terms

Static Hazard



Static Hazard

0 0 0 1 1 1 1 0

A B

0 0 1 1

0 1 1 0

The blue oval shows the redundant term used to cover the

transition between product terms.

S=0

S=1

Static Hazard



Static Hazard

How can we verify the

presence and operationof the „redundant‟ gate?

Static Hazard0000 0



Static Hazard 0001 1

0010 2

0011 3

0100 4

0101 5

0110 6

0111 7

1000 81001 9

1010 10

1011 11

1100 121101 13

1110 14

1111 15

0000 16

Terminal count of

a 4-bit synchronous

counter.

Static Hazard



Static HazardFlight Design Example

TMR Triplet Majority Voter

High-skew buffer

Static Hazard



Static HazardFlight Design Example

Care is needed when using TMR circuits. First,the output of the voter may be susceptible to a

logic hazard “glitch.” This is not a problem if the

TMR is feeding the input of another synchronous

input. However, the TMR output should never

feed asynchronous inputs such as flip-flop

clocks, clears, sets, read/write inputs, etc.

“Design Techniques for Radiation-Hardened FPGAs”

Actel Corporation, September 1997

-- based on “SEU Hardening of Field Programmable Gate Arrays (FPGAs) for Space

Applications and Device Characterization,” R. Katz, R. Barto, et. al., IEEE Transactions

on Nuclear Science, Dec. 1994.

Static Hazard



Static Hazard

We have covered static hazards. There are alsodynamic hazards. An example of a dynamic

hazard would be when a circuit is supposed to

switch as follows:

0 1

But instead switches:

0 1 0 1

Any circuit that is static hazard free is also

dynamic hazard free.

Common Output Stage



Common Output Stage

Definitions

• VOH - Output voltage when driving high

• VOL - Output voltage when driving low

• IOH - Output current when driving high

• IOL - Output current when driving low

• tT - Transition time, usually measuredbetween 10% and 90% of the waveform

(2.2)

V Test Configuration



VOH Test Configuration

VCC

i

+

-

Output Stage

Programmable

Load

V Test Configuration



VOL Test Configuration

VCC

i

+

-

Output Stage

ProgrammableLoad

VCC

A1460A TID (VOH) Test



VOUT

0 1 2 3 4 5

I OUT(A)

0.000

0.010

0.020

0.030

0.040

0.050

S/N LAN3501S/N LAN3502

S/N LAN3503

S/N LAN3504

A1460A TID (VOH) TestPost-Irradiation

A1460A TID (VOL) Test



Vcc-VOUT

0 1 2 3 4 5

I OUT(A)

0.000

0.020

0.040

0.060

0.080

0.100

S/N LAN3501

S/N LAN3502


A1460A TID (VOL) TestPost-Irradiation

RT54SX32 TID (VOH) Test



VOUT

0 1 2 3

I OUT(A)

0.000

0.010

0.020

0.030

0.040

0.050

0.060

0.070

0.080

S/N LAN4403

S/N LAN4404

S/N LAN4405

S/N LAN4406

RT54SX32 TID (VOH) TestPost-Irradiation

RT54SX32 TID (VOL) Test



Vcc-VOUT

0 1 2 3

I OUT(A)

0.000

0.020

0.040

0.060

0.080



RT54SX32 TID (VOL) TestPost-Irradiation

Sample RT54SX16 Rise Time



Sample RT54SX16 Rise Time

Sample RT54SX16 Fall Time



Sample RT54SX16 Fall Time

C I f L l



Common Interface Levels

• TTL

• 5V CMOS

• 5V PCI

• 3.3V PCI

• LVDS

• LVTTL

TTL Voltage Specification



TTL Voltage Specification

• VOH - 2.4 V

• VOL - 0.5 V

• VIH - 2.0 V

• VIL - 0.8 V

• '1' Noise margin = 400 mV

• '0' Noise margin = 300 mV

5V CMOS Voltages



5V CMOS Voltages

• VOH - ~VDD (no DC load)

• VOL - ~GND (No DC load)

• VIH - 70% VDD

• VIL - 30% VDD

Very high noise margin.



Flip-Flops

Basic RS Flip Flop (NAND)



Basic RS Flip-Flop (NAND)

A flip-flop holds 1 "bit".

"Bit" ::= "binary digit."

Clocked D Flip-Flop



Clocked D Flip Flop

The present state is held when CP is low.

Clock Pulse Definition



Clock Pulse Definition

Edges can also be referred to as leading and trailing.

Positive Pulse

Positive

Edge

Negative

Edge

Negative Pulse

Positive

Edge

Negative

Edge

Master-Slave Flip-Flop



Master Slave Flip Flop

Flip-Flop on RT54SX-A



p p

(Not hardened)

Master Slave

RT54SX-A SEU Performance



RT54SX A SEU Performance,

LET (MeV-cm2/mg)

0 10 20 30 40 50 6

C

ross-section(cm

2/flip-flop)

10-9

10-8

10-7

10-6

Flip-Flop StringFlip-Flop String w/ Buffers

Notes:

1. S/N LAN40012. Ions = 210 MeV Cl-35, 284 MeV Br-81, 345 MeV I-127

3. Fluence ~ 107

ions/cm2

4. Bias = 4.5, 2.25 VDC5. Checkerboard pattern

6. Frequency = 1 MHz7. 200 flip-flops / string8. Regular CLK Buffer

RT54SX-S Latch



(SEU Hardened)

Flip-Flop Timing: RT54SX-S



p p g

Worst-case Military Conditions, V CCA =2.3, V CCI=3.0V, TJ =125C-1 Speed Grade

Min Max Units

tRCO Sequential Clock-to-Q 1.0 ns

tCLR Asynchronous Clear-to-Q 0.9 ns

tPRESET Asynchronous Preset-to-Q 1.0 ns

tSUD Flip-Flop Data Input Set-Up 0.6 ns

tHD Flip-Flop Data Input Hold 0.0 ns

tWASYN Asynchronous Pulse Width 1.8 ns

Metastability Introduction



Metastability - Introduction

• Can occur if the setup, hold time, or clock pulse width of a

flip-flop is not met.

• A problem for asynchronous systems or events.

• Can be a problem in synchronous systems.

• Three possible symptoms: – Increased CLK -> Q delay.

– Output a non-logic level

– Output switching and then returning to its original state.

• Theoretically, the amount of time a device stays in themetastable state may be infinite.

• Many designers are not aware of metastability.

Metastability



Metastability

• In practical circuits, there is sufficient noise to move thedevice output of the metastable state and into one of the

two legal ones. This time can not be bound. It is

statistical.

• Factors that affect a flip-flop's metastable "performance"

include the circuit design and the process the device is

fabricated on.

• The resolution time is not linear with increased circuit time

and the MTBF is an exponential function of the available

slack time.

Metastability - Calculation



Metastability - Calculation

• MTBF = eK2*t / ( K1 x FCLK x FDATA)

t is the slack time available for settling

K1 and K2 are constants that are characteristic of the flip-flop

Fclock and Fdata are the frequency of the synchronizing clock and

asynchronous data.

• Software is available to automate the calculations with

built-in tables of parameters.

• Not all manufacturers provide data.

Metastability - Sample Data



Metastability - Sample DataSample Metastable Time Data

CX2001 Technology50 MHz clock, 10 MHz data rate

Slack Time (ns)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

log10(MTBF(years))

-15

-10

-5

0

5

10

15

20

25

Note: Each flip-flop has its own K1, K2 parameters.

Synchronizer (Bad Circuit)



Synchronizer (Bad Circuit)

Metastable State:



Possible Output from a Flip-flop

Metastable State:



Possible Outputs from a Flip-flop

Correct Output



Parallel Registers

4-Bit Parallel Register



4-Bit Parallel Register

4-Bit Register With Enable



4-Bit Register With Enable

Register Files (Simplified)



Register Files (Simplified)

D and Q are both sets of lines, with the number of lines

equal to the width of each register. There are often multiple

address ports, as well as additional data ports.

D

CLK

Q

Address - log2(num registers)

Register 1

Register 2



Memory Devices

Magnetic



Register

Core

Memory

Decoder(AND plane)

Sense wires serve as OR plane.

Semiconductor



Semiconductor

Memory

Decoder

(AND plane)

OR plane

Rad-Hard PROM Architecture



No latches in this architecture

W28C64 EEPROM



Simplified Block Diagram

Row

Address

Latches

Column

Address

Latches

A6-12

A0-5

Row

Address

Decoder

Column

Address

Decoder

Edge

Detect &

Latches

Control

Latch

Control

Logic

CE*

WE*

OE*

64 Byte

Page

Buffer

Timer

CLK

E2 Memory

Array

I/O Buffer/ Data Polling

I/O0-7

Latch Enable

PE RSTB VW



Module Design of

PALs and FPGAs

Programmable Logic

C t



Components

ANDPlane ORPlane

I n p u t s + B u f f e r s / I n v e r t e r s

I n v e r t e r s +

O u t p u t s

F l i p - F l o p s ( o p t i o n a l )

PROMs, PALs, and PLAs all have a similar architecture

PAL Architecture



Programmable

AND plane andfixed OR plane.

PALs have a built-in

POR circuit to

initialize all registers

to zero.

FPGA Logic Modules



• Actel (Act 1,2,3, SX) – Basics

– Flip-flop Construction

• UTMC/Quicklogic (i.e., UT4090)

– RAM blocks

• Xilinx (i.e., CQR40xxXL, Virtex)

– LUTs/RAM

– Carry Logic/Chain• Mission Research Corp. (MRC) - Orion

• Atmel - AT6010

Act 2 Logic Module: C-Mod



Act 2 Logic Module: C Mod

8-Input Combinational function

766 possible combinational

macros1

1”Antifuse Field Programmable Gate Arrays,” J. Greene, E. Hamdy, and S. Beal,

Proceedings of the IEEE, Vol. 91, No. 7, July 1993, pp. 1042-1056

Act 2 Flip-flop Implementation



p p p

Hard-wired Flip-flop

Feedback goes through

antifuses (R) and routing

segments (C)

Routed or “C-C Flip-flop”

SX R Cell Implementation



SX R-Cell Implementation

SX S R Cell Implementation



SX-S R-Cell Implementation

UT4090 Logic Module



• Antifuse Configuration

Memory

• Mux-based• Multiple Outputs

• Wide logic functions

UT4090 RAM Module



• Dual-port

• 1152 bits per cell

• Four configurations

– 64 X 18

– 128 X 9

– 256 X 4

– 512 X 2

WA(8:0)

WD(17:0)

WE

WCLK

MODE(1:0)

RE

RCLK

RA(8:0)

RD(17:0)

ASYNCRD

XC4000 Series CLBSi lifi d CLB C L i N t Sh



Simplified CLB - Carry Logic Not Shown

RAM LUTs

for Logic or

small SRAMTwo Flip-flops

XQR4000XL Carry Path



General interconnect

Placement is

important forperformance.

Carry Logic Operation



Effective Carry Logic for a Typical Addition - XQR4000XL

MRC Orion Logic Module



AT60xx Logic Module



28 unique functions

AT60xx Logic Module



A Closer Look

logic course

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