lm 2-1 number system rev2!2!11 14

NSF TUES-Type 2 Project, “Dissemination of Microprocessor Courses through Classroom and Interactive Cyber-Enabled Technologies” 2/11/2014 LEARNING MODULE 2-1- P A G E | 1

This materials are based on work supported by the National Science Foundation under grant number: DUE 1120000

Learning Module #2-1: Number Systems and Gates

Table of Contents Goals .......................................................................................................................................................................................... 3 Objectives ................................................................................................................................................................................ 3 Introduction ...................................................................................................................... Error! Bookmark not defined.

1. Why Study Number Systems? .................................................................................................................................. 3

2. Different Number Systems ..................................................................................................................................... 4 3. Number System Conversion ....................................................................................................................................... 4

(1) Decimal to Binary ................................................................................................................................................... 4 (2) Decimal to Octal Conversion ............................................................................................................................... 5 (3) Decimal to Hexadecimal ....................................................................................................................................... 5 (4) Binary to Octal....................................................................................................................................................... 6

(5) Binary to Hex ........................................................................................................................................................ 6 (6) Octal to Hex ........................................................................................................................................................... 6

4. Basic Logic Gates and Functions ............................................................................................................................... 7 (1) AND Gate ................................................................................................................................................................ 8 (2) OR Gate ................................................................................................................................................................... 8 (3) NOT/Inverter Gate.............................................................................................................................................. 9 (4) NAND Gate ............................................................................................................................................................. 9 (5) NOR Gate ................................................................................................................................................................ 9 (6) XOR Gate ............................................................................................................................................................... 10 (7) XNOR Gate ............................................................................................................................................................ 10 (8) Buffer ..................................................................................................................................................................... 11

5. Design Considerations ................................................................................................................................................ 12 (1) TTL Fan-out ........................................................................................................................................................... 12 (2) CMOS Fan-out ....................................................................................................................................................... 13 (3) Tri-state Devices ................................................................................................................................................. 14 (4) Open-Collector Outputs...................................................................................................................................... 14

6. Logic Arithmetic (Add & Subtract) ........................................................................................................................ 15 (1) The 1’s Complement .............................................................................................................................................. 15 (2) The 2’s Complement ............................................................................................................................................. 15

7. A Simple One-bit ADDER circuit ............................................................................................................................ 17

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8. The Environment and Software Operations ........................................................................................................ 22 (1) MPLAB IDE Operation ........................................................................................................................................ 22

9. Header File and Source Codes ................................................................................................................................ 25 Student Assessment ............................................................................................................................................................ 26 Practice Test Questions ..................................................................................................................................................... 27 Homework ............................................................................................................................................................................... 28

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Goals • Transfer data using different number systems. • Explain basic gate operations. • Use a PIC microcontroller in various number systems’ mathematics and logic operations.

Objectives 1. Manipulate different number systems under Decimal, Binary, Octal, and Hexadecimal bases. 2. Describe basic logic gate operation and uses. 3. Use and convert the 1’s and 2’s complements for Binary numbers. 4. Construct basic add and subtract Binary circuits. 6. Conduct addition and subtraction in Binary and Hex number systems. 7. Use basic logic operations in Binary, Octal, and Hex number systems. 8. Interpret PIC STATUS flag bits after mathematical and logic operations. 9. Describe PIC decisions/judgments based on STATUS flag bits.

Content

1. Why Study Number Systems?

The modern world of digital electronics is that of something being ON (Logic State 1) or something being OFF (Logic State 0). When these 0’s and 1’s are used to make up numbers (as in the decimal number system), they can be used to represent many different things like IP’s, entry codes, instructions for a microprocessor or microcontroller, etc. Since there are only two digits, 0 and 1, the base 2 or binary number system is used. In fact the term “Bit” comes from Binary digIT. The digital revolution has also coined the terms ‘nibble’ which is 4-Bits, ‘byte’ which is 8-Bits, and ‘word’ which is 16-Bits. The following are the standard names for groups of binary digits:

1 4 2 8 2 4 16

2 8 4 32 4 16 8 64

Bit Binary digitNibble BitsByte Nibbles BitsWord Bytes Nibbles BitsDouble Word Words Nibbles Bytes BitsLong Word Words Nibbles Bytes Bits

=== == = == = = == = = =

The problem is that humans have a difficult time interpreting binary numbers directly and the translation from binary to our normal decimal number system is a bit tedious. The most efficient number system for humans to use in interpreting binary numbers is the hexadecimal

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(base 16) number system. However, some systems use Octal instead. Therefore, we must examine the number systems that we will use in this coursework.

2. Different Number Systems 10 2 8 16Decimal/Base Binary/Base Octal/Base Hexidecimal/Base

0 0 0 01 1 1 12 10 2 23 11 3 34 100 4 45 101 5 56 110 6 67 111 7 78 1000 10 89 1001 11 910 1010 1211 1011 1312 1100 1413 1101 1514 1110 1615 1111 1716 10000 20 1017 10001 21 11

ABCDEF

3. Number System Conversion The following are some examples demonstrating how numbers can be changed between different number systems. We will use a short-hand method known as the ‘Sum-of-Weights’ method.

(1) Decimal to Binary In order to begin the ‘Sum-of-Weights’ method for conversion from Decimal to Binary, you start at the binary point (decimal pt) and start writing the powers of two (i.e., 20) to the left until the next power of two would be greater than the number to be converted. For this example we will convert 43110 to Binary:

431256 128 64 32 16 8 4 2 1

Once you have completed the method setup, start on the far left and start dividing. In this example, 256 goes into 431 one (1) time with 175 remainder.

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431 175256 128 64 32 16 8 4 2 11

Continuing with the example, 128 goes into 175 one (1) time with 47 remainder.

431 175 47256 128 64 32 16 8 4 2 11 1

Next, note that 64 doesn’t go into 47, so the remainder of 47 moves to the right and a (0) is recorded as the binary bit.

431 175 47 47256 128 64 32 16 8 4 2 11 1 0

The example continues until all columns have been completed:

2

431 175 47 47 15 15 7 3 1256 128 64 32 16 8 4 2 1 110101111 1 0 1 0 1 1 1 1

⇒

(2) Decimal to Octal Conversion

Example: 103.8210 to Octal: The conversion method for Decimal to Octal is the same method as before but this time with powers of 8. Note that this example has a fraction.

103 .8264 8 1 . .125 15.63 1.953 244.11 .

m m u

Finishing the ‘Sum of Weights’ method we get:

8

103 39 7 .82 70 7.48 1.6264 8 1 . .125 15.63 1.953 244.1 147.64361 4 7 . 6 4 3 6

m m mm m u ⇒

(3) Decimal to Hexadecimal

Example: 3654.01210 to Hex:

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Again, the only change in the method is that this time we use powers of 16.

3654 .012256 16 1 . 62.5 3.906 244.1m m u

Carrying the example to the end, we get:

16

3654 70 6 .012 .012 282256 16 1 . 62.5 3.906 244.1 46.031

4 6 . 0 3 1

um m u E

E⇒

(4) Binary to Octal Example: 10111.11012 to Octal This conversion process uses the fact that the largest digit in Octal is a 7 and it takes three bits to represent a 7 in Binary. So, you take the Binary number, start at the binary point and group the bits in each direction into groups of three. You are required to pad the right side with zeros to complete a group of three.

2 872 6

4

10111.1101 00 27.64padded

⇒

(5) Binary to Hex

Example: 111101.011012 to Hex This time the process uses the fact that the largest digit in Hex is an ‘F (15)’ and it takes four bits to represent a 15 in Binary. So, you take the binary number, start at the binary point and group the bits in each direction into groups of four. You are required to pad the right side with zeros to complete a group of four.

2 163 6

8

111101.01101000 3 68PaddedD

D⇔

(6) Octal to Hex

Example: 357148 to Hex In order to complete this process, you must first convert the octal number to Binary and then convert the Binary number to Hex. It is not possible to go directly to Hex from Octal.

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Convert the base 8 number to Binary. Note that we represent each octal number as 3 binary bits. Then, group the binary into groups of 4 and convert to HEX.

8 2 2 16001111011 101 100 3

3 5 7 1 4 11101111001100 11101111001100 3⇒ ⇒ ⇒CB C

BCC

4. Basic Logic Gates and Functions

When analyzing logic gates it helps to visualize the three basic gate body shapes and apply a meaning to them. You first look at these body shapes without inputs attached. The one to the right has a straight back to which the inputs would be attached which means ‘ALL of its inputs.’ The second basic gate body shape has a single curved end to which the inputs would be attached. This body shape means ‘One or more of its inputs.’

The final basic gate body shape has a double curved end to which the inputs would be attached. This body shape means ‘An odd # of its inputs.’

One final item that needs to be examined before the actual gates are introduced is the inversion bubble. When applied to an output of a gate, it means ‘inversion.’ So, if a logic ‘1’ is on the input side of the bubble, a logic ‘0’ would be on the other side.

Armed with this knowledge of basic gate body shapes you can now easily understand the function of any gate by just examining the body shapes and taking into account any

ALL of its inputs

ONE OR MORE of its inputs

AN ODD # of its inputs

Inversion Bubble

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bubbles which may be present. Now, let’s take a look at the basic gates and their functions.

(1) AND Gate The AND logic operation is expressed as: = •F A B (or it could be written as:

=F AB ). The gate is shown below along with its truth table. Analyzing the basic body shape of the AND gate, we can express the meaning of this gate verbally as: “The output is a logic ‘1’ (since there isn’t a bubble) only when ALL of its inputs are logic ‘1s’.” The accompanying truth table supports this result.

AB F

0 0 00 1 01 0 01 1 1

A B F

AND Function: The AND function behaves like two switches in series. When and only when all inputs are logic ‘1’ does the output go to logic ‘1’. At all other input combinations, the output is logic ‘0’. Its uniqueness is when all inputs are logic ‘1.’ In programming, this logic is useful when you need to “mask out” certain bits in order to examine other bits of interest. The AND function is supported by an instruction in the PIC Instruction Set.

(2) OR Gate The OR logic operation is expressed as: F A B= + . The OR gate is a logic circuit that can be expressed verbally as: “the output is a logic ‘1’ when ‘one or more’ of its inputs are a logic ‘1’.”

AB F

0 0 00 1 11 0 11 1 1

A B F

OR Function: Also referred to as the Inclusive OR, the OR function behaves like two switches in parallel. Another way of looking at its operation is: “When and only when all inputs are logic ‘0’ does the output go to logic ‘0’. All other input combinations result in an output of a logic ‘1’.” Its uniqueness is when all inputs are logic ‘0’. This logic is useful when you need to set

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certain bits in a byte or word and not disturb the original other bits in a byte or word. The Inclusive OR Function is supported by an instruction in the PIC Instruction Set.

(3) NOT/Inverter Gate The Inverter logic gate has only a single input and the output is always opposite to the input logic level. The Boolean expression is F A= . Note that even though the basic body shape is a bit different from that shown in the gate shape introduction, it still has a straight rear edge which even though there is a single input, the output will be a logic ‘0’ (since there is a bubble) when ALL of its inputs (the only input) are (is) a logic ‘1’.

0 11 0

A FA F

NOT/Inverter Function: Also referred to as Complement, the Inverter logic operation results in the output being the opposite logic state of the input. The Complement Function is supported by an instruction in the PIC Instruction Set.

(4) NAND Gate

NAND gate works like an AND gate followed by an inverter (the bubble). As a matter of fact, it can be looked at as a NOT AND gate. Based on the basic body shape and the bubble, the NAND gate operates in the following manner: “the output will be a logic ‘0’ (due to the bubble) whenever ALL of its inputs are logic ‘1s’.” The NAND gates Boolean expression is F AB= . The line over the AB signifies the inversion.

AB F

0 0 10 1 11 0 11 1 0

A B F

(5) NOR Gate

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The NOR gate works like an OR gate followed by an inverter (the bubble). The NOR gates Boolean expression is: F A B= + . The operation of the NOR gate is described (based on the basic body shape and the bubble) as: “The output of the NOR gate will be a logic ‘0’ (because of the bubble) when ONE or MORE of its inputs are logic ‘1s’.”

AB F

0 0 10 1 01 0 01 1 0

A B F

(6) XOR Gate

The Exclusive OR gate (more commonly known as an XOR) gate works like a difference detector. Based on the basic body shape, its operation can be described as: “The XOR’s output will be a logic ‘1’ when an ODD number of its inputs are logic ‘1s’.” The XOR gates Boolean expression is: F AB AB A B= + = ⊕ .

AB F

0 0 00 1 11 0 11 1 0

A B F

Exclusive OR Function: The XOR gate works like a ‘similarity’ or a ‘difference’ detector. If the input bits are the same logic state, the output is a logic ‘0’. If the input bits are not the same logic state, the output is logic ‘1’. This logic function is very useful in determining if two bits, bytes, or words match. This is important in matching key codes, passwords, device id’s, node id’s, security id’s, etc. The Exclusive OR function is supported by an instruction in the PIC Instruction Set.

(7) XNOR Gate

The XNOR gate works like the similarity detector. Its Boolean expression is given in several different forms here: = + = ⊕F A B A B A B . Based on its basic body shape and the bubble, its operation can be described by: “The XOR gates output will be a logic ‘0’ (due to the bubble) when an ODD # of its inputs are a logic ‘1’.” The accompanying

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truth table supports this description. The uniqueness of the gate is that it detects the similarity of inputs.

AB F

0 0 10 1 01 0 01 1 1

A B F

(8) Buffer

Now that you have the basics down, take an inverter and feed it into a second inverter. Note that when you do this, the result will be that the output of the second inverter will be the same as the input to the first. In effect, you just performed a double inversion (of course you have also inserted some additional propagation delay, discussed later).

FA

A A

At first glance the whole thing seems pretty pointless! Why go to all that trouble if all you are going to end up with is what you started out with in the first place? In order to understand why, it has to be 1st understood that a gate is more than just a Boolean device. It is also a signal amplifier, regardless of the Boolean function it was designed to perform. Gates also act as signal amplifiers, either on-purpose or not. The problem is that there quite often (especially with Transistor-to-Transistor Logic, TTL) is a degradation (weakening) of the signal.

There are two primary problems with a weak signal source: • It may be unable to supply or sink (absorb) enough current to drive the pin(s)

connected to its output. • If there isn’t enough current then it is difficult for the attached input to perform its

task of determining the correct voltage logic level.

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With an understanding of the above points, it can be seen that there is a very good reason for this previously considered ‘pointless’ operation. This weak signal would be boosted by the two inverters shown above without changing the logic level.

There is a special type of device (not normally called a ‘gate’) designed just for this purpose called a ‘Buffer.’ Its symbol looks like the inverter without the inversion bubble on the output terminal.

5. Design Considerations

(1) TTL Fan-out

There is a practical limitation to the number of inputs which an output can drive. This limitation is class, family, and sub-family specific. Within the TTL family, as long as a sub-family is driving pins on devices from the same sub-family, the maximum ‘fan-out’ is 10. This limitation is primarily based on current (I). So, care must be taken with connections between members of different sub-families. The following table lists example fan-outs between example combinations of TTL sub-families. Discussion of the actual sub-families and their properties is reserved for a later discussion. A device which stays within its rated fan-out limitations is guaranteed to run at rated speed at worst case currents while interpreting the input logic levels correctly (if noise is ignored).

Regular TTL (TTL) will drive 10 regular TTL inputs

20 LS TTL inputs

Low Power TTL (LTTL) will drive 2 regular TTL inputs

5 LS TTL inputs

High Power TTL (HTTL) will drive 12 regular TTL inputs

40 LS TTL inputs

Schottky TTL (STTL) will drive 12 regular TTL inputs

40 LS TTL inputs

Low Power Schottky TTL (STTL) will drive 5 regular TTL inputs

10 LS TTL inputs

A A

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Excerpt from Lancaster’s TTL Cookbook1

So, what do you do if you want an output to drive more than the allowed fan-out for the available sub-family combination? The answer to the question is to use the BUFFER that we just finished discussing. The NAND gate to the right is officially driving 2 inputs, but in actuality, it is driving up to 20 inputs (10 through each buffer, assuming fan-out of buffers is 10).

(2) CMOS Fan-out

Fan-out in CMOS is another story all together. A CMOS device has an EXTREMELY HIGH INPUT RESISTANCE. The Rin is so high that input current is next to nothing. For this reason, fan-out between CMOS devices is rated at 100 inputs.

Fan-out between CMOS and TTL devices is a bit more difficult to handle. If you want to drive a CMOS device with a TTL device, the CMOS device might have a problem discerning the correct logic levels. This is because a CMOS device requires 5 volt logic 1’s and a TTL’s logic ‘1’ output could be as low as 2.7 volts. The fix for this is to apply a pull-up resistor to the output of the driving TTL device which will ‘pull-up’ the logic ‘1’ output to the level of VCC. The following figure demonstrates one such connection.

The TTL device to the right is driving a SINGLE CMOS input with a ‘pulled-up’ output. The driven CMOS can then drive to its fan-out limit.

And finally, a CMOS output can drive a SINGLE TTL input without any pull-up.

1 Lancaster, D. (1974). Excerpt from Table 1-5, p. 31, TTL Cookbook, Carmel, Indiana, Prentice Hall Publishing.

AB

Up to ratedFan-out of

Buffer

Up to ratedFan-out of

BufferNAND Gate output only sees 2 inputs

VCC

Any TTLDevice

Any SINGLECMOS Device

Up to a total of 100CMOS inputs

Input driven by unknown device. If TTL, another

pull-up is required

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(3) Tri-state Devices

As we have seen above, digital outputs can drive many input pins at the same time. However, the reverse is not true. An input pin can only be driven by a single output pin. However, quite often it is desirable to do just that! So how does the digital designer accomplish this? The answer is to use a type of device which can be SHUT OFF when another device is driving the same input pin to which they both are connected. This type of device is known as a Tri-state device. The Tri-state input shown here has an active-high Tri-state input (there isn’t a bubble associated with the input). This means that it takes a logic ‘1’ to activate the output. It is very important to note that there are what amounts to three different states or possible output conditions (thus the name ‘Tri-state’):

• When the active-high tri-state input is a logic ‘1’, the output is activated and can

either be a (depending on the logic of the associated device): o Logic ‘0’ or a o Logic ‘1’

• When the active-high Tri-state input is a logic ‘0’, the output is inactivated (turned off) and the output achieves a HIGH IMPEDANCE (HIGH RESISTANCE) state. This means that the output will look like an open-circuit to any input attached to it.

Digital devices can also be obtained with Active-low Tri-State inputs as shown to the right. The only difference in the operation of a gate with this type of input is that it takes a logic ‘0’ to activate the output.

(4) Open-Collector Outputs

The predecessor to the Tri-state device is the device with Open-Collector outputs. The outputs of these types of devices have two possible outputs:

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• Logic ‘0’ • High-Impedance.

Note that there isn’t a logic ‘1’ possibility in this type of output, at least with the output acting alone. If a logic ‘1’ is desired (as it would most likely always be), a ‘pull-up’ resistor must be added between the output and Vcc as shown: While at 1st glance, one might think that this is not as efficient a choice of device properties as the tri-state, it does have significant advantages over the tri-state device.

It is possible through the resistor selection to set the amount of current supplied to the attached input with the logic ‘1’. Remembering your basic DC material, ‘the lower the resistor value, the larger the current available to the input’. The other advantage is the flexibility/choice of the Vcc to fit any desirable voltage signal that the interface output to the needed input circuit. So, if you want 12 volts out, replace Vcc with 12 volts.

It is very important to note that this represents a very COMMON source of ENGINEER (student) mistakes. It is very common to not note, or forget, the open-collector property of the selected device in a design and then wonder why the device is not operating as expected!

6. Logic Arithmetic (Add & Subtract)

(1) The 1’s Complement The 1’s Complement of a Binary number is easily found by simply inverting each bit as is demonstrated in the following example: Example: Find the 1’s Complement of: 1100110101002

2

1

1 1 0 0 1 1 0 1 0 1 0 00 0 1 1 0 0 1 0 1 0 1 1 cm

(2) The 2’s Complement

The 2’s Complement in its most basic form is nothing more than the 1’s Complement + 1. However, in reality, it requires a few more things.

AB

VCC

Open-CollectorOutput

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• There must be a sign bit attached to the left of the number, (0 Positive). • The length of the number including the sign bit (N) must be designated. This is not

that important until the values are used for arithmetic operations. When this happens, the selected value of N must be large enough for the result of the operation.

Example: Find the 2’s Complement of the previous example: 1100110101002 (N = 13) First, the 1’s complement is found as before. However, this time a positive sign bit has been added to the number (separated from the rest of the number by a comma). Note that the given value of N is large enough for the original number and its sign bit:

2

1

0 1 1 0 0 1 1 0 1 0 1 0 01 0 0 1 1 0 0 1 0 1 0 1 1

,, cm

A 1 is added to the 1’s complement to achieve the 2’s complement. Note that a sign bit has been added to the 1. Note that the sign bit ends up as a 1 which is the NEGATVE binary sign:

1

2

1 11 0 0 1 1 0 0 1 0 1 0 1 1

11 0 0 1 1 0 0 1 0 1 1 0 0

,

,

cm

cm

+

There is a simplified or short-hand 2’s complement method that works very well:

Example: Find the 2’s Complement of the previous example using the short-hand

method: 1100110101002 (N = 13) • Starting from a binary number’s LSB (right side) working toward its MSB (left side)

o Copy down all 0s up to the first 1 and the copy down that 1 as well.

1

2

0 1 1 0 0 1 1 0 1 0 1 0 01 0 0

, cm

cm

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o Invert the rest of bits.

1

2

0 1 1 0 0 1 1 0 1 0 1 0 01 0 0 1 1 0 0 1 0 1 1 0 0

,,

cm

cm

7. A Simple One-bit ADDER circuit

The truth table to the right represents a one-bit ADDER circuit which creates the following mathematical expression:

A0 + B0 = C0 and Cout

A0, B0, & Cin are inputs and S0 and Cout are the outputs. The 0 subscript indicates the operation is being performed on the LSBs of two numbers: A0 and B0.

The logic circuit which implements the table is shown below:

000

011

B0A0 Cin Cout

0 01 1

1 10

00

1111

0 010

1 01 1

S0

000

0 11 00 10 11 1

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If we use the above logic circuit in a modular device format to represent two one-bit adders, then a multiple bit (4 bits, or a nibble) addition can be easily presented as:

A0 B0

S0S1

A2

S2

A3

S3Cout

B1B2B3

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

A1

Some practice examples to be performed by hand in the same way that the hardware would solve them include:

1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 0 1 0 0 10 1 1 1 0 1 1 0 1 1 1 1 0 1 1 1 0 1 1 0 1 1 1 1+ + + + + +

We can take this ADDER circuit and make a minor addition to each stage in order to be able to use the circuit to both add and to subtract. We can now look at the 4 bit subtraction problem as:

3 2 1 0 3 2 1 0

3 2 1 0 3 2 1 0

3 2 1 0 3 2 1 0

2 '

out out

A A A A A A A AB B B B B B B B s complement

C S S S S C S S S S− ⇒ + ⇐

All that was needed in order to subtract by addition was to find the 2’s complement of the subtrahend. The subtrahend becomes negative and then an addition can be performed in order to subtract.

We can turn the modular 4-bit adder into a 4-bit ADDER / SUBTRACTOR by adding in an XOR gate on each stage in place of the Bx inputs as shown below. One input on each XOR gate is tied to a control signal (M) which controls the operation of the ADDER / SUBTRACTOR.

A0

B0

S0S1

A2

S2

A3

S3Cout

B1B2B3

M

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

A1

3 2 1 0

3 2 1 0

3 2 1 0out

A A A AB B B B

C S S S S+

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• M is used to control the addition with original number B or add with its 1’s complement: o M = 0 that causes a regular addition. o M = 1 causes a subtraction by causing each XOR gate to invert its Bx bit by placing a

logic ‘1’ from M on one of the two pins and Bx on the other. The resulting operation is A + (1’s complement of B).

o The operation becomes A – B when a 1 is added to the final result. This is accomplished by feeding M (=1) into the Carry In input of the LSB Adder.

Let’s use the 4-bit adder to perform A – B 7 – 4 0111 – 0100: The M input will control if the circuit will add (M = 0) or subtract (M = 1). The M value will also be the Carry-in to the Full Adder LSB.

Since it is desired to subtract the two numbers, M is set to 1. This will turn the XOR gates into the equivalent of inverters and each of the B-bits are inverted as shown here.

The LSB Adder operation starts out with the M bit of (1) being carried into column 0. The B bit gets inverted and you end up with:

3 2 100

3 2 100

3 2 1

11 111 After the 0 1 1 1 11 1 XOR 0 1 0 0 1

10 inversion 11

out

inin

out

CCC A A AAA B B BBB C S S S

⇒⇒⇒⇒⇒ ⇒ ⇒ ⇒

− ++ ⇒⇒

1

0

10

S3Cout

010

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

1

MS2 S1 S0

A B A BA B A B

1

0

10

S3Cout

010

1

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

1

MS2 S1 S0

A B A BA B A B11 0 1

1

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There will be a Carry-out of 1 into the next stage. Moving on to column 1 we see that the Carry Out bit of (1) from column 0 is applied to column 1. The B bit gets inverted and you end up with:

3 211

3 211

3 2

11 1 111 After the 0 1 1 1 1 11 1 XOR 0 1 0 0 1 1

10 inversion 1 11

out

inin

out

CCC A AAA B BBB C S S

⇒⇒⇒⇒⇒ ⇒ ⇒ ⇒

− ++ ⇒⇒

There will be a Carry-out of 1 into the next stage The current status of the 4-bit adder is shown here.

Moving on to column 2 we see that the Carry out bit of (1) from column 1 is applied to column 2. The B bit gets inverted and you end up with:

322

322

3

11 1 1 111 After the 0 1 1 1 1 1 11 1 XOR 0 1 0 0 0 1 1

01 inversion 0 1 10

out

inin

out

CCC AAA BBB C S

⇒⇒⇒⇒⇒ ⇒ ⇒ ⇒

− ++ ⇒⇒

There will be a 0 Sum out with a Carry-out of 0 into the next stage.

1

0

10

S3Cout

010

1

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

1

MS2 S1 S0


1 1

110

1 1

1

0

10

S3Cout

010

1

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

1

MS2

S1 S0


1 1

11

1

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Finally, we move on to column 3 where the Carry Out bit of (1) from column 2 is applied to column 3. The B bit gets inverted and we get:

( )

33

33

1 1 1 1 1 111 After the 0 1 1 10 1 1 1 0 0 XOR 1 0 1 10 1 0 010 inversion 0 0 1 110

out

inin

out

CCCAABB C

⇒⇒⇒⇒⇒ ⇒ ⇒ ⇒ +−

+ ⇒⇒

1

0

10

S3Cout

010

1

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

Inputs

Carry In

Carry Out

Output

1

MS2 S1 S0


1 1

110

1 1

01

1

The final Carry Out would end up being the Carry In to the next stage if it exists. If it does not exist, the Carry Out is discarded. With that bit being discarded here, we see that we ended up with the expected binary 3 result. The following are examples that can be easily implemented with above mentioned circuit and obtain the subtraction results. These operations can also be implemented with the PIC16FXXX microcontrollers. The following examples are meant to be performed by hand calculations in the same way that the computer will be performing them for comparison.

1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 0 1 0 0 10 1 1 1 0 1 1 0 1 1 1 1 0 1 1 1 0 1 1 0 1 1 1 1− − − − − −

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8. The Environment and Software Operations

Required Material With the basic knowledge of microcontroller operation and gate mathematics, the area of study is the application of this knowledge to programming a microcontroller to perform desired/designed tasks. The equipment and system that you need are: • Hardware

o a PC with either USB or DB25 port, o the PIC training system with power supply, o USB A-B Cable

• Software o MPLAB IDE, o PICKIT2

The equipment and programs relate to each other as shown below:

PC running MPLAB IDE that does editing on the Assembly source codes, compilation,

simulation, and PICKIT2 does the downloading of the source

codes and debugging.

PC System:PIC Training

System Board:

The training system has the target PIC MPU in the 40 pin

ZIF socket that is selectable on PIC package and choice of

program/operation functions via two DIP switches.

USB

DB25

(1) MPLAB IDE Operation

The operation of the Microchip MBLAB IDE is described as: • Running MPLAB IDE

o Start> Program> Microchip MPLAB IDE > MPLAB IDE • Creating Your Source Code (Assembly Language)

o File> New or o Open> Filename.XXX ;Retrieve old text file

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• Save Your Source Code (Assembly Language) o File> Save or o File> Save As ;Select Assembly Source File for XXX.ASM source

; code file ;Select C Source File for XXX.H header file

• Creating a Project

o Project> Project Wizard o Select Device: PIC16F84A o Select Tool Suite: Use default if your MPLAB is installed as recommended o Name Project: Specify the Project Name and its Project Directory o Select Source File: Add source file and associate Header file to the Project o Project Wizard Summary: Examine the project parameter o Finish Project o Project Window: Display all the project files

Important Note: You need to make sure the environment is set up correctly. This is based on MPLAB IDE 7.5, the other version’s folder may vary but the filenames are the same. o During your project created under the Project Wizard… menu. o After the Project Wizard creation under the project menu, choose Select Language

Toolsuite.

• After the Project Wizard creation under the project menu, o choose Set Language Tool Locations…, o select Microchip MPASM Suite, o select Executable.

• Make sure the following linkages are setup correctly: o Microchip MPASM Suite o MPASM Assembler (mpasmwin.exe) is located at C:\Program Files\MPLAB IDE\MCHIP_Tools\MPASMWIN.EXE

o MPLINK Object Linker (mplink.exe) is located at C:\Program Files\MPLAB IDE\MCHIP_Tools\MPLINK.EXE

o MPLIB Library (mplib.exe) is located at C:\Program Files\Microchip\MPASM Suite\mplib.exe

• Building the Project

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o Project> Build All o Output Window: Display the compiling/assembling results

• Running the Code o Debugger> Reset or F6 o Debugger> Run or F9 o Debugger> Halt or F5 o Debugger> Step Into or F7

• Running the MPLAB Simulation o Debugger> Select Tool> MPLAB Sim

• Watch Windows o View> Watch o Select Add SFR o Select Add Symbol o View> File Registers o View> Program Memory o View> EEPROM o View> Special Function Registers

• Re-arrange the Displayed Windows o Window Manu> Tile Vertically o Window Manu> Tile Horizontally

• Setting Break Point o Debugger> Reset or F6 o Mouse Point and Right Click or Double Clicks; Select Set Break Point

• Tracing Code o Debugger> Settings o Select Trace/Pins o View> Simulator Trace

• Clear Memory o Debugger> Clear Memory o Select All Memory ; You need to re-compile the source code

; if you choose this Program Memory ; You need to re-compile the source code if you

; choose this GPRs

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EEPROM Configuration Bits

9. Header File and Source Codes In the PIC16FXX working environment • MPLAB IDE handles the editing, compilation/assembling, & simulation of the user’s source

code, • PICKIT2 handles the downloading of the .HEX file into the PIC installed in the PIC

Training System, and the • Training System provides the controls and connections for the hardware components on

the board.

In order to compile/assemble the user’s source code properly, MPLAB IDE needs to have all the defined registers names which identify (map) their dedicated addresses or registers. This is the purpose of the HEADER file that should be the INCLUDE file in the user’s source code, every time before the compilation/assembling process. There will be an assignment that requires everyone to create one’s own HEADER file for future use. Everyone will be required to type all the names that have defined register bytes and bits per PIC16FXX data sheet’s definition.

Note: This typing exercise to create a HEADER file via the MPLAV IDE

editor may not make much sense at this moment, but you will soon understand how it achieves its objective of defining the registers bytes and bits as specified in the data sheet. You will find that it is MUCH easier to program with variable names instead of numbers.

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Student Assessment 1. Measuring questions during teaching

Convert the following numbers as indicated: AB16 to binary _______ ________________ 001110112 to hex ________________________ 4558 to decimal ________________________ 12510 to octal ________________________ 23410 decimal to hex ________________________ 10011101011002 to its 1’s complement ________________________ 10011101011002 to its negative 2’s complement: ________________________

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Practice Test Questions

1. Convert the following numbers as indicated:

1A16 to binary _______________________________ 1100 01112 to hex _______________________________ 3778 to decimal _______________________________ 25510 decimal to binary _______________________________ 23C816 to decimal _______________________________ 10111000110012 to hex _______________________________ 2. How many flags are there in the STATUS register that are used to indicate logic operation

results only?

3. How many flags are there in the STATUS register that are used to indicate both logic and

math operation results?

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Activities

Homework

1. Convert 715910 to Binary, Octal, and Hex formats. (9 Points) 2. Convert 836CE16 to Binary, Decimal, and Octal formats. (9 Points) 3. Convert 6578 to Binary, BCD, Decimal, and Hex formats. (12 Points) 4. Convert 110001010011001BCD to Binary, Decimal, Octal, and Hex. (12 Points) 5. Perform the following arithmetic operations in Binary and present your results in HEX and also

indicate the C & Z & DC flags status after each operation: (18 Points) (NOTE: 0X is another way of indicating that the value is HEX)

(a) 0X48 + 0X75 (b) 0XEF + 0XAC (c) 0X49 + 0X9D (d) 0X56 - 0XAD (e) 0X34 - 0XE7 (f) 0XFE - 0X02 6. Perform the following logic operations in Binary and present your results in Hex and also

indicate the C & Z & DC flags status after each operation: (18 Points)

(NOTE: 0X is another way of indicating that the value is HEX) (a) 0X40 AND 0X7F (b) 0XE0 IOR 0XAF (c) 0X49 XOR 0X49 (d) 0XFF AND 0XAD (e) 0X00 IOR 0XE7 (f) 0XFE XOR 0XFF

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