lessons learned the hard way: fpga pcb integration challenges dave brady & bruce riggins

Lessons Learned The Hard Way: FPGA PCB Integration Challenges

Dave Brady & Bruce Riggins

Brady/RigginsBrady/Riggins Page 2 MAPLD 2005/P131MAPLD 2005/P131

Agenda

Design Overview Design Challenge Summary Lessons Learned Suggested Strategies


System Design Challenges

Complex system implemented using multiple high-pin count FPGAs PCB bus speeds > 150 Mhz PCB physical size restricted Implementation team (s)

— System design, 2 engineers System architecture, Embedded CPU h/w design

— PCB design, 1 engineer Functional design, PCB timing, PCB signal integrity

— PCB physical design, 1 engineer PCB place and route, design for manufacturing

— FPGA design, 5 engineers RTL HDL development

— DSP design, 1 engineer C algorithm development

— Embedded software development, 2 engineers


Conceptual Design Overview

CPU & Embedded Platform

Custom (ASIC) Logic

Glue Logic

PCB

FPGA 1

FPGA Boot Module

Communication Module

Vo

ltag

e

Re

gu

lato

rs/G

en

era

tors

DRAMMemoryModules

Communication Module

DSP

Custom (ASIC) Logic

Glue Logic

FPGA 2

Clo

ck

Ge

ne

rato

rs


Design Challenge Summary

1. Overdriven signals

2. Cross talk

3. Simultaneous switching outputs

4. Meeting system performance specifications

5. Minimizing PCB manufacturing costs

6. Learning the FPGA device-specific I/O design rules

7. Maintaining (updating) FPGA symbols for the PCB schematic

8. Leveraging the complete design team


Lessons Learned: Increasing PCB CostsStarted with FPGA Timing

PCB

FPGA 1 FPGA 2

Tp > Spec by 100 ps

FPGA 1 pin-to-pin timing exceeded spec by 100 ps

FPGA designer increased drive strength

Pin-to-pin timing meets spec


Increasing PCB CostsInduced Signal Ringing on PCB (contd.)

Increasing drive strength on FPGA 1 output pin induced PCB signal ringing

PCB engineer identified

PCB

FPGA 1 FPGA 2

Tp < Spec

Time

Vo

lts


Increasing PCB CostsInduced Signal Ringing on PCB (contd.)

PCB engineer began inserting termination networks

Results: PCB

component count

PCB via count

PCB trace count

PCB routability

PCB costs

PCB

FPGA 1 FPGA 2

Tp < Spec

R


Lessons Learned: Increasing PCB Costs --Scoping the Problem

Not an issue for a single trace

Design contained four 64-bit high-speed data busses— All 256

signals were impacted!

PCB

FPGA 1 FPGA 2

Tp < Spec

B1data(0:63)

B2data(0:63)

B3data(0:63)

B4data(0:63)


Lessons Learned: Big Busses Cross Talk

Busses laid out on PCB with matching trace (tp) lengths

Identified by the PCB engineer

Traditional solutions:

— Increase trace-to-trace separation

— Leverage lower-dielectric PCB laminates

PCB

FPGA 1 FPGA 2

Tp < Spec

B1data(0)

B1data(1)

B1data(2)

B1data(63)

t

V

t

V


Lessons Learned: Big Busses Simultaneous Switching Outputs

Grouping busses into the same pin bank improves PCB routability

FPGA pin banks are limited in the current they may source— Leads to SSO

issues

PCB

FPGA 1 FPGA 2

Tp < Spec

B1data(0:63)

B2data(0:63)

B3data(0:63)

B4data(0:63)

SSO

t

V


Balance is the Key

Signal Too Slow Signal Ringing

FPGA I/O Drive Strength Setting

Simultaneous Switching Output Issues Signal Cross Talk

FPGA I/O Rail Voltage Setting


TPD=Pass

TPD=Pass

TPD=Fail

Lessons Learned: Leveraging I/O Flexibility

Both FPGA devices designed to specs

Unable to meet system timing specs


TPD=PassTPD=Fail

TPD=Fail

Leveraging I/O Flexibility (contd.)

Changed the physical location of signals on the FPGA

Unable to meet timing in one FPGA


TPD=PassTPD=Pass

TPD=Pass

Leveraging I/O Flexibility (contd.)

Changed the physical location of signals (again)

Finally met system timing specs

Simple for a single signal Complex for wide busses


Lessons Learned: The Domino Effect of Pin Swapping

11

22

33


All Pins Are Not The Same

CCLK

DONE M0

M1

M2

Pin Bank

3GIO

Clock

PROG_B

Single Ended

Double Ended


Virtex II Pro: Input AC Characteristics

Source: Xilinx website

Vendor Family Package Speed Grade IO Standard Io Sub Option

Xilinx Virtex II Pro FG256 "-7 (fastest)" LVTTL 4ma, SlowXilinx Virtex II Pro FG256 "-7 (fastest)" LVTTL 24ma, SlowXilinx Virtex II Pro FG256 "-7 (fastest)" LVTTL 4ma, FastXilinx Virtex II Pro FG256 "-5" LVTTL 4ma, SlowXilinx Virtex II Pro FG256 "-7 (fastest)" LVCOMS33 4ma, SlowXilinx Virtex II Pro FG256 "-7 (fastest)" LVCOMS25 4ma, SlowXilinx Virtex II Pro FG256 "-7 (fastest)" LVCOMS18 4ma, SlowXilinx Virtex II Pro FG256 "-7 (fastest)" LVCOMS15 4ma, SlowXilinx Virtex II Pro FG256 "-7 (fastest)" LVDCI LVDCI_33Xilinx Virtex II Pro FG256 "-7 (fastest)" LVDCI LVDCI_25Xilinx Virtex II Pro FG256 "-7 (fastest)" LVDCI LVDCI_18Xilinx Virtex II Pro FG256 "-7 (fastest)" LVDCI LVDCI_15Xilinx Virtex II Pro FG256 "-7 (fastest)" LVDCI LVDCI_DV2_25Xilinx Virtex II Pro FG256 "-7 (fastest)" LVDCI LVDCI_DV2_18Xilinx Virtex II Pro FG256 "-7 (fastest)" LVDCI LVDCI_DV2_15Xilinx Virtex II Pro FG256 "-7 (fastest)" LVDS LVDS_25Xilinx Virtex II Pro FG256 "-7 (fastest)" LVDS LVDS_25_DCI

delay (ns)Operating Frequency

(Hz)0.91 1.10E+090.91 1.10E+090.91 1.10E+09

1 1.00E+090.88 1.14E+090.84 1.19E+091.13 8.85E+081.2 8.33E+080.79 1.27E+090.84 1.19E+090.91 1.10E+090.97 1.03E+090.84 1.19E+090.91 1.10E+090.97 1.03E+091.15 8.70E+081.15 8.70E+08

Tiopi: Pad To Input Delay






(Hz)1.91 5.24E+081.91 5.24E+081.91 5.24E+082.15 4.65E+081.88 5.32E+081.84 5.43E+082.13 4.69E+082.2 4.55E+081.79 5.59E+081.84 5.43E+081.91 5.24E+081.97 5.08E+081.84 5.43E+081.91 5.24E+081.97 5.08E+082.15 4.65E+082.15 4.65E+08

Tiopid: Pad to Input with delay buffer







(Hz)0.93 1.08E+090.93 1.08E+090.93 1.08E+091.02 9.80E+080.9 1.11E+090.86 1.16E+091.15 8.70E+081.22 8.20E+080.81 1.23E+090.86 1.16E+090.93 1.08E+090.99 1.01E+090.86 1.16E+090.93 1.08E+090.99 1.01E+091.17 8.55E+081.17 8.55E+08

Tiopli: Pad to IQ via latch



Resolving Symbol Size

1500 Pin device

560 Pin device

100 Pin device


Synchronizing the FPGA & PCB Flows

Physical Placement & Connectivity


Multiple Perspectives That Don’t Match

FPGA and PCB design teams typically do not communicateFPGA and PCB design teams typically do not communicate


Suggested Strategies: Eliminate Team Communication Barriers

System Designer

PCB Layout

PCB Timing Analysis

PCB Signal

Integrity

FPGA Designer

Embedded System (CPU)

Designer

DSP Designer

We do the FPGA I/O Design








PCB (Schematic)

Designer


General Tips & Tricks Leverage Signal Integrity “What if” Analysis Early

— Anticipate signal ringing, cross talk, ground bounce, etc.— Develop system constraints to minimize PCB components— Make trade-offs at the system level

Run Signal Integrity Analysis on the PCB Design— Interactive part of the normal design process— NOT a design verification “check box”

Leverage Embedded Resistors— Some signal termination is un-avoidable— Minimize PCB size— Reduced PCB costs

Leveraging Gigabit Transceivers Reduces PCB Traces BUT— GHz signals High-Speed (& cost) PCB laminates— Introduces additional PCB components (clock generators, voltage regulators, etc)— Introduces additional termination topology requirements

Re-partition the FPGA Design to Optimize PCB Performance— Alternative to leveraging Gigabit transceivers— Will not work for every design— Worked for this design


Routing Comparison

Routing after I/O Designer optimization— 49% length reduction (320 ps less delay)— Reduced routing congestion and excess


PCB Layer Reduction

PCB

Optimized IOFPGA 1 FPGA 2


PCB designP

in-out assign

Reduce Overall System Design Time Concurrent design of FPGA and PCB Optimize system performance & reduce manufacturing costs

— Solution: Bi-directional FPGA I/O design

FPGA design

Pin

-ou

t chan

ges

Pin

-ou

t chan

ges

Pin

-ou

t chan

ges

PCB design

I/O Designer

•Reduced Design Time•Enhanced System Integration•Optimized Performance•Lowered Manufacturing Costs


Provide PCB Designers an Intelligent FPGA I/O Design Tool


Show FPGA Designers the PCB Design


Provide Everyone Detailed Control


Automate Pin Planning

Routing after I/O Designer optimization— 49% length reduction (320 ps less delay)— Reduced routing congestion and excess


100Mhz Clock

Clock to Output = PassOutput to Setup = Pass

Board Interconnect Budget = FAIL

I/O Design Planning Benefits

Meet performance constraints— Overall timing constraints

FPGA in-chip On board

— PCB signal integrity constraints

— Comply with FPGA technology I/O rules

Eliminate PCB signal layersPCB

Optimized IOFPGA 1 FPGA 2


The Complete Flow Including PCB Physical Design

Flow Integration — Schematic to layout— Layout to I/O pin

planning— FPGA Designer has

visibility into the PCB design

— PCB designer has access to I/O design rules

— Fast pin swaps— Automatic bus

untangling

lessons learned the hard way: fpga pcb integration challenges dave brady & bruce riggins

Documents

pcb timing

pcb component count

pcb contd

pcb schematicleveraging

presentation subject

increasing pcb costsstarted

engineerfunctional design

manufacturingfpga design