lesson 5

UNIT 5:Numbers and Displays APRI 13 - 2007VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITYINTEGRATED CIRCUIT DESIGN RESEARCH AND EDUCATION CENTER(ICDREC)

DEPUTY DIRECTOR

PURPOSE This is an exercise in designing combinational circuits that can perform:

Binary-coded-decimal (BCD) addition

Binary-to-decimal number conversionVIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Part 1: Display the decimal values on the 7-segment displaysVIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

ContentWe wish to display on the 7-segment displays HEX3 to HEX0 the values set by the switches SW 15-0 . Let the values denoted by SW15-12 , SW11-8, SW7-4 and SW3-0 be displayed on HEX3, HEX2, HEX1 and HEX0, respectively. Your circuit should be able to display the digits from 0 to 9, and should treat the valuations 1010 to 1111 as dont-cares. VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

StepsCreate a new project which will be used to implement the desired circuit on the Altera DE2 board. Write a Verilog le that provides the necessary functionality. Include this le in your project and assign the pins on the FPGA Compile the project and download the compiled circuit into the FPGA chip Test the functionality of your design by toggling the switches and observing the displays. VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Instruction B H0 0 0 0 0 0 0 0 0 0 10 0 0 1 1 0 0 1 1 1 10 0 1 0 0 0 1 0 0 1 00 0 1 1 0 0 0 0 1 1 00 1 0 0 1 0 0 1 1 0 00 1 0 1 0 1 0 0 1 0 00 1 1 0 1 1 0 0 0 0 00 1 1 1 0 0 0 1 1 1 11 1 1 0 0 0 0 0 0 0 01 0 0 1 0 0 0 1 1 0 01 0 1 0 x x x x x x xVIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Mimimize Boolean functionVIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Using Karnaugh map to minimal expression of a Boolean function HEXi[0] = (B[2] & ~B[0]) | (~B[3] & ~B[2] & ~B[1] & B[0])HEXi[1] = (B[2] & ~B[1] & B[0]) | (B[2] & B[1] & ~B[0]) HEXi[2] = (~B[2] & B[1] & ~B[0]) HEXi[3] = (~B[2] & ~B[1] & B[0]) | (B[2] & ~B[1] & ~B[0]) | (B[2] & B[1] & B[0]) HEXi[4] = (~B[1] & B[0]) | (~B[3] & B[0]) | (~B[3] & B[2] & ~B[1]) HEXi[5] = (B[1] & B[0]) | (~B[2] & B[1]) | (~B[3] & ~B[2] & B[0]) HEXi[6] = (B[2] & B[1] & B[0]) | (~B[3] & ~B[2] & ~B[1]) VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Part1 Case Statementmodule bcdto7seg(B,H);input [3:0]B;output[6:0]H;reg[6:0];always @(B)case (B)(code not show)endcaseendmoduleVIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Part 2: Convert binary to decimalVIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Converts a four-bit binary number V = v3 v2 v1 v0 into its two-digit decimal equivalent D =d1d0The intent of this exercise is to use simple Verilog assign statements to specify the required logic functions using Boolean expressions. Your Verilog code should not include any if-else, case, or similar statements. ContentVIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

InstructionVIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Minimization for Boolean function of circuit Az = 1 iff V > 9z = VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Minimization for Boolean function of circuit B (1 of 2)VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Minimization for Boolean function of circuit B (2 of 2)VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Boolean function for circuit Cz = 0, HEX1 [0:6]= 7b1111111z = 1, HEX1 [0:6] = 7b1001111So, we have:HEX1 [0:6] = 7b1 1111Verilog code:assignHEX1[6:0] = {4b1111,~z,~z,1b1}VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

StepsMake a Quartus II project. Compile the circuit and use functional simulation to verify the correct operation of your comparator, multiplexers, and circuit A. Augment your Verilog code to include circuit A in Figure 1 as well as the 7-segment decoder. Change the inputs and outputs of your code to use switches SW 3-0 on the DE2 board to represent the binary number V , and the displays HEX1 and HEX0 to show the values of decimal digits d1 and d0 . Recompile the project, and then download the circuit into the FPGA chip. Test your circuit by trying all possible values of V and observing the output displays. VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

PART2 BEHAVIORAL ABSTRACTIONSN = 7b1111111n = 7b1111111 if binarynum 9VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Part 3 : Ripple-Carry AdderVIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

ContentDesign a Ripple-Carry adder using Full adder modulesA circuit for a full adder, which has the inputs a, b, and ci , and produces the outputs s and co . S:sum bit , co:carry bitVIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

StepsCreate a new Quartus II project. Write a Verilog module for the full adder subcircuit and write a top-level Verilog module that instantiates four instances of this full adder. Use switches SW7-4 and SW3-0 to represent the inputs A and B , respectively. Use SW 8 for the carry-in cin of the adder. Connect the SW switches to their corresponding red lights LEDR, and connect the outputs of the adder, cout and S , to the green lights LEDG. Include the necessary pin assignments for the DE2 board, compile the circuit, and download it into the FPGA chip. Test your circuit by trying different values for numbers A, B , and c in VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

PART3 BEHAVIORAL ABSTRACTIONSWe use arithmetic operator +In Verilog, a reg type is interpreted as an unsigned numberIn Verilog, a integer type is interpreted as a signed number in 2s complement form with the rightmost bit as the least significant bit.The net type (wire, wor,wand) is interpreted as unsigned numbersThus, to synthesize an unsigned arithmetic operator, the net or reg type is used.VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Part 4: Adds 2 BCD digits VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

ContentUsing conversion of binary numbers into decimal digits to design a circuit that adds two BCD digits. The inputs to the circuit are BCD numbers A and B , plus a carry-in, cin . The output should be a two-digit BCD sum S1 S0 .

Note that the largest sum that needs to be handled by this circuit is S1 S0 = 9 + 9 + 1 = 19. Write your Verilog code using simple assign statements to specify the required logic functions-do not use other types of Verilog statements such as if-else or case statements for this part of the exercise. VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

StepsCreate a new Quartus II project for your BCD adder You should use the four-bit adder circuit from part III to produce a four-bit sum and carry-out for the operation A + B . A circuit that converts this 5-bit binary into 2 BCD digits S1S0 can be designed in a very similar way as the binary-to-decimal converter from part II.

VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Use switches SW7-4 and SW3-0 for the inputs A and B, respectively, and use SW 8 for the carry-in. Display the BCD values of A and B on the 7-seg displays HEX6 and HEX4, and display S1 S0 on HEX1 and HEX0. Since your circuit handles only BCD digits, check for the cases when the input A or B is greater than 9. If this occurs, indicate an error by turning on the green light LEDG 8 . Download circuit into the FPGA chip and test it


Boolean function of circuit AY = X3X2 + X3X1Y = 1 iff X[3:0] > 9Verilog code for circuit A:assign LEDG[8] = ((A[3] & A[2]) | (A[3] & A[1]) ) | ((B[3] & B[2]) | (B[3] & B[1]) ) VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Boolean function of circuit BIf C = 0 , S0_M = S0If C = 1


Implementation of circuit BVIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Implementation of circuit CHEX1 = 7b1111111 iff Cout = 0 and S1 = 0HEX1 = 7b1001111 iff Cout = 1 or S1 = 1 Verilog code : assign HEX1 = {1b1, ~(S1|Cout),~(S1|Cout), 4b1111};VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Part 5 : Add two 2-digit BCD numbers to three-digit BCD VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

ContentDesign a circuit that can add two 2-digit BCD numbers, A1 A0 and B1 B0 to produce the three-digit BCD sum S2S1S0. Use two instances of your circuit from part IV to build this two-digit BCD adder. VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

StepsUse switches SW15-8 and SW7-0 to represent 2-digit BCD numbers A1A0 and B1B0, respectively. The value of A1 A0 should be displayed on the 7-segment displays HEX7 and HEX6, while B1 B0 should be on HEX5 and HEX4. Display the BCD sum, S2S1S0, on the 7-segment displays HEX2, HEX1 and HEX0. Download the circuit into the FPGA chip, and test its operation. VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Part 6: Add two 2-digit BCD numbers to three-digit BCD using if-else statements VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

ContentDesign a circuit that can add two 2-digit BCD numbers, A 1 A0 and B1 B0 to produce the three-digit BCD sum S2S1S0.But it different part 5 by using if-else statements along with the Verilog > and + operators.VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Pseudo-codeT0 = A0 + B0if (T0 >9) thenZ0 = 10;c1 = 1;elseZ0 = 0;c0 = 0;endifS0 = T0 Z0 T1 = A1 + B1 + c1 if (T1 > 9) then Z1 = 10; c2 = 1; else Z1 = 0; c2 = 0; endif S1 = T1 Z1 S2 = c2VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Part 7 : Converts a 6-bit binary number into a 2-digit decimal number VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

ContentDesign a combinational circuit that converts a 6-bit binary number into a 2-digit decimal number represented in the BCD form. Use switches SW5-0 to input the binary number and 7-segment displays HEX1 and HEX0 to display the decimal number. VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

StepsCreate a new Quartus II project for your Verilog code. Use the Quartus II RTL Viewer tool to examine the circuit produced by compiling your Verilog code. Download your circuit onto the DE2 board VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Instructionif (bin6 < 10) bcd_h = 4'h0; bcd_l = bin6[3:0];Endif

if (bin6 < 20)bcd_h = 4'h1;bcd_l = /* bin6 - 10 */ bin6[3:0] + 4'h6; // -10 = 11110110. So, add 6Endif


if (bin6 < 30)bcd_h = 4'h2;bcd_l = /* bin6 - 20 */ bin6[3:0] + 4'hC; // -20 = 11101100. So, add 12Endif

if (bin6 < 40)bcd_h = 4'h3;bcd_l = /* bin6 - 30 */ bin6[3:0] + 4'h2; // -30 = 11100010. So, add 2endif


if (bin6 < 50)bcd_h = 4'h4;bcd_l = /* bin6 - 40 */ bin6[3:0] + 4'h8; // -40 = 11011000. So, add 8 Endif

if (bin6 < 60)bcd_h = 4'h5;bcd_l = /* bin6 - 50 */ bin6[3:0] + 4'hE; // -50 = 11001110. So, add 14 Endif


elsebcd_h = 4'h6;bcd_l = /* bin6 - 60 */ bin6[3:0] + 4'h4; // -60 = 11000100. So, add 4 end


HomeworksVIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

Exercise 1Design a circuit that can Multiply two 1-digit BCD numbers, A and B to produce the 2-digit BCD sum S1S0. Write your Verilog code using simple assign statements to specify the required logic functions-do not use other types of Verilog statements such as if-else or case statements for this part of the exercise . Perform the steps below: 1.Use switches SW7-4 and SW3-0 to represent 1-digit BCD numbers A and B, respectively. The value of A should be displayed on the 7-segment displays HEX6, while B should be on HEX3. Display the BCD sum, S1S0, on the 7-segment displays HEX1 and HEX0. 2.Make the necessary pin assignments and compile the circuit. 3.Download the circuit into the FPGA chip, and test its operation


Exercise 2Repeat the exercise 1 but you can use if-else statements along with the Verilog > and + operators.VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY NGO DUC HOANG

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lesson 5

Documents

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b0 b2 b1 b0 hexi4

b2 b0 hexi6

b1 hexi5

b1 b0hexi1

b0 hexi2

b0 hexi3

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