lecture7 wires (1)

7/21/2019 Lecture7 Wires (1)

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EE415 VLSI Design 1

The WireThe Wire

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]


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EE415 VLSI Design 2

The WireThe Wire

transmitters receivers

schematics physical


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EE415 VLSI Design 3

Interconnect Impact on ChipInterconnect Impact on Chip


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EE415 VLSI Design 4

Wire ModelsWire Models

All-inclusive modelapacitance-only


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EE415 VLSI Design 5

Impact of Interconnect ParasiticsImpact of Interconnect Parasitics

!nterconnect parasitics reduce reliability

affect performance and po"er consumptionlasses of parasitics apacitive

Resistive

!nductive


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EE415 VLSI Design 6

Pentiu

rP

n

i

II

Nature of InterconnectNature of Interconnect

Local Interconnect

lo!al Interconnect

SLocal " S#echnologySlo!al " S$ie

Source%In

tel


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EE415 VLSI Design 7

INTERCONNECTINTERCONNECT


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EE415 VLSI Design 9

Capacitance of Wire InterconnectCapacitance of Wire Interconnect

VDD VDD

Vin

Vout

M'

M2

M(

M)Cdb2

Cdb'

Cgd'2

Cw

Cg)

Cg(

Vout2

*anout

!nterconnect

VoutVin

CL

Simplifie&Mo&el


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EE415 VLSI Design 10

Capacitance: The Parallel Plate ModelCapacitance: The Parallel Plate Model

Dielectric

Substrate

L

W

H

tdi

Electrical-field lines

Current flow

WLt

c

di

di

int

=

LL

Cwire

SSS

SS

1=

=


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Permittivity alues of !ome "ielectricsPermittivity alues of !ome "ielectrics

(.' + (.)olyimides or%anic

2.'#eflon A*

''./ilicon

1.Alumina pac3a%e

/.ilicon nitride

4lass epo5y 6s

(.1 + ).ilicon dio5ide

2.7 + 2.8Aromatic t$ermosets i9:

'.Acro%els

'*ree space

diMaterial


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#ringing Capacitance#ringing Capacitance

W - H/2H

+

(a)

(b)


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#ringing versus Parallel Plate#ringing versus Parallel Plate

-from [6a3o%lu81].

H/T

H/T

W/T

HT


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!ources of Inter$ire Capacitance!ources of Inter$ire Capacitance

"ire; pp< frin%e< inter"ire ; di=tdi&9

< 2di=lo%tdi=>

< di=tdi>9

inter'ire

fringe

pp

W W

W

H

H

H

tdi

tdi

tdi


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Wiring CapacitancesWiring Capacitancesiel& cti*e Poly l1 l+ l, l-

oly 88

)

Al' (0 )' /

)0 )/ )

Al2 '( ' '/ (7

2 2/ 21 )

Al( 8.1 1.) '0 ' )'

'8 '1 20 2/ )1

Al) 7. 7.8 / 8.1 ' (

') ' ' '8 2/ )

Al .2 .) .) 7.7 1.' ') (8'2 '2 '2 ') '1 2/ 2

frin%e in a*=mpar. plate in a*=m2

Poly l1 l+ l, l- l.

!nter"ire ap )0 1 8 8 8 ''

per unit "ire len%t$ in a*=m for minimally-spaced "ires


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"ealing $ith Capacitance"ealing $ith Capacitance 9o" capacitance lo"-3 dielectrics insulators

suc$ as polymide or even air instead of i?2 family of materials t$at are lo"-3dielectrics

must also be suitable t$ermally and mec$anically and

compatible "it$ copper interconnect

opper interconnect allo"s "ires to be t$inner"it$out increasin% t$eir resistance, t$erebydecreasin% inter"ire capacitance

?! silicon on insulator to reduce @unction

capacitance


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INTERCONNECTINTERCONNECT


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Wire ResistanceWire Resistance

9

&

>

R ; 9

> &

$eet Resistance R

R' R2;

;

9

A;

Material

(

/m)

ilver A% '.7 5 '0-8

opper u './ 5 '0-8

4old Au 2.2 5 '0-8

Aluminum Al 2./ 5 '0-8

#un%sten & . 5 '0-8

Material Sheet Res0 (

)

n, p "ell diffusion '000 to '00

n


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!ources of Resistance!ources of Resistance

? structure resistance - Ron

ource and drain resistance ontact via resistance

&irin% resistance

#op vie"

Brain n< ource n

&; =f"$ere f is freEuency

; )5 '0-/>=m

so t$e overallcross section is F 2&

; 2.7 mfor Al at ' 4>G

#$e onset of s3in effect is at fs- "$ere t$e s3in dept$ is eEual to $alf

t$e lar%est dimension of t$e "ire.fs; ) = ma5&,>2

An issue for $i%$ freEuency, "ide tall "ires i.e., cloc3sH


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!%in Effect for "ifferent W&s!%in Effect for "ifferent W&s

A (0I increase in resistance is observe for 20 m Al "ires at ' 4>Gversus only a 'I increase for ' m "ires

0.'

'

'0

'00

'000

*reEuency ->G

I!

ncrea

seinResistan

& ; ' um

& ; '0 um

& ; 20 um'8 '1 ''0

for > ; ./0 um


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"ealing $ith Resistance"ealing $ith Resistance

Selecti*e #echnology Scaling

3se 4etter Interconnect Materials

e.%. copper, silicidesMore Interconnect Layers

reduce avera%e "ire-len%t$


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Polycide 'ate MO!#ETPolycide 'ate MO!#ET

n+n+

SiO2

PolySilicon

Silicide

p

Silicides: WSi 2, TiSi 2, PtSi2and TaSi

Conductivity: 8-10 times better than Poly


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Modern InterconnectModern Interconnect


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E(ample: Intel )*+, micron ProcessE(ample: Intel )*+, micron Process

metal layers

#i=Al - u=#i=#iK

olysilicon dielectric


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InterconnectInterconnectModelingModeling


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The -umped ModelThe -umped Model

Vout

Driver

cwire

V in

C lum pe d

R driverV

out


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The -umped RC.ModelThe -umped RC.Model

The Elmore "elayThe Elmore "elayTo model propagation delaytime along a path from the

source sto destination i

considering the loading effect

of the other nodes on the pathfrom sto k

The shared path resistance i!

The "lmore delay

s


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The Ellmore "elayThe Ellmore "elay

RC ChainRC Chain


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Wire ModelWire Model

AssumeL &ire modeled by K eEual-len%t$ se%ments

*or lar%e values of KL


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The "istri/uted RC.lineThe "istri/uted RC.line


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!tep.response of RC $ire as a!tep.response of RC $ire as a

function of time and spacefunction of time and space

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.5

1

1.5

2

2.5

voltage(V)

x= L/10

x = L/4

x = L/2

x= L


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RC.ModelsRC.Models


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"riving an RC.line"riving an RC.line

V in

R s V o u t

(rw,cw,L)


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"esign Rules of Thum/"esign Rules of Thum/

rc delays s$ould only be considered "$en tpRMM tp%ateof t$e drivin% %ate

9critMM tp%ate=0.(8rc rc delays s$ould only be considered "$en t$e

rise fall time at t$e line input is smaller t$anR, t$e rise fall time of t$e line

triseN R ot$er"ise, t$e c$an%e in t$e input si%nal is slo"ert$an t$e propa%ation delay of t$e "ire

lecture7 wires (1)

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