lecture6

Digital System DesignDigital System Design

Lecture 7

ASM and ASMD chartsASM and ASMD charts

5/16/2010 1Engr.Anees Ullah

Why ASMs?Why ASMs?

• State‐transition graphs (STGs) indicate the State t a s t o g ap s (S Gs) d cate t etransitions that result from inputs that are applied when a state machine is in a particular

b d d l d l hstate, but STGs do not directly display the evolution of states under the application of input datadata.

• Complex digital systems are difficult to describe with Finite State Machines.with Finite State Machines.

• ASMs are similar to Flowcharts but they have a timing information.g


FSMs Vs ASMsFSMs Vs ASMs

• An ASM chart focuses on the activity of the ymachine, rather than on the contents of all the storage elements. Sometimes it is more convenient and even essential to describe theconvenient, and even essential, to describe the state of a machine by the activity that unfolds during its operation, rather than the data that are produced by the machine. For example, instead of describing a 16‐bit counter by its contents we can view it as acounter by its contents we can view it as a datapath unit and describe its activity (e.g., counting, waiting, etc.). g, g, )


Fundamental ASM elementsFundamental ASM elements


Vehicle Speed ControllerVehicle Speed Controller


Vehicle Speed ContollerVehicle Speed Contoller

• Outputs of Moore Machines are inside theOutputs of Moore Machines are inside the state box.

• Mealy output are shown by conditional boxes• Mealy output are shown by conditional boxes.

• The decision boxes along a path in ASM chart i l i i d diimply a priority decoding.


Algorithmic State Machines and Data h ( ) hpath (ASMD) charts

• The digital design RecipeThe digital design RecipeDigital design = Controller + Data path

• ASM chart when linked to the operations of a• ASM chart when linked to the operations of a data path.

• The chart is modified by annotating each of its• The chart is modified by annotating each of its paths to indicate the concurrent register operations that occur in the associated dataoperations that occur in the associated data path unit when the state of the controller makes a transition along the path.


ASMD chartsASMD charts

• Register operations that occur concurrentlyRegister operations that occur concurrently with state transitions are annotated on a path of the chart rather than in conditional boxesof the chart, rather than in conditional boxes on the path, or in state boxes, because these registers are not part of the controllerregisters are not part of the controller.


2‐ Stage Pipelined Register2 Stage Pipelined Register


ASMD chart of 2‐Stage Pipelined RegisterRegister


Up Down CounterUp Down Counter

• Suppose a 3‐bit counter has the features thatSuppose a 3 bit counter has the features that it can count up or down or hold the count.


Verilog Code for Up Down CounterVerilog Code for Up Down Counter

module Up_DownImplicit1 (count, up_dwn, clock, rese_); output [2: 0] count; input [1: 0] up_dwn; i t l k tinput clock, reset_; reg [2: 0] count; always @ (negedge clock or negedge reset ) y @ ( g g g g _)if (reset_ ==0) count <= 3'bO; else if (up_dwn == 2'bOO II up_dwn == 2'b11) count <= count; else if (up_dwn == 2'b01) count <= count + 1; else if (up_dwn == 2'b10) count <= count ‐1; end moduleend module


Ring CounterRing Counter


Verilog for Ring CounterVerilog for Ring Counter

module ring counter (count, enable, clock, reset); odu e g_cou te (cou t, e ab e, c oc , eset);output [7: 0] count; input enable, reset, clock;input enable, reset, clock; reg [7: 0] count; always @ (posedge reset or posedge clock)always @ (posedge reset or posedge clock)

if (reset == 1'b1) count <= 8'bOOOO_0001; elseelse

if (enable == 1'b1) count <= {count[6: 0], count[7]}; endmoduleendmodule


Modified 3 bit Up Down CounterModified 3 bit Up Down Counter


Modified 3 bit Up Down counterModified 3 bit Up Down counter


Shift RegisterShift Register


Verilog for Shift RegisterVerilog for Shift Register

module ShifUeg4 (Data_out, Data_in, clock, reset); output Data_out; input Data_in, clock, reset; reg [3: 0] Data reg;reg [3: 0] Data_reg; assign Data_out = Data_reg[O]; always @ (negedge reset or posedge clock) begin if (reset == 1'bO) Data_reg <= 4'bO; else Data reg <= {Data in, Data reg[3:1]};else Data_reg < {Data_in, Data_reg[3:1]}; end endmodule


Parallel load RegisterParallel load Register


Verilog for Parallel load RegisterVerilog for Parallel load Register

module PaUoad_reg4 (Data_out, Data_in, load, clock, reset); input [3: 0] Data_in; input load, clock, reset; output [3: 0] Data out; p [ ] _ ;reg Data_out; always @ (posedge reset or posedge clock) beginbegin if (reset == 1'b1) Data_out <= 4'bO; else if (load == 1'b1) Data_out <= Data_in; endend endmodule


Barrel ShifterBarrel Shifter


Verilog for Barrel ShifterVerilog for Barrel Shifter

module barrel_shifter (Data_out, Data_in, load, clock, reset); output [7: 0] Data_out; input [7: 0] Data_in; input load, clock, reset; reg [7: 0] Data_out; always @ (posedge reset or posedge clock) begin if (reset == 1'b1) Data_out <= 8'bO; else if (load == 1'b1) Data_out <= Data_in; else Data out <= {Data out[6: 0], Data out[7]}; _ { _ [ ], _ [ ]};end endmodule


Universal Shift RegisterUniversal Shift Register


Verilog for Universal Shift Registerd l i l Shif ( O S O S O i S imodule Universal_Shift Reg (Data_Out, MSB_Out, LSB_Out, Data_in, MSB_in, LSB_in, s1, so, clk, rst);

output [3: 0] Data_Out; output MSB_Out, LSB_Out; input [3: 0] Data_in; input MSB_in, LSB_ln; input 51, sO, clk, rst; reg Data Out;reg Data_Out; assign MSB_Out = Data_Out[3]; assign LSB_Out = Data_Out[O]; always @ (posedge clk) begin if (rst) Data_Out <= 0; else case ({s1, sO}) 0: Data_Out <= Data_Out; 1: Data Out <= {MSB in, Data Out[3:1]};1: Data_Out < {MSB_in, Data_Out[3:1]}; 2: Data_Out <= {Data_Out[2: 0], LSB_in}; 3: Data_Out <= Data_in; endcase

dend endmodule5/16/2010 26Engr.Anees Ullah

Register FileRegister File


Verilog for Register FileVerilog for Register Filemodule Register_File (Data_Out_1, Data_Out_2, Data_in, Read_Addr_1,

)Read_Addr_2, Write_Addr, Write_Enable, Clock); output [31: 0] Data _ Out_1, Data _ Out_2; input [31: 0] Data_in; input [4: 0] Read Addr 1 Read Addr 2 Write Addr;input [4: 0] Read_Addr_1, Read_Addr_2, Write_Addr; input Write_Enable, Clock; reg [31: 0] Reg_File [31: 0]; //32bit x32 word memory declaration assign Data Out 1 = Reg File[Read Addr 1];assign Data_Out_1 = Reg_File[Read_Addr_1]; assign Data_Out_2 = Reg_File[Read_Addr_2]; always @ (posedge Clock) begin if (Write Enable) Reg File [Write Addr] <= Data in; ( _ ) g_ [ _ ] _ ;end endmodule


Data path + FSMData path + FSM


4 bit Synchronous Binary Counter4 bit Synchronous Binary Counter


STGSTG


ASMASM


ASMDASMD


Verilog Code: Top Level ModuleVerilog Code: Top Level Module

module Binary Counter Part RTL (count, enable, y_ _ _ ( , ,clk, rst);

parameter size = 4; output [size ‐1: 0] count; input enable; i t lk tinput clk, rst; wire enable_DP; Control Unit MO (enable DP enable clk rst);Control_Unit MO (enable_DP, enable, clk, rst); Datapath_Unit M1 (count.,enable_DP, clk, rst); endmoduleendmodule


Control Unit ModuleControl Unit Module

module Control Unit (enable DP enable clkmodule Control_Unit (enable_DP, enable, clk, rst);

output enable DP;output enable _ DP;

input enable;

input clk, rst; // Not needed

wire enable DP = enable; // pass through_ ; // p g

endmodule


Data path Modulemodule Datapath_Unit (count, enable, clk, rst);

parameter size = 4;

output [size‐1: 0] count;output [size 1: 0] count;

input enable;

input clk, rst;

reg count;reg count;

wire [size‐1: 0] next_count;

always @ (posedge elk)

if (rst == 1) count <= 0;if (rst == 1) count <= 0;

else if (enable == 1) count <= next_count(count);

function [size‐1: 0] next_count;

input [size‐1: 0] count;input [size‐1: 0] count;

begin

next_count = count + 1;

endend

endfunction

endmodule5/16/2010 36Engr.Anees Ullah

Reading AssingmentReading Assingment

• 5 14 5 15 5 16 7 1 7 25.14, 5.15, 5.16, 7.1, 7.2


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conditional boxes onthepath

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