lecture10 sram2

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EE241 Spring 2008EE241 - Spring 2008Advanced Digital Integrated Circuits

Lecture 10: SRAM

AnnouncementsHomework 1

Due February 26Homework 2

Next week

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2

AgendaSRAM stability metrics

RetentionReadWriteDynamic

Options for scalingColumn assist techniques

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Migration away from 6TTechnology optionsDeparture from SRAM (eDRAM)

SRAMSRAM

Read/Write/Retention Margins

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ITRS Single Cell Reported Individual Cell Reported Cell in Arraym

2 )SRAM Scaling Trends

100

ITRS Effective Cell Reported Effective Cell

m2 )

700 600 500 400 300 200 10010090 80 70 60 50 40 30

0.1

1

10

SR

AM

Cel

l Siz

e (u

T h l N d ( )

300 200 100 90 80 70 60 50 40 30

0.1

1

10

SRAM

Cel

l Siz

e (u

T h l N d ( )

0.5x effective cell area scaling difficult

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Technology Node (nm)

Individual SRAM cell area able to track ITRS guidelineArray area deviates from ITRS guideline at 90nmMemory design no longer sits on the 0.5x area scaling trend!


Memory Scaling

ze (M

B) Server processors

It i ®

180 160 140 120 100 80 60

1

10

On-

Die

L3

Cac

he s

iz


Itanium® Processors

Xeon® Processors

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• Memory latency demands larger last level cache (LLC)• Memory is more energy-efficient than logic• LLC approaches 50% chip area for desktop and mobile processors• LLC approaches 80% chip area for server processors

Vivek De, Intel 2006

gy ( )

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6-T SRAM Cell

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• Improve CD control by unidirectional poly• Relax critical layer patterning requirements• Optimizing design rules is key

SRAM cell design trends0.46x1.24μmIEDM 02

VDD

BL BLB

Improve CD control by unidirectional polyImprove CD control by unidirectional poly

Cell in 90nm(1μm2)

Cell in 65nm(0.57μm2)

’GNDWL

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•• Improve CD control by unidirectional polyImprove CD control by unidirectional poly•• Relax critical layer patterning requirementsRelax critical layer patterning requirements•• Optimizing design rules is keyOptimizing design rules is key•• Shorter Shorter bitlinebitline enables better cycle time and/or array efficiencyenables better cycle time and/or array efficiency•• Full metal Full metal wordlinewordline with wider pitch achieves better RCwith wider pitch achieves better RC

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SRAM Cell Trends

0.242μm2 cell in 45nm from TSMC (IEDM’07)

90.346μm2 cell in 45nm from Intel (IEDM’07)

More SRAM Trends

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0.15μm2 cell in 32nm from TSMC (IEDM’07)

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Ion/Ioff: Cell Read and Leakage

11H. Pilo, IEDM 2006

SRAM Cell/ArrayHold stabilityRead stability

WL

VDDM4M2

Write stabilityRead current (access time)

BL

M5 M6

M1 M3

BL

QQ

Access Transistor

12Pull down Pull up

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WL Load

PRPL

VDD

SRAM Design – Hold (Retention) Stability

BL

AXL

NPD

Access‘1’ ‘0’

AXR

NRNL

BL

Data RetentionLeakage

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Scaling trend: Increased gate leakage + degraded ION/IOFF ratio

Lower VDD during standby

PMOS load devices must compensate for leakage

SRAM Cell Mismatch

1

14

WLCV

oxTh

1∝Δ Due to RDF

K. Zhang, Intel

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The Data-Retention Voltage (DRV) of SRAM

DRVVwhen11 ∂∂ VV

VDD

V1

M3

MM5

M1

V2VDD

0 0DRV Condition:

DRVVwhen , DDinverterRight 2

1

inverterLeft 2

1 =∂

=∂ VV

M4

M65

M2 Leakagecurrent

2

Leakagecurrent

VDDVDD

0.3

0.4

VDD=0.4V

VTC of SRAM cell inverters

When Vdd scales down to DRV, the voltage transfer curves (VTC) of the internal inverters degrade to such a

150 0.1 0.2 0.3 0.4

0

0.1

0.2

V1 (V)

2

VTC1VTC2

VDD=0.18V internal inverters degrade to such a level that retention static noise margin (SNM) of the SRAM cell reduces to zero.

Qin, ISQED’04

250

300

Monte-Carlo Simulation of DRV Distribution

100

150

200

stog

ram

of c

ell #

160 50 100 150 200 250 300

0

50

Simulated DRV of 1500 SRAM cells (mV)

Hi

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Read Stability – Static Noise Margin (SNM)

PR

VDD 1

Read SNM[1]AXR

NR

VL VR

0.5

VR (V

)

90nm simulation

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• Read SNM is typically the most stringent constraint

0 0.5 10

VL (V)

90nm simulation

[1] E. Seevinck, JSSC 1987

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SRAM Design – Read StabilityWL Load

PRPL

VDD

BL

AXL

NPD

Access

‘1’ V>0AXR

NRNL

BL

Retention fluctuations

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Read margin and retention margin

[Bhavnagarwala, IEDM’05]

Read Stability – N-Curve

• A, B, and C correspond to the two stable points A and C and the meta-stable point B of the SNM curvep

• When points A and B coincide, the cell is at the edge of stability and a destructive read can easily occur

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Write Stability – Write Noise Margin (WNM)

1 90nm simulationPR

VDD

0.5

VR (V

)

WNM[1]

AXR

NR

VL VR

22

0 0.5 10

VL (V)

• Write stability is becoming more stringent with scaling• Optimizing read and write stability at the same time is difficult

[1] A. Bhavnagarwala, IEDM 2005

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0.81

1.2

(V) 0.8

11.2

(V) WM

Write Stability – BL/WL Write Margins

-0.20

0.20.40.6

0.00E+00 2.00E-08 4.00E-08 6.00E-08 8.00E-08 1.00E-07

Time (s)

Volta

ge

WM

-0.20

0.20.40.6

0.00E+00 2.00E-08 4.00E-08 6.00E-08 8.00E-08 1.00E-07

Time (s)

Volta

ge (

Highest BL voltage under which write is possible when BLC is kept precharged (left)

BLWL

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precharged (left)

Difference between VDD and lowest WL voltage under which write is possible when both bit-lines are kept precharged (right)

Can be directly measured in large memory arrays via BL currents

Write Stability – Write Current (N-Curve)

24[1] C. Wann et al, IEEE VLSI-TSA 2005

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SRAM Design – Read/Write StabilityWL Load

PRPL

VDDCell Trip Voltage

Cell Stability

R d U t

BL

AXL

NPD

Access

‘1’ V>0AXR

NRNL

BL

Voltage

Cell Read Voltage

Read Upset Occurs

Technology ScalingH. Pilo, ISSCC’2005

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Read margin is typically the most stringent constraint

Cell read voltage must stay below cell trip voltageHarder to achieve with process induced variations

Noise margin degraded with technology scaling

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6-T SRAM Static/Dynamic Stability

Read MarginSNM: pessimistic

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Write MarginWNM: optimistic

[1] E. Seevinck, JSSC 1987; [2] A. Bhavnagarwala, IEDM 2005


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Next LectureSRAM design techniquesAlternatives to planar 6T SRAM

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