COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE

Lecture 1Course Introduction

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Course Information2

Course Title Computer Organization and Assembly Language

Credit Hours 4 Lab Yes

Course & Lab Instructor

Falak Nawaz Email fnn@aumc.edu.pk

Office Hours 0830 to 1630 Hrs Office Faculty Office at 5th Floor

Pre-requisite DLD

Books3

Textbook: Computer Organization & Design, Pa tte rs o n & He nne s s y 4th Ed . , Mo rg a n &

Kaufm a nn, 2 0 0 9 . MIPS Assembly Language Programming, Ro be rt L. Britto n Co m pute r Sc ie nc e

De p a rtm e nt Ca lifo rnia Sta te Unive rs ity, Chic o , Ca lifo rnia

Reference Books: MIPS32™ Architecture For Programmers Volume II: The MIPS3 2™

Ins truc tio n Se t Re vis io n 2 . 0 MIPS Assembly Language Programming, Dis cus s io n a nd Pro je c t Bo o k,

Da nie l J. Ella rd

 

Grading Policy4

Grades will be awarded on the basis of continuous assessment through quizzes, assignments, one midterm exams and a final exam. The tentative distribution of marks is as under:  Quizzes 4 5% Assignments 4 5% Project 1 10% Lab multiple 10% Midterm 25% Final exam 45%

Weekly Breakdown5

Week 1: Introduction to computer architecture, computer organization, layered approach in computer design, levels of program code, components of ISA

 Week 2: Stored program concepts, Number system, Introduction to assembly language basics, Instruction types 

Week 3: MIPS architecture, Program structure, Data declaration, arithmetic instructions

Week 4: MIPS architecture, Mode of addressing, Assembly language concepts, Load instructions, Shift instructions

Week 5: Control instructions, Loops and if-else, Register usage, program stack

Week 6: Creating executables, assembler, linker, loader, Instruction set  Week 7: Negative binary number, signed versus unsigned operations Week 8: Floating point number, IEEE 754 floating point standard Midterm Exam

Weekly Breakdown6

Week 10: Memory reference instructions, arithmetic and logical instructions, control-transfer instructions,

Week 11: Control unit, control signal table, ALU control Week 12: Instruction cycle, Interrupts, Types of Interrupts, Interrupt cycle,

Multiple interrupts Week 13: Multi-cycle execution, data path, multi-cycle control, execution

steps  Week 14: Memory hierarchy, Registers, Internal memory, external memory Week 15: Cache memory, main memory, Cache memory and main memory,

locality of references Week 16: Cache design and addressing, cache-memory mapping Week 17: Course Review and Project demonstration Final Exam

In this course, Briefly …7

We will study Computer architecture

MIPS architecture Concepts of assembler, linker, compiler Computer arithmetic

Signed and unsigned binary numbers Floating point format Operations (add/div/…)

Basic processor performance analysis Processor organization

Datapath Control

Computer organization We will do

Assembly language programming (in MIPS)

Rules and Regulations8

Plagiarism – Zero tolerance Cheating – Zero tolerance Attendance – At-least 75% attendance Disruption – Will be kicked out of the class  Punctuality and Regularity - in all theory and lab

sessions are required. No makeup quizzes shall be taken  Deadlines – Fixed and will not change. At least 10%

marks shall be deducted for late submission within 24 hours of the deadline. Late submissions with more than 24 hours will not be accepted and will be graded zero.

COMPUTER ORGANIZATIONIntroduction

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Computer Systems10

“Desktop computers” E.g. PCs, MACs, … Includes Notebooks

“Servers” Web servers File and compute servers Supercomputers

“Embedded computers” Usually NOT directly observable Very wide range of applications

Desktop Computers11

Servers12

Embedded Computers13

Computer Organization14

We study this part in this course!

Computer Architecture?15

Computer systems Underlying hardware Software running on it

Computer architecture The hardware/software interface seen by the user Instruction set architecture (ISA)

Processor microarchitecture Implementation of a given architecture May or may not be visible to the user

Layered Approach in Computer Design16

Computer Architecture orInstruction Set Architecture

Microarchitecture

Architecture

Machine Code Example17

swap:muli $t0, $a0, 4add $t0, $a1, $t0lw $t1, 0($t0)lw $t2, 4($t0)sw $t2, 0($t0)sw $t1, 4($t0)jr $ra

void swap(int v[], int k){

int temp;temp = v[k];v[k] = v[k+1];v[k+1] = temp;

}

00000000101000010…00000000000110000…10001100011000100…10001100111100100…10101100111100100…10101100011000100…00000011111000000…

compil

er

assembler

Levels of Program Code High-level language

Level of abstraction closer to problem domain

Provides for productivity and portability

Assembly language Textual representation of

instructions Hardware representation

Binary digits (bits) Encoded instructions and

data

Components of ISA19

In most cases, a “programmer’s reference manual” (PRM) will disclose the ISA of a processor

To understand an ISA, find in PRM Data types the processor supports Supported instructions and their definitions Registers (general-purpose & special purpose) Processor modes Exception mechanism

ISA20

The instruction set Consists of format of the instruction and the

semantics of the instruction. The semantics include the kinds of way to access and maneuver data (called a ddre s s ing m o d e s ).

The register set Instructions work on registers and memory.

Register set defines which registers the instruction may access (MIPS uses register names such as $r0, $r1, ..., $r31).

Inside a PC21

Integrated Circuits (ICs) CPU (Central Processing Unit), companion chipset, memory,

peripheral I/O chip (e.g., USB, IDE, IEEE1394, …) Printed Circuit (PC) boards (next slide)

Substrate for ICs and interconnection Distribution of clock, power supply Heat dissipation

Hard disk, CD-RW DVD-RW, (floppy disk) Power supply Chassis

Holds boards, power supply, and provides physical interface for user and other systems

Connectors and cables

Technology Trend (Processor Complexity)22

2x transistors/chip every 1.5 years!Moore’s Law

Main memory23

PC/servers use “DRAM” (Dynamic RAM) SDRAM (Synchronous Dynamic RAM) DDR SDRAM RDRAM (RAMBUS DRAM)

A typical SDRAM “module”

Storage24

Secondary storage Non-volatile Stores programs, user-saved data, etc. In PC/server domain, magnetic disk (hard-

disk) is usually used In embedded computers, “flash” memory or

“ROM” is usually employed

Storage, cont’d25

5.25-inch floppy disk1.2MB

3.5-inch floppy disk1.44MB

USB Flash card256MB

Storage, cont’d26

System Bus27

There's usually a bus that connects the CPU to memory and to disk and I/O devices.

A bus could have wires B31-0 to indicate there are 32 wires. 

Types of Buses Data Bus Address Bus Control Bus

Data, Address, and Control Bus28

Data Bus 32-bit data bus used to write or read 32 bits of

data to or from memory Address Bus

32-bit bus for the CPU to specify which address to read or write from or to memory.

Control Bus Allow CPU and memory to communicate (for

example, to indicate when and whether a read or write is to be performed).

Register29

A CPU contains very fast memory called re g is te rs . For example, a MIPS ISA stores 32 32-bit registers.

A register is made up of what?