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Lecture 060 – Capacitors (3/24/10) Page 060-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 060 - CAPACITORSLECTURE ORGANIZATION
Outline• Introduction• pn junction capacitors• MOSFET gate capacitors• Conductor-insulator-conductor capacitors• Deviation from ideal behavior in capacitors• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 43-47, 58-59 and 63-64
Lecture 060 – Capacitors (3/24/10) Page 060-2
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTIONTypes of Capacitors for CMOS Technology1.) PN junction (depletion)
capacitors
2.) MOSFET gate capacitors
3.) Conductor-insulator-conductor capacitors
060204-01 + −vD
xd
W2W1
+− +− +−+− +− +−
d
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p-well
p+
G D,S,B
n+n+
Cox
Cjunction
Top ConductorBottomConductorDielectric
Insulating layer
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Lecture 060 – Capacitors (3/24/10) Page 060-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Characterization of CapacitorsWhat characterizes a capacitor?1.) Dissipation (quality factor) of a capacitor is
Q = CRp = C
Rs
where Rp is the equivalent resistance in parallel with the capacitor, C, and Rs is the electrical series resistance (ESR) of the capacitor, C.
2.) Parasitic capacitors to ground from each node of the capacitor.3.) The density of the capacitor in Farads/area.4.) The absolute and relative accuracies of the capacitor.5.) The Cmax/Cmin ratio which is the largest value of capacitance to the smallest when
the capacitor is used as a variable capacitor (varactor).6.) The variation of a variable capacitance with the control voltage.7.) Linearity, q = Cv.
Lecture 060 – Capacitors (3/24/10) Page 060-4
CMOS Analog Circuit Design © P.E. Allen - 2010
PN JUNCTION CAPACITORSPN Junction Capacitors in a WellGenerally made by diffusion into the well.
Anode
n-well
p+
Substrate
Fig. 2.5-011
n+n+
������p+
DepletionRegion
Cathode
p- substrate
CjCj
RwjRwj Rw
Cw
Rs
Anode Cathode
VA VBC
Rwj
rD
Layout:
Minimize the distance between the p+ and n+ diffusions.Two different versions have been tested.
1.) Large islands – 9μm on a side2.) Small islands – 1.2μm on a side n-well
n+ diffusion
p+ dif-fusion
Fig. 2.5-1A
Lecture 060 – Capacitors (3/24/10) Page 060-5
CMOS Analog Circuit Design © P.E. Allen - 2010
PN-Junction Capacitors – ContinuedThe anode should be the floating node and the cathode must be connected to ac ground.Experimental data (Q at 2GHz, 0.5μm CMOS)†:
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00.5
1
1.52
2.5
3
3.54
0 0.5 1 1.5 2 2.5 3 3.5
CA
node
(pF
)
Cathode Voltage (V)
Large Islands
Small Islands
Cmax Cmin
0
20
40
60
80
100
120
0 0.5 1 1.5 2 2.5 3 3.5
QA
node
Qmin Qmax
Large Islands
Small Islands
Cathode Voltage (V)
R-XBridge
Anode Cathode
CathodeVoltage
C
R-XBridge
Anode Cathode
CathodeVoltage
C
Small Islands (598 1.2μm x1.2μm) Large Islands (42 9μm x 9μm)TerminalUnder Test Cmax/Cmin Qmin Qmax Cmax/Cmin Qmin Qmax
Anode 1.23 94.5 109 1.32 19 22.6Cathode 1.21 8.4 9.2 1.29 8.6 9.5
† E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
Electrons as majority carriers lead to higher Q because of their higher mobility.The resistance, Rwj, is reduced in small islands compared with large islands higher Q
Lecture 060 – Capacitors (3/24/10) Page 060-6
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSFET GATE CAPACITORSMOSFET Gate Capacitor StructureThe MOSFET gate capacitors have the gate as one terminal of the capacitor and somecombination of the source, drain, and bulk as the other terminal.In the model of the MOSFET gate capacitor shown below, the gate capacitance is reallytwo capacitors in series depending on the condition of the channel.
Cgate = 1
1Cox
+1Cj
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p-well
p+
G D
n+n+
Cox
Cjunction
G
S D
B
Cox
Cjunction
Channel Resistance
Bulk Resistance
S B
Lecture 060 – Capacitors (3/24/10) Page 060-7
CMOS Analog Circuit Design © P.E. Allen - 2010
060207-03
p-well
p+
G D,S,B
n+n+
Cox
Cjunction
VG-VD,S,B
Capacitance
StrongInversion
Accumulation
ModerateInversion
WeakInv.
Depletion
CoxCox
MOSFET Gate Capacitor as a function of VGS with D=S=B
Operation:In this configuration, the MOSFET gate capacitor has 5 regions of operation as VGS isvaried. They are:
1.) Accumulation2.) Depletion3.) Weak inversion4.) Moderate inversion5.) Strong inversion
For the first four regions, the gate capacitance is the series combination of Cox and Cjgiven as,
Cgate = 1
1Cox
+1Cj
Lecture 060 – Capacitors (3/24/10) Page 060-8
CMOS Analog Circuit Design © P.E. Allen - 2010
Use of a 3 Segment Model to Explain the Gate Capacitor Variation
Region Channel R Cox and Cj Cgate 3-Segment Model
Accumulation Large In series andCj > Cox
Cgate Cox
Depletion Large In series andCj Cox
Cgate 0.5Cox 0.5Cj
WeakInversion
Large In series andCj < Cox
Cgate Cj
ModerateInversion
Moderate In series andCj < Cox
Cj < Cgate < Cox
StrongInversion
Small In parallel andCj < Cox
Cgate Cox
Lecture 060 – Capacitors (3/24/10) Page 060-9
CMOS Analog Circuit Design © P.E. Allen - 2010
MOSFET Gate Capacitor as a function of VGS with Bulk Fixed (Inversion Mode)
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p-well
p+
G D,S
n+n+
Cox
Cjunction
VG-VD,S
CoxCox
B Capacitance
0
VT shift if VBS ≠ 0
B=D= S
InversionMode MOS
Conditions:• D = S, B = VSS
• Accumulation region removed by connecting bulk to VDD
• Nonlinear• Channel resistance:
Ron = L
12KP'(VBG-|VT|)
• LDD transistors will give lower Q because of the increased series resistance
Lecture 060 – Capacitors (3/24/10) Page 060-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Inversion Mode NMOS CapacitorBest results are obtainedwhen the drain-source areconnected to ac ground.
Experimental Results (Q at2GHz, 0.5μm CMOS)†:
1.5
2
2.5
3
3.5
4
4.5
0 0.5 1 1.5 2 2.5 3 3.5
CG
ate
(pF)
VG = 2.1V
VG = 1.8V
VG = 1.5V
Cmax Cmin
Drain/Source Voltage (V)
2224
26
2830
32
34
3638
0 0.5 1 1.5 2 2.5 3 3.5
VG = 1.8V
VG = 1.5V
Qmax Qmin
Drain/Source Voltage (V) 070617-06
QG
ate
VG = 2.1VRX
MeterVG VD,S
RXMeter
VG VD,S
VG =1.8V: Cmax/Cmin ratio = 2.15 (1.91), Qmax = 34.3 (5.4), and Qmin = 25.8(4.9)
† E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
���������Cox
p+
Bulk
G D,S
G
D,S
p- substrate/bulk����������������n+n+
n- LDD
Rd RdCd CdCsi
CjRsj
Rsi
Cov Cov B
Fig. 2.5-2
Shown in inversion mode
Lecture 060 – Capacitors (3/24/10) Page 060-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Accumulation Mode NMOS Gate CapacitorG B
n+n+
Cox
060207-05
VG-VD,S,B
Capacitance
Depletion
Cox
Inversion Accumulation
Conditions:• Remove p+ drain and source and put n+ bulk contacts instead.• Implements a variable capacitor with a larger transition region between the maximum
and minimum values.• Reasonably linear capacitor for values of VGB > 0
Lecture 060 – Capacitors (3/24/10) Page 060-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Accumulation Mode Capacitor – ContinuedBest results areobtained when thedrain-source are onac ground.
ExperimentalResults (Q at 2GHz, 0.5μm CMOS)†:
2
2.4
2.8
3.2
3.6
4
0 0.5 1 1.5 2 2.5 3 3.5
CG
ate
(pF)
VG = 0.9V
VG = 0.6V
VG = 0.3V
Cmax Cmin
Drain/Source Voltage (V)
25
30
35
40
45
0 0.5 1 1.5 2 2.5 3 3.5
Qmax Qmin
Drain/Source Voltage (V)
QG
ate
VG = 0.9V
VG = 0.6V
070617-07
VG = 0.3VRXMeter
VG VD,S
RXMeter
VG VD,S
† E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
����
������
Cox
p+Bulk
G D,S
G
D,S
p- substrate/bulk
n+n+
n- LDD
Rd RdCd Cd
Cw
Rs
Cov Cov B
Fig. 2.5-5
n- well
Rw
Shown in depletion mode.
VG = 0.6V: Cmax/Cmin ratio = 1.69 (1.61), Qmax = 38.3 (15.0), and Qmin = 33.2(13.6)
Lecture 060 – Capacitors (3/24/10) Page 060-13
CMOS Analog Circuit Design © P.E. Allen - 2010
CONDUCTOR-INSULATOR-CONDUCTOR CAPACITORSPolysilicon-Oxide-Polysilicon (Poly-Poly) CapacitorsLOCOS Technology:A very linear capacitorwith minimum bottomplate parasitic.
DSM Technology:A very linear capacitor withsmall bottom plate parasitic.
Lecture 060 – Capacitors (3/24/10) Page 060-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Metal-Insulator-Metal (MiM) CapacitorsIn some processes, there is a thin dielectric between a metal layer and a special metallayer called “capacitor top metal”. Typically the capacitance is around 1fF/μm2 and isat the level below top metal.
060530-01
Third levelfrom top metal
Second level from top metalInter-
mediateOxideLayers
Top Metal
Protective Insulator Layer
Metal Via
Capacitor Top Metal
Capacitor bottom plate
Capacitordielectric
Fourth levelfrom top metal
Vias connecting bottom plate to lower metal
Vias connecting top plate to top metal
Vias connecting bottom plate to lower metal
Good matching is possible with low parasitics.
Lecture 060 – Capacitors (3/24/10) Page 060-15
CMOS Analog Circuit Design © P.E. Allen - 2010
Metal-Insulator-Metal Capacitors – Lateral and Vertical FluxCapacitance between conductors on the same level and use lateral flux.
These capacitors are sometimes called fractal capacitors because the fractal patterns arestructures that enclose a finite area with a near-infinite perimeter.The capacitor/area can be increased by a factor of 10 over vertical flux capacitors.
+ - + -
+ - +-
Fringing field
Metal
Fig2.5-9
+ - + -Metal 3
Metal 2
Metal 1
Metal
Top view:
Side view:
Lecture 060 – Capacitors (3/24/10) Page 060-16
CMOS Analog Circuit Design © P.E. Allen - 2010
More Detail on Horizontal Metal Capacitors†
Some of the possible metal capacitor structures include:1.) Horizontal parallel plate (HPP).
2.) Parallel wires (PW):
† R. Aparicio and A. Hajimiri, “Capacity Limits and Matching Properties of Integrated Capacitors, IEEE J. of Solid-State Circuits, vol. 37, no. 3, March
2002, pp. 384-393.
030909-01
030909-02 Top ViewLateral View
Lecture 060 – Capacitors (3/24/10) Page 060-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Horizontal Metal Capacitors - Continued3.) Vertical parallel plates (VPP):
Vias
030909-03
4.) Vertical bars (VB):
Vias
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Top ViewLateral View
Lecture 060 – Capacitors (3/24/10) Page 060-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Horizontal Metal Capacitors - ContinuedExperimental results for a CMOS process with 3 layers of metal, Lmin =0.5μm, tox =0.95μm and tmetal = 0.63μm for the bottom 2 layers of metal.
Structure Cap. Density(aF/μm2)
Caver.(pF)
Std. Dev.(fF) Caver.
fres.
(GHz)Q @
1 GHzRs ( ) Break-
down (V)
VPP 158.3 18.99 103 0.0054 3.65 14.5 0.57 355PW 101.5 33.5 315 0.0094 1.1 8.6 0.55 380HPP 35.8 6.94 427 0.0615 6.0 21 1.1 690
Experimental results for a digital CMOS process with 7 layers of metal, Lmin =0.24μm,tox = 0.7μm and tmetal = 0.53μm for the bottom 5 layers of metal. All capacitors = 1pF.
Structure(1 pF)
Cap. Density(aF/μm2)
Caver.(pF)
Area(μm2)
Cap.Enhancement
Std.Dev.(fF)
Caver.
fres.(GHz)
Q @1 GHz
Break-down
(V)VPP 1512.2 1.01 670 7.4 5.06 0.0050 > 40 83.2 128VB 1281.3 1.07 839.7 6.3 14.19 0.0132 37.1 48.7 124
HPP 203.6 1.09 5378 1.0 26.11 0.0239 21 63.8 500MIM 1100 1.05 960.9 5.4 - - 11 95 -
Lecture 060 – Capacitors (3/24/10) Page 060-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Horizontal Metal Capacitors - ContinuedHistogram of the capacitance distribution forthe above case (1 pF):
Experimental results for a digital CMOSprocess with 7 layers of metal, Lmin =0.24μm, tox = 0.7μm and tmetal = 0.53μm forthe bottom 5 layers of metal (all capacitors =10pF):
Structure(10 pF)
Cap. Density(aF/μm2)
Caver.(pF)
Area(μm2)
Cap.Enhancement
Std.Dev.(fF)
Caver.
fres.(GHz)
Q @1 GHz
Break-down
(V)
VPP 1480.0 11.46 7749 8.0 73.43 0.0064 11.3 26.6 125VB 1223.2 10.60 8666 6.6 73.21 0.0069 11.1 17.8 121
HPP 183.6 10.21 55615 1.0 182.1 0.0178 6.17 23.5 495MIM 1100 10.13 9216 6.0 - - 4.05 25.6 -
0
2
4
6
8
10
12
94 96 98 100 102 104 106
HPPVPPPW
Num
ber
of d
ice
σcCaver
030909-05
Lecture 060 – Capacitors (3/24/10) Page 060-20
CMOS Analog Circuit Design © P.E. Allen - 2010
DEVIATION FROM IDEAL BEHAVIOR IN CAPACITORSCapacitor Errors1.) Dielectric gradients2.) Edge effects3.) Process biases4.) Parasitics5.) Voltage dependence6.) Temperature dependence
Lecture 060 – Capacitors (3/24/10) Page 060-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Capacitor Errors - Oxide GradientsError due to a variation in dielectric thickness across the wafer.Common centroid layout - only good for one-dimensional errors:
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2C C 2C CNo common centroid layout Common centroid layout
An alternate approach is to layout numerous repetitions and connect them randomly toachieve a statistical error balanced over the entire area of interest.Improved matching of three components, A, B, and C:
A B C A B C A B C
A BC A B C A B C
AB C A B C A B C
A
B
C 070625-01
Lecture 060 – Capacitors (3/24/10) Page 060-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Capacitor Errors - Edge EffectsThere will always be a randomness on the definition of the edge.However, etching can be influenced by the presence of adjacent structures.For example,
AC
A BC
B
Matching of A and B are disturbed by the presence of C.
Improved matching achieve by matching the surroundings of A and B.
Lecture 060 – Capacitors (3/24/10) Page 060-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Process Bias on CapacitorsConsider the following two capacitors:
If L1 = L2 = 2μm, W2 = 2W1 = 4μm andx = 0.1μm, the ratio of C2 to C1 can
be written as,C2C1
= (2-.2)(4-.2)(2-.2)(2-.2) =
3.81.8 = 2.11 5.6% error in matching
How can this matching error be reduced?The capacitor ratios in general can be expressed as,
C2C1
= (L2-2 x)(W2-2 x)(L1-2 x)(W1-2 x) =
W 2W 1
1 -2 xW 2
1 -2 xW 1
W 2W 1
1 -2 xW 2
1 +2 xW 1
W 2W 1
1 -2 xW 2
+2 xW 1
Therefore, if W2 = W1, the matching error should be minimized. The best matchingresults between two components are achieved when their geometries are identical.
L1
W1
C1 L2 C2
W2041022-03
ΔxΔx
ΔxΔx
Lecture 060 – Capacitors (3/24/10) Page 060-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Replication PrincipleBased on the previous result, a way to minimize the matching error between two or moregeometries is to insure that the matched components have the same area to peripheryratio. Therefore, the replication principle requires that all geometries have the same area-periphery ratio.Correct way to match the previous capacitors (the two C2 capacitors are connectedtogether):
If L1 = L2 = 2μm, W2 = 2W1 = 2μm and x = 0.1μm, the ratio of C2 to C1 can be writtenas,
C2C1
= 2(2-.2)(2-.2)(2-.2)(2-.2) =
2·1.81.8 = 2 0% error in matching
The replication principle works for any geometry and includes transistors, resistors aswell as capacitors.
L1
W1
C1
041022-04
Δx
ΔxL2
W2
C2
Δx
ΔxL2
W2
C2
Δx
Δx
Lecture 060 – Capacitors (3/24/10) Page 060-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Capacitor Errors - Relative AccuracyCapacitor relative accuracy is proportional to the area of the capacitors and inverselyproportional to the difference in values between the two capacitors.For example,
0.04
0.03
0.02
0.01
0.001 2 4 8 16 32 64
Unit Capacitance = 0.5pF
Unit Capacitance = 1pF
Unit Capacitance = 4pF
Rel
ativ
e A
ccur
acy
Ratio of Capacitors
Lecture 060 – Capacitors (3/24/10) Page 060-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Capacitor Errors - ParasiticsParasitics are normally from the top and bottom plate to ac ground which is typically thesubstrate.
060702-08
Top Plate
Bottom Plate
DesiredCapacitor
Bottomplate
parasitic
Topplate
parasitic
Top plate parasitic is 0.01 to 0.001 of Cdesired
Bottom plate parasitic is 0.05 to 0.2 Cdesired
Lecture 060 – Capacitors (3/24/10) Page 060-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Layout Considerations on Capacitor AccuracyDecreasing Sensitivity to Edge Variation:
060207-09
FringingField
FringingField
Sensitive to alignment errors in the upper and lower plates and loss ofcapacitance flux (smaller capacitance).
? ?Insensitive to alignment errors and the flux reaching the bottom plate is largerresulting in large capacitance.
A structure that minimizes the ratio of perimeter to area (circle is best).
060207-10
Bottom Plate
TopPlate
Reduced bottom plate parasitic.
Lecture 060 – Capacitors (3/24/10) Page 060-28
CMOS Analog Circuit Design © P.E. Allen - 2010
Accurate Matching of Capacitors†
Accurate matching of capacitors depends on the following influence:1.) Mismatched perimeter ratios2.) Proximity effects in unit capacitor photolithography3.) Mismatched long-range fringe capacitance4.) Mismatched interconnect capacitance5.) Parasitic interconnect capacitanceLong-range fringe capacitance:
061216-04
Shield to collect long-range fringe fields? ? ? ?
Obviously there will be a tradeoff between matching and speed.
† M.J. McNutt, S. LeMarquis and J.L.Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE J. of Solid-StateCircuit, vo. 29, No. 5, May 1994, pp. 611-616.
Lecture 060 – Capacitors (3/24/10) Page 060-29
CMOS Analog Circuit Design © P.E. Allen - 2010
ShieldingThe key to shielding is to determine and control the electric fields.Consider the following noisy conductor and its influence on the substrate:
060118-10
Substrate
Noisy Conductor
SubstrateShield
SeparateGround
Noisy Conductor
Increased Parasitic Capacitance
Use of bootstrapping to reduce capacitor bottom plate parasitic:
060316-02
Substrate
Top Plate
Bottom Plate
ShieldSubstrate
Cpar
2Cpar
2Cpar
+1
Lecture 060 – Capacitors (3/24/10) Page 060-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Definition of Temperature and Voltage CoefficientsIn general a variable y which is a function of x, y = f(x), can be expressed as a Taylorseries,
y(x) y(x0) + a1(x- x0) + a2(x- x0)2+ a3(x- x0)3 + ···where the coefficients, ai, are defined as,
a1 = df(x)dx
|x=x0 , a2 =
12
d2f(x)dx2
|x=x0 , ….
The coefficients, ai, are called the first-order, second-order, …. temperature or voltagecoefficients depending on whether x is temperature or voltage.Generally, only the first-order coefficients are of interest.
In the characterization of temperature dependence, it is common practice to use a termcalled fractional temperature coefficient, TCF, which is defined as,
TCF(T=T0) = 1
f(T=T0) df(T)dT
|T=T0 parts per million/°C (ppm/°C)
or more simply,
TCF = 1
f(T) df(T)dT parts per million/°C (ppm/°C)
A similar definition holds for fractional voltage coefficient.
Lecture 060 – Capacitors (3/24/10) Page 060-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Capacitor Errors - Temperature and Voltage DependenceMOSFET Gate Capacitors:
Absolute accuracy ±10%Relative accuracy ±0.2%Temperature coefficient +25 ppm/C°Voltage coefficient -50ppm/V
Polysilicon-Oxide-Polysilicon Capacitors:Absolute accuracy ±10%Relative accuracy ±0.2%Temperature coefficient +25 ppm/C°Voltage coefficient -20ppm/V
Metal-Dielectric-Metal Capacitors:Absolute accuracy ±10%Relative accuracy ±0.6%Temperature coefficient +40 ppm/C°
Voltage coefficient -20ppm/V, 5ppm/V2
Accuracies depend upon the size of the capacitors.
Lecture 060 – Capacitors (3/24/10) Page 060-32
CMOS Analog Circuit Design © P.E. Allen - 2010
Future Technology Impact on CapacitorsWhat will be the impact of scaling down in CMOS technology?• The capacitance can be divided into gate capacitance and overlap capacitance.
Gate capacitance varies with external voltage changesOverlap capacitances are constant with respect to external voltage changes
As the channel length decreases, the gate capacitance becomes less of the totalcapacitance and consequently the Cmax/Cmin will decrease. However, the Q of thecapacitor will increase because the physical dimensions are getting smaller.
• For UDSM, the gate leakage current will eliminate gate capacitors from being useful.Best capacitor for future scaled CMOS?
Polysilicon-polysilicon or metal-metal (too much leakage current in gatecapacitors)Best varactor for future scaled CMOS?
The standard mode CMOS depletion capacitor because Cmax/Cmin is larger thanthat for the accumulation mode and Q should be sufficient. The pn junction will bemore useful for UDSM.
Lecture 060 – Capacitors (3/24/10) Page 060-33
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Capacitors are made from:
- pn junctions (depletion capacitors)- MOSFET gate capacitors- Conductor-insulator-conductor capacitors
• Capacitors are characterized by:- Q, a measure of the loss- Density- Parasitics- Absolute and relative accuracies
• Deviations from ideal capacitor behavior include;- Dielectric gradients- Edge effects (etching)- Process biases- Parasitics- Voltage and temperature dependence