lecture 8 shelving in superscalar processors (part 1) advanced computer architecture

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Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

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Page 1: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

Lecture 8Shelving in Superscalar

Processors (Part 1)

Advanced Computer Architecture

Page 2: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

Direct Issue

Page 3: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

The principle of shelving: Indirect Issue

Page 4: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

Design Space of Shelving

Page 5: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

Scope of Shelving

Page 6: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

Layout of Shelving Buffers

Page 7: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

Implementation of Shelving Buffer

Page 8: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

Basic Variants of Shelving Buffers

Page 9: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

Using a Combined Buffer for

Shelving, Renaming, and Reordering

Page 10: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

Number of Shelving Buffer Entries

Page 11: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

Number of read and write ports

how many instructions may be written into (input ports) or

read out from (output parts) a particular shelving buffer in a cycle

depend on individual, group, or central reservation stations

Page 12: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

Shelving: Operand Fetch Policy

Page 13: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

Operand Fetch Policies

Page 14: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

Operand fetch during instruction issue

Reg. file

Page 15: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

Operand fetch during instruction dispatch

Reg. file