lecture 3

Waqar Ahmad

Department of Electrical Engineering

VLSI DesignLecture 3

(CMOS Fabrication and Layout)

Wafer Preparation

VLSI Design2

Photolithography

• Used to print desired patterns on wafer• The feature size directly depends on the wavelength of your

lithographic system

UV light

Reticle field size20 mm × 15mm,4 die per field

5:1 reduction lens

Wafer

Image exposure on wafer 1/5 of reticle field4 mm × 3 mm,4 die per exposure

Serpentine stepping

pattern

VLSI Design3

oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single photolithographic cycle (from [Fullman]).

Photo-Lithographic Process

VLSI Design4

Fabricating one transistor

VLSI Design5

Oxidation(Field oxide)

Silicon substrate

Silicon dioxideSilicon dioxide

oxygen

PhotoresistDevelop

oxideoxide

PhotoresistCoating

photoresistphotoresist

Mask-WaferAlignment and Exposure

Mask

UV light

Exposed Photoresist

exposedphotoresist

exposedphotoresist

GS D

Active Regions

top nitride

S DG

silicon nitridesilicon nitride

NitrideDeposition

Contact holes

S DGG

ContactEtch

Ion Implantation

ox D

G

Scanning ion beam

S

Metal Deposition and

Etch

drainS DGG

Metal contacts

PolysiliconDeposition

polysiliconpolysilicon

Silane gas

Dopant gas

Oxidation(Gate oxide)

gate oxidegate oxide

oxygen

PhotoresistRemove

oxideoxide

Ionized oxygen gas

OxideEtch

photoresistphotoresistoxideoxide

Ionized CF4 gas

PolysiliconMask and Etch

oxideoxide

Ionized CCl4 gas

CMOS Fabrication

VLSI Design6

CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section

of wafer in a simplified manufacturing process

CMOS Top View

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+

SiO2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+

7

Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors

n+

p substrate

p+

n well

A

YGND VDD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor

VLSI Design8

Well and Substrate Taps Substrate must be tied to GND and n-well to VDD

Metal to lightly-doped semiconductor forms poor connection called Shottky Diode

Use heavily doped well and substrate contacts / taps

VLSI Design9

Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line

GND VDD

Y

A

substrate tap well tapnMOS transistor pMOS transistor

VLSI Design10

Detailed Mask Views Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal

VLSI Design11

CMOS Process at a Glance

Define active areasEtch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers

VLSI Design12

Patterning of SiO2

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

PhotoresistSiO2

UV-light

Patternedoptical mask

Exposed resist

SiO2

Si-substrate

Si-substrate

Si-substrate

SiO 2

SiO 2

(d) After development and etching of resist,chemical or plasma etch of SiO 2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasmaetch

VLSI Design13

Photolithography Step 1 – n-well Formation Step 2 – Active Region Formation Step 3 – Polysilicon Gate Step 4 – p-type and n-type diffusion Step 5 – Metal Contact Formation

VLSI Design14

1.1 – Oxidation & PhotoresistForm N-Well regions

Grow oxide Deposit photoresist

Two types Positive Tone

The area exposed to light dissolves (softens)

Negative Tone The area exposed to

light remains (hardens)

Layout view

Cross section view

p-type substrate

NWELL mask

NWELL mask

oxide photoresist

VLSI Design15

1.2 LithographyForm N-Well regions

Grow oxide

Deposit photoresist

Pattern photoresist NWELL Mask expose only n-well areas

Layout view

Cross section view

p-type substrate

NWELL mask

NWELL mask

oxide photoresist

VLSI Design16

1.3 EtchForm N-Well regions

Grow oxide Deposit photoresist Pattern photoresist

NWELL Mask expose only n-well areas

Etch oxide Etch oxide with hydrofluoric

acid (HF) Only attacks oxide where

resist has been exposed

Remove photoresist Use mixture of acids called

piranah etch Necessary so resist doesn’t

melt in next step Layout view

Cross section view

p-type substrate

oxide

VLSI Design17

1.4 Well FormationForm N-Well regions

Grow oxide Deposit photoresist Pattern photoresist

NWELL Mask expose only n-well areas

Etch oxide Remove photoresist

Diffuse n-type dopants through oxide mask layer Diffusion

Place wafer in furnace with arsenic gas

Heat until As atoms diffuse into exposed Si

Ion Implanatation Blast wafer with beam of As

ions Ions blocked by SiO2, only

enter exposed Si

Layout view

Cross section view

p-type substrate

n-well

VLSI Design18

1.5 Strip OxideForm N-Well regions

Grow oxide

Deposit photoresist

Pattern photoresist NWELL Mask expose only n-well areas

Etch oxide

Remove photoresist

Diffuse n-type dopants through oxide mask layer

Strip off the remaining oxide using HF

Layout view

Cross section view

p-type substrate

n-well

VLSI Design19

2.1 Spin Resist

Form Active Regions

Deposit SiN over wafer Deposit photoresist

over SiN layer

ACTIVE mask

ACTIVE mask

SiN photoresist

p-type substrate

n-well

VLSI Design20

2.2 Masking for Diffusion

Form Active Regions

Deposit SiN over wafer

Deposit photoresist over SiN layer

Pattern photoresist *ACTIVE MASK

ACTIVE mask

SiN photoresist

p-type substrate

n-well

VLSI Design21

ACTIVE mask

2.3 EtchingForm Active Regions


Deposit photoresist over SiN layer


Etch SiN in exposed areas leaves SiN mask which

blocks oxide growth

SiN photoresist

p-type substrate

n-well

VLSI Design22

ACTIVE mask

2.4 Oxide Growth

Form Active Regions


Deposit photoresist over SiNlayer


Etch SiN in exposed areas leaves SiN mask which blocks

oxide growth

Remove photoresist Grow Field Oxide

(FOX) thermal oxidation

p-type substrate

n-well

FOX

VLSI Design23

ACTIVE mask

2.5 Strip Oxide

Form Active Regions


Deposit photoresist over SiNlayer


Etch SiN in exposed areas leaves SiN mask which blocks

oxide growth

Remove photoresist

Grow Field Oxide (FOX) thermal oxidation

Remove SiN

p-type substrate

n-well

FOX

VLSI Design24

ACTIVE mask

3.1 Thin Gate Oxide

Form Gate (Poly layer)

Grow thin Gate Oxide over entire wafer negligible effect on FOX

regions

gate oxide

VLSI Design25

POLY mask

3.2 Deposit Poly & PhotoresistForm Gate (Poly layer)

Grow thin Gate Oxide over entire wafer negligible effect on FOX regions

Deposit Polysilicon Chemical Vapor

Deposition (CVD) of silicon layer Place wafer in furnace

with Silane gas (SiH4) Forms many small

crystals called polysilicon Heavily doped to be good

conductor

Deposit Photoresist

gate oxide

POLY mask

POLY mask

polysilicon

VLSI Design26

3.3 LithographyForm Gate (Poly layer)

Grow thin Gate Oxide over entire wafer negligible effect on FOX regions

Deposit Polysilicon

Deposit Photoresist

Pattern Photoresist *POLY MASK

Etch Poly in exposed areas

Etch/remove Oxide gate protected by poly

gate oxide

POLY mask

VLSI Design27

POLY mask

3.4 Etch

Form Gate (Poly layer)

Grow thin Gate Oxide over entire wafer negligible effect on FOX

regions

Deposit Polysilicon

Deposit Photoresist

Pattern Photoresist *POLY MASK

Etch Poly in exposed areas

Etch/remove Oxide gate protected by poly

gate oxide

VLSI Design28

POLY mask

4.1 PhotoresistForm pmos S/D

Cover with photoresist

PSELECT mask

VLSI Design29

PSELECT mask

4.2 Masking Form pmos S/D


Pattern photoresist *PSELECT MASK

PSELECT mask

VLSI Design30

PSELECT mask

4.3 p-type doping

Form pmos S/D


Pattern photoresist *PSELECT MASK

Implant p-type dopants P-diffusion forms pMOS

source, drain, and p-substrate contact

Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing

Remove photoresist

p+ dopantp+ dopant

VLSI Design31

PSELECT mask

4.4 PhotoresistForm nmos S/D


NSELECT mask

p+p+ p+

n

VLSI Design32

NSELECT mask

4.5 MaskingForm nmos S/D

Cover with photoresist Pattern photoresist

*NSELECT MASK

NSELECT mask

p+p+ p+

n

VLSI Design33

NSELECT mask

4.6 n-type doping

Form nmos S/D

Cover with photoresist Pattern photoresist

*NSELECT MASK

Implant n-type dopants N-diffusion forms nMOS

source, drain, and n-well contact

Remove photoresist

n+ dopantn+ dopant

p+p+ p+

n

n+ n+ n+

VLSI Design34

NSELECT mask

5.1 Spin ResistForm Contacts

Deposit oxide Deposit photoresist

CONTACT mask

p+p+ p+

n

n+ n+ n+

CONTACT mask

VLSI Design35

5.2 MaskingForm Contacts

Deposit oxide Deposit photoresist Pattern photoresist

*CONTACT Mask One mask for both active

and poly contact shown

CONTACT mask

p+p+ p+

n

n+ n+ n+

VLSI Design36

CONTACT mask

5.3 EtchForm Contacts

Deposit oxide

Deposit photoresist

Pattern photoresist *CONTACT Mask One mask for both active

and poly contact shown

Etch oxide

p+p+ p+

n

n+ n+ n+

VLSI Design37

CONTACT mask

5.4 Deposit Metal 1Form Contacts

Deposit oxide

Deposit photoresist

Pattern photoresist *CONTACT Mask One mask for both active and

poly contact shown

Etch oxide

Remove photoresist Deposit metal1

immediately after opening contacts so no native oxide grows in contacts

Planerize make top level

p+p+ p+

n

n+ n+ n+

VLSI Design38

CONTACT mask

5.5 Further Metal Layers Rest of metal layers

follow similarly p+p+ p+

n

n+ n+ n+

p-type substrate

VLSI Design39

METAL2 mask

Metalization

Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

M etal

VLSI Design40

Advanced Metallization

VLSI Design41

Advanced Metallization

VLSI Design42

Twin-Well CMOS Process

Separate optimization of NMOS and PMOS

Vth, body effect and channel transconductance

Reduces unbalanced drain parasitics

VLSI Design43

Silicon-on-Insulator (SOI)

Insulating substrate instead of silicon Improved speed and latch up susceptibility Independent NMOS and PMOS creation Higher integration density (no wells), avoidance of latch-up

problem and low parasitics

VLSI Design44

Design Rulesand

Layout

Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and

hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon

Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of λ = f/2 E.g. λ = 0.3 μm in 0.6 μm process

VLSI Design46

p-substrate n-well n+ p+ Gate oxide Gate (polysilicon) Field Oxide Insulated glass Provide electrical isolation

VLSI Design47

Layer Types

CMOS Process Layers Color CodingLayer

Polysilicon

Well (p,n)

Active Area (n+)

Color Representation

Yellow

Green

RedMetal1

Metal2

Blue

Magenta

Contact To Poly

Contact To Diffusion

Via

Black

Black

Black

Select (n+) GreenActive Area (p+) Beige

VLSI Design48

Layers in 0.25 μm CMOS process

VLSI Design49

Two major approaches: “Micron” rules: stated at micron resolution. λ rules: simplified micron rules with limited scaling attributes.

Design rules represents a tolerance which insures very high probability of correct fabrication scalable design rules: lambda parameter absolute dimensions (micron rules)

In reality, Design rules are determined by experience

VLSI Design50

Design Rule Conventions

All minimum sizes and spacing specified in microns. Rules don't have to be multiples of λ. Can result in 50% reduction in area over λ based rules Standard in industry.

VLSI Design51

“Micron” Rules

Lambda-based (scalable CMOS) design rules definescalable rules based on λ (which is half of theminimum channel length)

Stick diagram is a draft of real layout, it serves as anabstract view between the schematic and layout.

VLSI Design52

Lambda-based Design Rules

Circuit designer in general want tighter, smaller layoutsfor improved performance and decreased silicon area.

On the other hand, the process engineer wants designrules that result in a controllable and reproducibleprocess.

All widths, spacing, and distances are written in theform of λ = 0.5 X minimum drawn transistor length

VLSI Design53

Lambda-based Design Rules – Need

Design rules based on single parameter, λ

Simple for the designer

Wide acceptance

Minimum feature size is defined as 2 λ

Prevents shorting, opens, contacts from slipping out ofarea to be contacted

VLSI Design54

Lambda-based Design Rules – Advantages

Minimum width of PolySi and diffusion line = 2λ Minimum width of Metal line = 3λ as metal lines run over a

more uneven surface than other conducting layers to ensuretheir continuity

2λ

Metal

Diffusion

Polysilicon

3λ

2λVLSI

Design55


PolySi – PolySi space 2λ Metal - Metal space 2λ Diffusion – Diffusion space 3λ. To avoid the possibility of their

associated regions overlapping and conducting current

2λ

Metal

Diffusion

Polysilicon

2λ

3λVLSI

Design56


Diffusion – PolySi space λ. To prevent the lines overlapping toform unwanted capacitor

Metal lines can pass over both diffusion and polySi withoutelectrical effect. Where no separation is specified, metal linescan overlap or cross

λ

Metal

Diffusion

VLSI Design57


Metal lines can pass over both diffusion and polySi withoutelectrical effect

However, it is recommended practice to leave λ between ametal edge and a polySi or diffusion line to which it is notelectrically connected

λ

Metal

Polysilicon

VLSI Design58


Vias and Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2

VLSI Design59

VLSI Design60

Lambda-based Design Rules – Simplified

Wiring Tracks A wiring track is the space required for a wire 4 λ width, 4 λ spacing from neighbor = 8 λ pitch

Transistors also consume one wiring track

VLSI Design61

Well spacing Wells must surround transistors by 6 λ Implies 12 λ between opposite transistor flavors Leaves room for one wire track

VLSI Design62

6λ

2λ

6λ

2λ

3λ

All device mask dimensions are based on multiples of λ, e.g., polysilicon minimum width = 2λ. Minimum metal to metal spacing = 3λ

VLSI Design63

Lambda-based Design Rules – Example

Inverter Layout Transistor dimensions specified as Width / Length Minimum size is 4λ / 2λ, sometimes called 1 unit In f = 0.6 μm process, this is 1.2 μm wide, 0.6 μm long

VLSI Design64

Gate Layout Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells

Standard cell design methodology VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts

VLSI Design65

Example: Inverter

VLSI Design66

CMOS Inverter Layout

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’

VLSI Design67

Sticks Diagram

1

3

In Out

VDD

GND

Stick diagram of inverter

• Dimensionless layout entities• Only topology is important• Final layout generated by “compaction” program

VLSI Design68

Example: 3-input NAND Layout

Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 λ by 40 λ

VLSI Design69

Example: 3-input NAND Stick Diagrams

Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers

c

AVDD

GND

Y

AVDD

GND

B C

Y

INV

metal1polyndiffpdiffcontact

NAND3

VLSI Design70

Area Estimation

Estimate area by counting wiring tracksMultiply by 8 to express in λ

32

40

VLSI Design71

Example: O3AI Gate

Sketch a stick diagram for 4-input gate ( )Y A B C D= + +

VLSI Design72

Packaging

Packaging Requirements

Electrical: Low parasitics Mechanical: Reliable and robust Thermal: Efficient heat removal Economical: Cheap

VLSI Design74

Bonding Techniques

Lead Frame

Substrate

Die

Pad

Wire Bonding

VLSI Design75

Tape-Automated Bonding (TAB)

(a) Polymer Tape with imprinted

(b) Die attachment using solder bumps.

wiring pattern.

Substrate

Die

Solder BumpFilm + Pattern

Sprockethole

Polymer film

Leadframe

Testpads

VLSI Design76

Flip-Chip Bonding

Solder bumps

Substrate

Die

Interconnect

layers

VLSI Design77

Package-to-Board Interconnect

(a) Through-Hole Mounting (b) Surface Mount

VLSI Design78

References

Contents of this lecture are courtesy of Neil H. E. Weste Nivedita Shettar Jan M. Rabaey A. Mason

lecture 3

Documents