lecture #17: cpu design ii – controlcs61c/su05/lectures/l17-ajc-control.pdf · cs 61c l17 control...

CS 61C L17 Control (1) A Carle, Summer 2005 © UCB

inst.eecs.berkeley.edu/~cs61c/su05CS61C : Machine Structures

Lecture #17: CPU Design II – Control

2005-07-19

Andy Carle


Anatomy: 5 components of any Computer

Personal Computer

Processor

Computer

Control(“brain”)

Datapath(“brawn”)

Memory

(where programs, data live whenrunning)

Devices

Input

Output

Keyboard, Mouse

Display, Printer

Disk(where programs, data live whennot running)

This week


Review: A Single Cycle Datapath• Rs, Rt, Rd, Imed16 connected to datapath• We have everything except control signals

32

ALUctr

Clk

busW

RegWr

3232

busA

32busB

55 5

Rw Ra Rb32 32-bitRegisters

Rs

Rt

Rt

RdRegDst

Extender

Mux

Mux

3216imm16

ALUSrc

ExtOp

Mux

MemtoReg

Clk

Data InWrEn

32Adr

DataMemory

32

MemWrA

LU

InstructionFetch UnitClk

Zero

Instruction

0

1

0

1

01

Imm16RdRsRt

nPC_sel


An Abstract View of the Critical PathCritical Path (Load Operation) =

Delay clock through PC (FFs) +Instruction Memory’s Access Time +Register File’s Access Time, +ALU to Perform a 32-bit Add +Data Memory Access Time +Stable Time for Register File Write

Clk

5


RdA

LU

Clk

Data In

DataAddress Ideal

DataMemory

Instruction

InstructionAddress

IdealInstruction

Memory

Clk

PC

5Rs

5Rt

16Imm

32

323232A

B

Nex

t Add

ress

• This affects how much you can overclockyour PC!


Recap: Meaning of the Control Signals• nPC_MUX_sel: 0 ⇒ PC


Recap: Meaning of the Control Signals• ExtOp: “zero”, “sign”• ALUsrc: 0 ⇒ regB;

1 ⇒ immed• ALUctr: “add”, “sub”, “or”

° MemWr: 1 ⇒ write memory° MemtoReg: 0 ⇒ ALU; 1 ⇒ Mem° RegDst: 0 ⇒ “rt”; 1 ⇒ “rd”° RegWr: 1 ⇒ write register

32

ALUctr

Clk

busW

RegWr

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst

Extender

Mux

3216imm16

ALUSrcExtOp

Mux

MemtoReg

Clk

Data InWrEn32 Adr

DataMemory

MemWr

AL

U

Equal

0

1

0

1

01

=


RTL: The Add Instruction

add rd, rs, rt

•MEM[PC] Fetch the instruction from memory

•R[rd] = R[rs] + R[rt] The actual operation•PC = PC + 4 Calculate the next

instruction’s address

op rs rt rd shamt funct061116212631

6 bits 6 bits5 bits5 bits5 bits5 bits


Instruction Fetch Unit at the Beginning of Add• Fetch the instruction from Instruction memory: Instruction = MEM[PC]

• same for all instructions

PC E

xt

Adr

InstMemory

Adder

Adder

PC

Clk

00Mux

4

nPC_MUX_sel

imm

16Instruction


The Single Cycle Datapath during Add

32

ALUctr = Add

Clk

busW

RegWr = 1

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst = 1

Extender

Mux

Mux

3216imm16

ALUSrc = 0

ExtOp = x

Mux

MemtoReg = 0

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr = 0A

LU

InstructionFetch Unit

Clk

Zero

Instruction• R[rd] = R[rs] + R[rt]

0

1

0

1

01

Imm16RdRsRt


nPC_sel= +4


Instruction Fetch Unit at the End of Add• PC = PC + 4

• This is the same for all instructions except: Branch and Jump

Adr

InstMemory

Adder

Adder

PC

Clk

00Mux

4

nPC_MUX_sel

imm

16Instruction

0

1


Single Cycle Datapath during Or Immediate?op rs rt immediate

016212631

32

ALUctr =

Clk

busW

RegWr =

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst =

Extender

Mux

Mux

3216imm16

ALUSrc =

ExtOp =

Mux

MemtoReg =

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr = A

LU


Clk

Zero

Instruction

0

1

0

1

01

Imm16RdRsRt

nPC_sel =

• R[rt] = R[rs] OR ZeroExt[Imm16]


32

ALUctr = Or

Clk

busW

RegWr = 1

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst = 0

Extender

Mux

Mux

3216imm16

ALUSrc = 1

ExtOp = 0

Mux

MemtoReg = 0

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr = 0A

LU


Clk

Zero

Instruction

• R[rt] = R[rs] OR ZeroExt[Imm16]

0

1

0

1

01

Imm16RdRsRt

op rs rt immediate016212631

nPC_sel= +4

Single Cycle Datapath during Or Immediate?


The Single Cycle Datapath during Load?

32

ALUctr=

Clk

busW

RegWr =

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst =

Extender

Mux

Mux

3216imm16

ALUSrc =

ExtOp =

Mux

MemtoReg =

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr =A

LU


Clk

Zero

Instruction

0

1

0

1

01

Imm16RdRsRt

• R[rt] = Data Memory {R[rs] + SignExt[imm16]}op rs rt immediate

016212631

nPC_sel=


The Single Cycle Datapath during Load

32

ALUctr= Add

Clk

busW

RegWr = 1

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst = 0

Extender

Mux

Mux

3216imm16

ALUSrc = 1

ExtOp = 1

Mux

MemtoReg = 1

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr = 0A

LU


Clk

Zero

Instruction

0

1

0

1

01

Imm16RdRsRt

• R[rt] = Data Memory {R[rs] + SignExt[imm16]}op rs rt immediate

016212631

nPC_sel= +4


The Single Cycle Datapath during Store?op rs rt immediate

016212631

32

ALUctr =

Clk

busW

RegWr =

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst =

Extender

Mux

Mux

3216imm16

ALUSrc =

ExtOp =

Mux

MemtoReg =

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr = A

LU


Clk

Zero

Instruction

0

1

0

1

01

Imm16RdRsRt

nPC_sel =

• Data Memory {R[rs] + SignExt[imm16]} = R[rt]


The Single Cycle Datapath during Store

32

ALUctr= Add

Clk

busW

RegWr = 0

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst = x

Extender

Mux

Mux

3216imm16

ALUSrc = 1

ExtOp = 1

Mux

MemtoReg = x

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr = 1A

LU


Clk

Zero

Instruction

0

1

0

1

01

Imm16RdRsRt

• Data Memory {R[rs] + SignExt[imm16]} = R[rt]op rs rt immediate

016212631

nPC_sel= +4


The Single Cycle Datapath during Branch?

32

ALUctr =

Clk

busW

RegWr =

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst =

Extender

Mux

Mux

3216imm16

ALUSrc =

ExtOp =

Mux

MemtoReg = x

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr =A

LU


Clk

Zero

Instruction

0

1

0

1

01

Imm16RdRsRt

• if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0op rs rt immediate

016212631

nPC_sel=


The Single Cycle Datapath during Branch

32

ALUctr =Sub

Clk

busW

RegWr = 0

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst = x

Extender

Mux

Mux

3216imm16

ALUSrc = 0

ExtOp = x

Mux

MemtoReg = x

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr = 0A

LU


Clk

Zero

Instruction

0

1

0

1

01

Imm16RdRsRt

• if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0op rs rt immediate

016212631

nPC_sel= “Br”


Instruction Fetch Unit at the End of Branch

• if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4

op rs rt immediate016212631

• What is encoding of nPC_sel?

• Direct MUX select?• Branch / not branch

• Let’s pick 2nd option

nPC_sel zero? MUX0 x 01 0 01 1 1

Adr

InstMemory

Adder

Adder

PCClk

00Mux

4

nPC_sel

imm

16

Instruction

0

1

Zero

nPC_MUX_sel

Q: What logic gate?


Step 4: Given Datapath: RTL -> Control

ALUctrRegDst ALUSrcExtOp MemtoRegMemWr Zero

Instruction

Imm16RdRsRt

nPC_sel

Adr

InstMemory

DATA PATH

Control

Op

Fun

RegWr


A Summary of the Control Signals (1/2)inst Register Transfer

ADD R[rd]


A Summary of the Control Signals (2/2)

add sub ori lw sw beq jumpRegDstALUSrcMemtoRegRegWriteMemWritenPCselJumpExtOpALUctr

1001000x

Add

1001000x

Subtract

01010000

Or

01110001

Add

x1x01001

Add

x0x0010x

Subtract

xxx0001x

xxx

op target address


op rs rt immediate

R-type

I-type

J-type

add, sub

ori, lw, sw, beq

jump

funcop 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010Appendix A

10 0000See 10 0010 We Don’t Care :-)


Administrivia

• Project 2 Due Sunday• HW 6 out tomorrow

• Slight shakeup of the schedule starting tomorrow (we’re only doing one Control lecture)

• This allows us to have the second midterm before the drop deadline, if that would be preferable


32

ALUctr =

Clk

busW

RegWr =

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst =

Extender

Mux

Mux

3216imm16

ALUSrc =

ExtOp =

Mux

MemtoReg =

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr =A

LU


Clk

Zero

Instruction

0

1

0

1

01

Imm16RdRsRt

• New PC = { PC[31..28], target address, 00 }

nPC_sel=

The Single Cycle Datapath during Jumpop target address

02631J-type jump

25

Jump=

TA26


The Single Cycle Datapath during Jump

32

ALUctr =x

Clk

busW

RegWr = 0

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst = x

Extender

Mux

Mux

3216imm16

ALUSrc = x

ExtOp = x

Mux

MemtoReg = x

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr = 0A

LU


Clk

Zero

Instruction

0

1

0

1

01

RdRsRt

• New PC = { PC[31..28], target address, 00 }

nPC_sel=0

Jump=1

Imm16

TA26

op target address02631

J-type jump25


Instruction Fetch Unit at the End of Jump

Adr

InstMemory

Adder

Adder

PCClk

00Mux

4

nPC_sel

imm

16

Instruction

0

1

Zero

nPC_MUX_sel

• New PC = { PC[31..28], target address, 00 }op target address

02631J-type jump

25

How do we modify thisto account for jumps?

Jump


Instruction Fetch Unit at the End of Jump

Adr

InstMemory

Adder

Adder

PC

Clk00

Mux

4

nPC_sel

imm

16

Instruction

0

1

Zero

nPC_MUX_sel

• New PC = { PC[31..28], target address, 00 }op target address

02631J-type jump

25

Mux

1

0

Jump

TA26

4 (MSBs)

00

Query• Can Zero still

get asserted?

• Does nPC_selneed to be 0?

• If not, what?


Build CL to implement Jump on paper now

Jump

Inst31Inst30Inst29Inst28Inst27Inst26Inst25

Inst01Inst00


Build CL to implement Jump on paper now

Jump

Inst31Inst30Inst29Inst28Inst27Inst26Inst25

Inst01Inst00

2-input6-bit-wideXNOR

A

B

6-inputAND

000010

111001010100

XNORBiAi


Peer Instruction

A. MemToReg=‘x’ & ALUctr=‘sub’. SUB or BEQ?B. ALUctr=‘add’. Which 1 signal is different for

all 3 of: ADD, LW, & SW? RegDst or ExtOp?C. “Don’t Care” signals are useful because we

can simplify our Boolean equations?

32

ALUctr

Clk

busW

RegWr

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst

Extender

Mux

Mux

3216imm16

ALUSrc

ExtOp

Mux

MemtoReg

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr

AL

U


Clk

Zero

Instruction

0

1

0

1

01

Imm16RdRsRt

nPC_sel


°5 steps to design a processor• 1. Analyze instruction set => datapath requirements• 2. Select set of datapath components & establish clock

methodology• 3. Assemble datapath meeting the requirements• 4. Analyze implementation of each instruction to

determine setting of control points that effects the register transfer.

• 5. Assemble the control logic°Control is the hard part°MIPS makes that easier

• Instructions same size• Source registers always in same place• Immediates same size, location• Operations always on registers/immediates

And in Conclusion… Single cycle control

Control

Datapath

Memory

ProcessorInput

Output

lecture #17: cpu design ii – controlcs61c/su05/lectures/l17-ajc-control.pdf · cs 61c l17 control...

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