Lecture 15. Writing Circuit EquationsLecture 15. Writing Circuit Equations

Jaeha KimMixed-Signal IC and System Group (MICS)Seoul National Universityjaeha@ieee.org

Outlines Readings

Willy M C Sansen “Analog Design Essentials ” Ch 2 Willy M. C. Sansen, Analog Design Essentials, Ch. 2

Overview Despite the advance in circuit simulators and optimizers, Despite the advance in circuit simulators and optimizers,

tools can never replace designers’ intuition and expertise. The best way to cultivate such expertise is to exercise writing as many equations as possible, since analytical equations y q p y qcan tell how the performance metrics will change with the design parameters while each simulation only tells the point-wise information.

However, most students find writing equations difficult and necessary. It is often because they try to model everything –let’s focus only on the design intent (that is everything is ideal in the way you want). Then you will find it much easier.

2

gm/ID Methodology Characterizes the operating region of a saturated

MOS device by the ratio Gm/IdsMOS device by the ratio Gm/Ids

According to the square law model, Gm/Id is an equivalent measure to the gate overdrive (Vgs-Vth):q g ( g )

If so, why bother using Gm/Id?

3

gm/ID Methodology Often, we need to increase Gm/Id ratio:

For a fixed IB and R, the largest gm maximizes the gaingain

Av = gm R

The largest gm also minimizes the input-referred noise:

4

Why use gm/ID?

35

40

0.18um NMOS

25

30

/A]

2/VOVBJT (q/kT)

15

20

g m/I D

[S/

Th l d l

5

10The sqaure-law model overestimates gm, as Vovapproaches to zero!

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50

VOV [V]

Using g /I directly sustains the accuracy into the W I5

Using gm/ID directly sustains the accuracy into the W.I.

Basic Figures of Merit

• Current efficiencySquare Law

• Current efficiency– Want large gm, for as little

current as possible D

mIg

OVV2

• Transit frequency mg OVV3 – Want large gm, without large Cgg

I t i i i

ggC 2L2

• Intrinsic gain– Want large gm, but no gds

ds

mgg

OVV2

6

Transit Frequency Plot

50

0.18um NMOS

40

0.18um NMOSSquare Law Model

20

30

f T [GH

z]

mgf 1

10

20f

ggT C

f2

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50

V [V]

VOV [V]

Intrinsic Gain Plot80

0.18um NMOS

60

70 Long Channel Model, =0.3

30

40

50

g m/g

ds

Short Channel Device

10

20

30

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50

10

V [V]

VOV [V]

VDS,SAT

So far, we assumed the MOS device operated in saturated region (hence considered its g )saturated region (hence considered its gm) We need to make sure that VDS > VDS,SAT VDS SAT = VGS-VTH = VOV according to the square-law modelDS,SAT GS TH OV g q

But, what if we use gm/ID, fT, and intrinsic gain to But, what if we use gm/ID, fT, and intrinsic gain to describe the device characteristics instead of VOV? Need a way to estimate VDS,SAT with these metrics Often use VDS,SAT 2/(gm/ID) This is a conservative estimate, esp. in the velocity saturation

regionregion9

VDSsat Estimate Based on gm/ID

0 35

0.4NMOS, L=0.18um

VDSsat

0.25

0.3

0.352/(gm/ID)

VOV “VDSsat” defined

0.15

0.2

0.25

[V] (arbitrarily) as VDS

at which 1/gds is equal to ½ of the

0.05

0.1~4kT/qq

value at VDS = VDD/2

2/(g /I ) is a reasonable estimate of “V ”

0 0.05 0.1 0.15 0.2 0.25 0.30

VOV [V]

2/(gm/ID) is a reasonable estimate of VDSsat

Sizing with gm/IDNMOS, 0.18...0.5um (step=20nm), VDS=0.9V

For the chosen For the chosen gm/ID and L, one can

101

W [A

/m] L=0.18um

one can determine W from this

I D/W

L=0.5um“sizing chart” –current density

/I

5 10 15 20/I [S/A]

vs. gm/ID

gm/ID [S/A]

Other Viewpoint: Max fT and fMAX

Dickson, et al., “The Invariance of Characteristic Current Densities in Nanoscale MOSFETs ” JSSC 08/2006in Nanoscale MOSFETs…, JSSC 08/2006.

max fT @ 0.3mA/um max fmax @ 0.2mA/um min NF@ 0.15mA/um

12

Writing Design Equations for Analog Analog building blocks:

CS/CD/CG stages differential pair current mirror CS/CD/CG stages, differential pair, current mirror, …

Let’s review their characteristics focusing on their intents

13

Review: Single-Stage Configurations

voltage buffer current buffervoltage buffer14

current buffer

Common-Source Amplifier Gain =

BW =

GBW =

Exercise: size transistor for GBW = 100MHz when C =3pF I = 0 2mACL=3pF, IL = 0.2mA The required gm : 2mS gm/ID = 10

Fi d I /W d th W f th i i h t15

Find ID/W and thus W from the sizing chart

CS Amplifier with Large RS and CGS

Gain =

BW =

GBW =

16

CS Amplifier with Feedback Capacitance Gain =

BW =

GBW

17

CS Amplifier with Source Degeneration gm,eff =

Rout =

Cin =

18

CS Amplifier with Source Degeneration (2) gm,eff =

Rout =

Zin =

19

CS Amplifier with Diode-Connected Load Rout =

Gain = Gain =

20

Push-Pull Amplifier Rout =

Gain =

BW =

GBW =

21

Source Follower

G i Gain =

R t Rout =

22

Active Inductor

Gain =

Zout =

Lout = Lout =

23

Active Inductor Loads

Compare their output bias voltagesg24

Cascode

Gain =

Rout =Rout

BW = BW

GBW = GBW =

The GBW remains unchanged!25

g

Folded Cascode

Gain =

Rout =Rout

BW = BW

GBW = GBW =

26

Regulated Cascode

Gain =

Rout =Rout

BW = BW

GBW = GBW =

27

Current Mirrors

Compare their output resistances and minimum Vout’s

28

Single-Stage OTA

Gain =

Rout =Rout

BW = BW

GBW = GBW =

29

Two-Stage OTA Gain =

BW BW

GBW

30