lecture 14 - bilkent universitykilyos.ee.bilkent.edu.tr/~eee314/downloads/l14.pdf · announcements...

Lecture 14Ozgur Aktas

[email protected]

March 20, 2006

What we have learnt up to now?

• Basic semiconductor equations

• Drawing band diagrams for pn junctions, and npn/pnp transistors

• RTL/DTL/TTL/ATTL/STTL analysis

– Analysis for states of each transistor– Transfer characteristics– Power dissipation– Definitions that relate to delay– Input/output currents, voltages– The problems/solutions of charge removal from base

• ECL basics

L14

Todays overview

• Announcements

• Output impedance of Darlington pull-up circuit

• Finish ECL

L14

Announcements

• Exam on April 13th

• HW2 due this Friday (March 24th)

• Tutorial session on April 10 evening

L14

Output impedance of Darlington pull-up circuit

The circuit is drawn as follows:

QP

RCP

QP2

REP

RC

Vout

+5V

Assuming the output current issmall the transistors QP andQP2 will be active. Then,ignoring Rbb′, the equivalentmodel will be:

RCP

REP

RC

Vout

+5V

IB(QP2)

β

IB(QP)

IB(QP)

IB(QP2)β

VBEA

VBEA

L14 1

Output impedance of Darlington pull-up circuit

RCP

REP

RC

Vout

+5V

IB(QP2)

β

IB(QP)

IB(QP)

IB(QP2)β

VBEA

VBEA

rout =∂Vo∂Io

Io = (β + 1)IB(QP2)

Io = (β + 1)

(

(β + 1)IB(QP ) −Vo + 0.7

REP

)

Ignoring the term with REP

Io = (β + 1)2 VCC − Vo − 2 ∗ VBEA

RC

∂Vo∂Io

=−RC

(β + 1)2

L14 2

ECL gates

The basic circuit forming the basisof ECL gates is the ”emittercoupled current switch”

VCC

-VEE

RCI RCR

QI QRVref

Vin

out

IRE

The operation of the currentswitch is based on changingthe transistor through which thecurrent IRE flows. This changeis fast, since the emitter currentof an active npn transistordepens exponentially on thebase-emitter voltage. For each60mV change in the base-emitter bias, the emitter currentof an active npn changes byexp(

VBEkTq

)

L14 1

ECL gates

The basic circuit forming the basisof ECL gates is the ”emittercoupled current switch”

VCC

-VEE

RCI RCR

QI QRVref

Vin

out

IRE

Band diagrams of E-Bjunctions of QI and QR.

< VrefVin

Vin Vref=

Vin Vref>

Emitter Base

L14 2

ECL gates

Emitter coupled current switch

VCC

-VEE

RCI RCR

QI QRVref

Vin

out

IRE

< VrefVin

Vin Vref=

Vin Vref>

Emitter Base

Assume VIH − VIL = 100mVVin < Vref − 0.05 :: QI is OFF, QR is ACT

Vin > Vref + 0.05 :: QI is ACT, QR is OFF

In order to guarantee ACT operation, the resistor,input voltage range, and power supply voltagesmust be selected APPROPRIATELY.

ECL standart ::VCC = 0V , VEE = −5.2V , Vref = −1.175V

So:Vin < Vref − 0.05 :: VCQI = VCC

Vin > Vref + 0.05 :: VCQI = VCC − RCCIRE

L14 3

ECL gates

”emitter coupled current switch”

VCC

-VEE

RCI RCR

QI QRVref

Vin

out

IRE

Basic ECL gate

VCC

-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV

VOUT VOUT(VINV) (VNINV)

L14 4

ECL gates

Basic ECL gateVCC

-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


The emitter followers ( QINV − Ro and QNINV − Ro ) provide extremelylow output impedance. Thereby increasing the capacity to feed highnumber of fan-out gates.

L14 5

ECL gatesOutput impedance of emitter follower

Emitter follower and model

VCC

-VEE

Vin

RO

Qef

VOUT

-VEE

Vin

RO

VOUT

VCC

IB

IBβRbb’

The output resistanceconsists of Rbb′ asseen from the output inparallel with Ro.

L14 6

ECL gatesOutput impedance of emitter follower

Model of emitter follower

-VEE

Vin

RO

VOUT

VCC

IB

IBβRbb’

Derivation HERE

L14 7

ECL inverter transfer characteristic: NINV

VCC

-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


Assume VIH − VIL = 100mV

Consider node NINV with VIN=logic0VIN < V ref − 0.05 (LOW voltage)

Now: QI :: OFF, QR::ACT

IRE =Vref − VBEA − (−VEE)

RE

IRCR = αIRE

IRCR = αVref − VBEA − (−VEE)

RE

VBQNINV= 0 − RCR ∗ IRCR

The node (NINV) is now at logic 0 value, which is:VOL = VBQNINV

− VBEA = 0 − RCR ∗ IRCR − VBEA

VOL = VBQNINV−VBEA = 0−RCR∗α

Vref − VBEA − (−VEE)

RE−VBEA

The resistor values and VEE is selected so that VOL ≈ −2 ∗ VBEA

L14 8


VCC

-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


270 300

1240

2000 Ω

Ω

ΩΩ

Ω2000

Use VBEA = 0.75V for ECL

NINV with VIN=logic0 (LOW)

VOL = −RCR ∗ αVref − VBEA − (−VEE)

RE− VBEA

VOL = −300 ∗ 0.98 ∗−1.175 − 0.75 − (−5.2)

1240− 0.75 = −1.526V

Note that this is for NINV output.

L14 9a


VCC

-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


270 300

1240

2000 Ω

Ω

ΩΩ

Ω2000


NINV with VIN=logic1 (HIGH)VIN > V ref + 0.05 (LOW voltage)Then, node NINV will be at logic1 (HIGH)VOH = 0 − VBEA = −0.75V


L14 9b


VCC

-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


270 300

1240

2000 Ω

Ω

ΩΩ

Ω2000


For (V ref − 0.05) < VIN < (V ref + 0.05)the logic state is indeterminate.QI is switching from OFF to ACT.QR is switching from ACT to OFF.

Assume V o (NINV) changes linearly as VIN changes fromVref − 0.05 to Vref + 0.05.

L14 9c


−1.5 −1.4 −1.3 −1.2 −1.1 −1.0 −0.9 −0.8 −0.7−1.6

−1.5

−1.4

−1.3

−1.2

−1.1

−1.0

−0.9

−0.8

−0.7

ECL characteristics

Vin

outp

uts

NON−inverting output

L14 10

ECL inverter transfer characteristic: INV

NINV with VIN = logic0 (LOW)VIN < V ref − 0.05 (LOW voltage)

Now: QI:: OFF, QR::ACT

Node INV (Vout) is at logic1 (HIGH)VOH = VCC − VBEA = −0.75V

Note that this is for INV output.

VCC

-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


270 300

1240

2000 Ω

Ω

ΩΩ

Ω2000

For(V ref − 0.05) < VIN < (V ref + 0.05)the logic state is indeterminate.QI is switching from OFF to ACT.QR is switching from ACT to OFF.

When VIN > (V ref + 0.05) QI is ACT.Assume Vo (INV) changes linearly as VIN changes from Vref−0.05to Vref + 0.05.

L14 11

ECL inverter characteristic: NINV & INV

−1.5 −1.4 −1.3 −1.2 −1.1 −1.0 −0.9 −0.8 −0.7−1.6

−1.5

−1.4

−1.3

−1.2

−1.1

−1.0

−0.9

−0.8

−0.7

ECL characteristics

Vin

outp

uts

NON−inverting output inverting output

L14 12


VCC

-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


Consider node INV with VIN=logic1VIN > V ref + 0.05 (HIGH)

Now: QI :: ACT, QR::OFF

IRE =VIN − VBEA − (−VEE)

RE

IRCI = αIRE

IRCI = αVIN − VBEA − (−VEE)

RE

VBQNINV= 0 − RCI ∗ IRCI

The node (INV) is now at logic 0 value, which is:VOL(INV ) = VBQNINV

− VBEA = 0 − RCI ∗ IRCI − VBEA

VOL(INV ) = 0 − RCI ∗ αVIN − VBEA − (−VEE)

RE− VBEA

L14 13

ECL inverter transfer characteristic: INVVCC

-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


270 300

1240

2000 Ω

Ω

ΩΩ

Ω2000


The resistor value RCI selectedto be smaller than RCR so thatVo = VOL for VIN = VOH

INV with VIN > (V ref + 0.05)=logic1(HIGH)VOL = 0 − RCI ∗ α

VIN − VBEA − (−VEE)

RE− VBEA

VOL = −270 ∗ 0.98 ∗VIN − 0.75 − (−5.2)

1240− 0.75

VOL = −0.213 ∗ VIN − 1.7


L14 14


−1.5 −1.4 −1.3 −1.2 −1.1 −1.0 −0.9 −0.8 −0.7−1.6

−1.5

−1.4

−1.3

−1.2

−1.1

−1.0

−0.9

−0.8

−0.7

ECL characteristics

Vin

outp

uts

L14 15


VCC

-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


270 300

1240

2000 Ω

Ω

ΩΩ

Ω2000

As VIN increases further, QIwill saturate whenVCE(QI) = VCES

Assume VBCS = 0.7VAssume VCES = 0.05V

VC(QI) = 0 − RCI ∗ αVIN − VBEA − (−VEE)

REVE(QI) = VIN − VBEA

Rather than try to remember Eq. 6.23, just useVCE(QI) = VCES for condition of saturation. When saturation ofQI happensVo = VIN + VBCS − VBEA

L14 16


VCC

-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


270 300

1240

2000 Ω

Ω

ΩΩ

Ω2000

As VIN increases further, QIwill saturate whenVCE(QI) = VCES

Assume VBCS = 0.7VAssume VCES = 0.05V

VC(QI) = −270 ∗ 0.98VIN + 4.45

1240= −0.213 ∗ VIN − 0.95

VE(QI) = VIN − 0.75

Solving for VCE(QI) = 0.05VINsat = −0.21V

L14 17


−1.6 −1.4 −1.2 −1.0 −0.8 −0.6 −0.4 −0.2 −0.0−1.7

−1.6

−1.5

−1.4

−1.3

−1.2

−1.1

−1.0

−0.9

−0.8

−0.7

ECL characteristics

Vin

outp

uts

L14 18


VIN LOGIC Vo (INV) V o (NINV)VIN < −1.180 LOGIC0 -0.75 -1.523VIN > −1.170 LOGIC1 LOW -0.75VIN > −0.21 INVALID SAT -0.75

L14 19

ECL inverter characteristic: Motorola-SPECs

Typical and AVERAGE characteristics

L14 20

ECL inverter characteristic: Motorola-SPECs

NML=|VOL(max) − VIL(max)| = | − 1.5 + 1.325| = 0.175VNMH=|VOH(min) − VIH(min)| = | − 0.85 + 1.025| = 0.175V(note that the definitions are somewhat different than the ones used in the book)

L14 21

ECL inverter power dissipation

ECL power dissipation dominated by DC dissipation.This is an approximation and will not hold at higher frequencies.Still, we will only consider DC dissipation of ECL gates.PL is the DC dissipation when NONINVERTING output is LOW.PH is the DC dissipation when NONINVERTING output is HIGH.

PL = −(−VEE) ∗ IEE = VEE ∗ IEE = VEE ∗ (IRE + I1 + I2)

VCC

-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


270 300

1240

2000 Ω

Ω

ΩΩ

Ω2000

IEE

I1 I2

L14 1

ECL inverter power dissipationVCC

-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


270 300

1240

2000 Ω

Ω

ΩΩ

Ω2000

IEE

I1 I2

PL = −(−VEE) ∗ IEE = VEE ∗ IEE = VEE ∗ (IRE + I1 + I2)

IRE =Vref − VBEA + VEE

RE

I1 =VOH + VEE

RE

I2 =VOL + VEE

RE

L14 2


-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


270 300

1240

2000 Ω

Ω

ΩΩ

Ω2000

IEE

I1 I2

PH = −(−VEE) ∗ IEE = VEE ∗ IEE = VEE ∗ (IRE + I1 + I2)

IRE =VOH − VBEA + VEE

RE

I1 =VOL + VEE

RE

I2 =VOH + VEE

RE

L14 2


-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


270 300

1240

2000 Ω

Ω

ΩΩ

Ω2000

IEE

I1 I2

PDC =PL + PH

2

L14 3


-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


270 300

1240

2000 Ω

Ω

ΩΩ

Ω2000

IEE

I1 I2

This specific circuits power dissipation to be asked in next quiz.

L14 4

ECL logic designVCC

-VEE

RCI RCR

QI1 QRVref

Vin1

IRE

RORO

QNINVQINV


QI2Vin2

QI3Vin3

Using OR-NOR and inverter-buffer gates is much easier in ECL.Also:If we connect output of 2 ECL gates, the outputs are logically ”OR”ed.

The reason why OR-NOR is to be preferred will be asked in next quiz.ECL implementation of a given logic function to be asked in the next quiz.

L14 1

ECL temperature dependence

The main source of temperature dependence comes from VBEA and VD.

∂VBE∂T

≈ −2mV/◦C

VD (diode built-in potential) also shows a similar change.

L14 1


Considering the basic ECL inverter/buffer:Output high level is given as:

VOH = −VBEA

So:∂VOH∂T

= 2mV/◦C

Output low level is given as:

VOL = −RCI ∗ αVIN − VBEA − (−VEE)

RE− VBEA

So:∂VOL∂T

= −RCIRE

(

∂VOHT

−VBEA

T

)

−VBEA

T≈ 1mV/◦C

L14 2


With increasing temperature, the NMH decreases and NML increases.The overall effect is a decrease in the noise marginIt would be better to ”compansate” so that the NM decreases slower.

L14 3

ECL family: ECL I

-VEE

RCI RCR

QI QRVref

Vin

IRE

RORO

QNINVQINV


Decouples grounds for switch and emitter followers.

L14 1

ECL family: ECL I/III/10k

-VEE

RCI RCR

QI QRVrefVin

IRE

RORO

QNINVQINV


Has temperature compensated reference.

L14 2

ECL family: ECL I/III/10k, temperaturecompensation

δ represents the change in junction voltage.

L14 3

ECL family: ECL I/III/10k, temperaturecompensation

∆VR =2δR1

R1 + R2− δ ≈ −0.77δ

∆VoutLOW = −∆VRRCRE

+ δRCRE

− delta

∆VoutHIGH = −δ

∆Vout(AV ERAGE) =∆VoutLOW+∆VoutHIGH

2 ≈ −0.77δSince average change in output levels is equal to change in VR, VR stays at midpoint of logic transition range. Hence, theNML and NMH changes equally. But NML and NMH still does change.

L14 4

ECL family: ECL 100k

QI QRVref

Vin

IRE

RORO

QNINVQINV


D1

D2

R

R RR=500

-VEE-VEE

-VEE

-Vref2=-3.2V

RE=300

Has constant current source (reducing dependence on VEE)Diodes and R reduce temperature coefficients of VOL and VOH.Also has better temperature compansated reference voltage supply.

L14 5

ECL family: Level sensitive active pull-down

-VEE

RCI

RCR

QI QRVrefVin

IRE

VREG

Vo

Vref2

Definitely makes a nice HW-quix/exam question.

Active pulldown decreasesLtLH.

VREG = VOL − VBEA.

L14 6

Omission Note:

Not responsible from sections 6.10.1 and 6.11

L14 1

Next Lecture Hour:

Will finish ECL.Finish reading ECL in preparation of quiz.Will start MOS.Make a quick reading of MOS chapter for quiz.

L14 1

lecture 14 - bilkent universitykilyos.ee.bilkent.edu.tr/~eee314/downloads/l14.pdf · announcements...

Documents