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EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 1
Lecture #13
OUTLINE
�MOSFET ID vs. VGS characteristic
�Circuit models for the MOSFET
� resistive switch model
�small-signal model
Reading
� Hambley: Chapter 12.1-12.6
� Rabaey: Section 3.3
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 2
At high electric fields, the average velocity of carriers is
NOT proportional to the field; it saturates at ~107 cm/sec
for both electrons and holes:
Velocity Saturation
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 3
Current Saturation in Modern MOSFETs� In digital ICs, we typically use transistors with the
shortest possible gate-length for high-speed operation.
� In a very short-channel MOSFET, ID saturates because
the carrier velocity is limited to ~107 cm/sec
v is not proportional to E,
due to velocity saturation
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 4
1. ID is lower than that predicted by the mobility model
2. ID increases linearly with VGS − VT rather than quadratically in the saturation region
Consequences of Velocity Saturation
sat
n
DSAT
satDSAT
TGSoxDSAT
vL
V
vV
VVWCI
µ=
−−=
where
2
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 5
MOSFET VT Measurement
� VT can be determined by plotting ID vs. VGS,
using a low value of VDS :
DSDS
TGSnD VV
VVL
WkI
−−′=2
ID (A)
VGS (V)VT
0
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 6
Subthreshold Conduction (Leakage Current)� The transition from the ON state to the OFF state
is gradual. This can be seen more clearly when
ID is plotted on a logarithmic scale:
� In the subthreshold
(VGS < VT) region,
This is essentially the channel-
source pn junction current.
(Some electrons diffuse from the
source into the channel, if this
pn junction is forward biased.)
∝nkT
qVI GSD exp
VDS > 0
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 7
Qualitative Explanation for Subthreshold Leakage
� The channel Vc (at the Si surface) is capacitively
coupled to the gate voltage VG:
ox
dep
ox
depox
C
C
C
CCn +=
+=⇒ 1
Cox
Cdep+
Vc
–
VG
Using the capacitive
voltage divider formula:
p-type Si
n+ poly-Si
n+ n+
depletion
region
VG
CIRCUIT MODELDEVICE
The forward bias on
the channel-source pn
junction increases with
VG scaled by the factor
Cox / (Cox+Cdep)
VD G
depox
oxc V
CC
CV ∆
+=∆
Adep
Sidep
NWC
1∝=
ε
Wdep
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 8
Slope Factor (or Subthreshold Swing) S� S is defined to be the inverse slope of the log (ID)
vs. VGS characteristic in the subthreshold region:
VDS > 0
1/S is the slope
)10ln(
≡
q
kTnS
Units: Volts per decade
Note that S ≥ 60 mV/dec
at room temperature:
mV 60)10ln( =
q
kT
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 9
VT Design Trade-Off
(Important consideration for digital-circuit applications)� Low VT is desirable for high ON current
IDSAT ∝∝∝∝ (VDD - VT)ηηηη 1 < η < 2
where VDD is the power-supply voltage
…but high VT is needed for low OFF currentLow VT
High VT
IOFF,high VT
IOFF,low VT
VGS
log IDS
0
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 10
The MOSFET as a Resistive Switch� For digital circuit applications, the MOSFET is
either OFF (VGS < VT) or ON (VGS = VDD). Thus,
we only need to consider two ID vs. VDS curves:
1. the curve for VGS < VT
2. the curve for VGS = VDD
ID
VDS
VGS = VDD (closed switch)
VGS < VT (open switch)
Req
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 11
Equivalent Resistance Req� In a digital circuit, an n-channel MOSFET in the
ON state is typically used to discharge a
capacitor connected to its drain terminal:
� gate voltage VG = VDD
� source voltage VS = 0 V
� drain voltage VD initially at VDD, discharging toward 0 V
The value of Req should be
set to the value which gives
the correct propagation
delay (time required for
output to fall to ½VDD):
Cload
−≅ DDn
DSATn
DDeq V
I
VR λ
6
51
4
3( )2
2TnDD
nDSATn VV
L
WkI −
′=
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 12
Typical MOSFET Parameter Values� For a given MOSFET fabrication process
technology, the following parameters are known:
� VT (~0.5 V)
� Cox and k′′′′ (<0.001 A/V2)
� VDSAT (≤ 1 V)
� λ λ λ λ (≤ 0.1 V-1)
Example Req values for 0.25 µm technology (W = L):
How can Req be decreased?
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 13
MOSFET Model for Analog Circuits
� For analog circuit applications, the MOSFET is biased in the saturation region, and the circuit is designed to process incremental signals.� A DC operating point is established by the bias voltages VBIAS
and VDD, such that VDS > VGS – VT
� Incremental voltages vs and vds that are much smaller in magnitude perturb the operating point
� The MOSFET small-signal model is a circuit which models the change in the drain current (id) in response to these perturbations
MOSFET+–
+–
RD
VDDVBIAS
vs
G
S S
D
ID + id
+
VDS + vds
−−−−
−−−− +
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 14
NMOSFET Small-Signal Model
gmvgs ro
+
vgs
−−−−
id
( )
D
DS
Do
TGS
GS
Dm
dsogsmds
DS
Dgs
GS
Dd
Iv
ig
VVkL
W
v
ig
vgvgvv
iv
v
ii
λ≅∂∂
≡
−′≅∂∂
≡
+=∂∂
+∂∂
=S
D
S
G
transconductance
output conductance
+
vds
−−−−
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 15
Notation� Subscript convention (Lecture 2, Slide 11):
� VDS ≡≡≡≡ VD – VS , VGS ≡ VG – VS , etc.
� Double-subscripts denote DC sources (Lecture 23, Slide 7):� VDD , VCC , ISS , etc.
• To distinguish between DC and AC components of an electrical quantity, the following convention is used:
– DC quantity: upper-case letter with upper-case subscript
� ID , VDS , etc.
– AC quantity: lower-case letter with lower-case subscript
� id , vds , etc.
– Total (DC + AC) quantity:
lower-case letter with upper-case subscript
� iD , vDS , etc.
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 16
P-Channel MOSFET Example� In a digital circuit, a p-channel MOSFET in the
ON state is typically used to charge a capacitor
connected to its drain terminal:
� gate voltage VG = 0 V
� source voltage VS = VDD (power-supply voltage)
� drain voltage VD initially at 0 V, charging toward VDD
Cload
−≅ DDp
DSATp
DDeq V
I
VR λ
6
51
4
3
VDD
0 V
iD
( )22
TpDD
p
DSAT VVL
WkI −
′−=
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 17
Common-Source (CS) Amplifier� The input voltage
vs causes vGS to
vary with time,
which in turn
causes iD to vary.
VDD
RD
+
vOUT = vDS
−−−−
+
vIN = vGS
−−−−
+–
VBIAS
vs−−−− +
iD
� The changing voltage
drop across RD causes
an amplified (and
inverted) version of the
input signal to appear
at the drain terminal.
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 18
Load-Line Analysis of CS Amplifier� The operating point of the circuit can be determined
by finding the intersection of the appropriate
MOSFET iD vs. vDS characteristic and the load line:
DSDDDD viRV +=
vGS (V)
vDS (V)
iD (mA) load-line equation:
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 19
Voltage Transfer Function
(1): transistor biased in cutoff region
(2): vIN > VT ; transistor biased in saturation region
(3): transistor biased in saturation region
(4): transistor biased in “resistive” or “triode” region
Goal:
Operate the amplifier
in the high-gain region,
so that small changes
in vIN result in large
changes in vOUTvIN
vOUT
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 20
Quiescent Operating Point� The operating point of the amplifier for zero input
signal (vs = 0) is often referred to as the quiescent
operating point or Q point.
� The Q point should be chosen so that the output voltage
is approximately centered between VDD and 0 V.
� vs varies the input voltage around the Q point.
Note: The relationship between vOUT and vIN is not linear;
this results in a distorted output voltage signal. If the
input signal amplitude is very small, however, we can
have amplification with negligible distortion.
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 21
Bias Circuit Example
VDD
RD
R1
R2
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 22
Rules for Small-Signal Analysis
� A DC supply voltage source acts as a short circuit
� Even if AC current flows through the DC voltage source,
the AC voltage across it is zero.
� A DC supply current source acts as an open circuit
� Even if AC voltage is applied across the current source,
the AC current through it is zero.
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 23
Small-Signal Equivalent Circuit
gmvgs ro
+
vgs
−−−−
RD
+
vout
−−−−
R1 R2
G
S S
D
+
vin
−−−−
( )
( )Dom
in
outv
Dogsmout
Rrgv
vA
Rrvgv
||
||
−==
−=
voltage gain
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 24
1. Voltage amplifier
input & output signals are voltages
2. Current amplifier
input and output signals are currents
3. Transconductance amplifier
input signal is voltage;
output signal is current
4. Transresistance amplifier
input signal is current;
output signal is voltage
Amplifier Types
amplifier+vin−−−−
+vout−−−−
amplifier
ioutiin
amplifier
iout+vin−−−−
amplifier
iin+vout−−−−
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 25
Two-Port Amplifier Model
for a transconductance amplifier
gmvin Rout
+
vin
−−−−
Rin
iout
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 26
Effect of Source and Load Resistances
� Overall transconductance is degraded by the
source resistance Rs and load resistance RL
gmvin Rout
+
vin
−−−−
RLRin+–vs
+
+=
outL
outm
sin
in
s
out
RR
Rg
RR
R
v
i
ioutRs
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 27
NMOSFET Summary: Current Flow
Gate current iG = 0
Body current iB = 0
� iS = −iD
G
S D
p-type Si
n+ poly-Si
NMOSFET Structure
n+ n+
iG
NMOSFET Circuit Symbol
iDiS
iB
+vGS
−−−−
−−−− vDS +
If vGS ≤ VT, iD = 0
If vGS > VT, iD > 0
Current is limited by either
• the resistance of the
inversion-charge layer, or
• velocity saturation
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 28
• When vGS ≤ VT, an n-type channel is not formed.
� No electrons flow from SOURCE to DRAIN
“CUTOFF mode”
• When vGS > VT, an n-type channel (“inversion” layer of
electrons at the surface of the semiconductor) is formed.
� Electrons may flow from SOURCE to DRAIN (iD > 0)
If vDS < vGS–VT, the inversion layer exists across the
entire channel length, and current iD increases with vDS
“LINEAR mode” or “TRIODE mode”
If vDS ≥ vGS–VT, the inversion layer is pinched off at the
drain end, and current iD does not increase with vDS
“SATURATION mode”
NMOSFET Summary: Modes of Operation
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 29
NMOSFET Summary: I-V Characteristics
vDS
iD
0
pn+n+
“SATURATION”
“LINEAR”
or
“TRIODE” vGS = VG3 > VG2
vGS = VG2 > VG1
vDS= vGS–VT ≡ VDSAT
pn+ n+
pn+n+
“CUTOFF”( vGS ≤≤≤≤ VT )
pn+n+
vGS = VG1 > VT
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 30
NMOSFET Summary: I-V Equations
“SATURATION”“LINEAR” or “TRIODE”
DSDS
TGSnD vv
VvL
Wki
−−′=2
( )22
TGSn
D VvL
Wki −
′=
vDS
iD
0
vGS > VT
vDS= vGS–VT ≡ VDSAT
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 31
PMOSFET I-V Equations
“SATURATION” “LINEAR” or “TRIODE”
DSDS
TpGSpD vv
VvL
Wki
−−′−=2
( )22
TpGS
p
D VvL
Wki −
′−=
vDS
iD
0
|vGS| > |VTp|
vDS= vGS–VT ≡ VDSAT
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 32
Channel-length modulation:
� The length of the pinch-off region, ∆L, increases with increasing vDS above vGS–VT. It reduces the length of the
inversion layer and hence the resistance of this layer.
→ iD increases noticeably with vDS, if L is small
NMOSFET Summary: Non-Ideal Behavior
vDS
iD
0
cross-sectional
view of channel:
inversion layer
VDSAT
λ λ λ λ is the slope(channel-length
modulation parameter)
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 33
sat
n
DSAT
satDSAT
TGSoxDSAT
vL
V
vV
VvWCi
µ=
−−=
where
2
Velocity Saturation:
� In a very-short-channel MOSFET, iD saturates because
the carrier velocity is limited to ~107 cm/sec
� iD reaches a limit before pinch-off occurs
(continued)
< vGS–VT
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 34
(continued)
Subthreshold Leakage:
� For vGS ≤ VT, iD is exponentially dependent on vGS:
� The leakage current specification sets the lower limit for
the threshold voltage VT
leakage current, IOFFvGS
log iDS
0 VT
1/S is the slope
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 35
NMOSFET Summary: Circuit Models
� For analog circuit applications (where we are concerned
only with changes in current and voltage signals, rather
than their total values), the small-signal model is used:
( )
Do
TGSnm
Ig
VVkL
Wg
λ≅
−′≅
gmvgs 1/go
+
vgs
−−−−
id
S
D
S
G
transconductance
output conductancewhere VGS & ID are the
DC bias (Q point) values
EE40 Summer 2005: Lecture 13 Instructor: Octavian Florescu 36
NMOSFET Summary: Circuit Models
� For digital circuit applications, the MOSFET is modeled
as a resistive switch:Req
−≅ DDn
DSATn
DDeq V
I
VR λ
6
51
4
3
( )22
TnDDn
DSATn VVL
WkI −
′=
vDS
iD
0 VDDVDD/2
MOSFET is turned on
(VGS = VDD) when VDS = VDD
As the load capacitor discharges,
VDS decreases to 0 V
slope ≅≅≅≅ VDD
/ IDSAT
slope ≅≅≅≅ VDD / 2 IDSAT