lecture 12 vector machines/gpus overview topicsreadings: posix threads finished very long...

Lecture 12Vector Machines/GPUs Overview

Topics Topics

Readings:Readings: Posix Threads finished Very Long Instruction Word (VLIW) Vector Machines GPU overview

November 9, 2015

CSCE 513 Computer Architecture

– 2 – CSCE 513 Fall 2015

Multi-issue

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ROB- Multi Issue with Speculation

– 4 – CSCE 513 Fall 2015

..

https://computing.llnl.gov/tutorials/pthreads/

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Top 10 challenges in parallel computing

By By Michael Wrinn (Intel) In priority order: In priority order:1.1. Finding concurrency in a program - how to help Finding concurrency in a program - how to help

programmers “think parallel”?programmers “think parallel”?

2.2. Scheduling tasks at the right granularity onto the Scheduling tasks at the right granularity onto the processors of a parallel machine.processors of a parallel machine.

3.3. The data locality problem: associating data with tasks and The data locality problem: associating data with tasks and doing it in a way that our target audience will be able to use doing it in a way that our target audience will be able to use correctly.correctly.

4.4. Scalability support in hardware: bandwidth and latencies Scalability support in hardware: bandwidth and latencies to memory plus interconnects between processing to memory plus interconnects between processing elements.elements.

5.5. Scalability support in software: libraries, scalable Scalability support in software: libraries, scalable algorithms, and adaptive runtimes to map high level algorithms, and adaptive runtimes to map high level software onto platform details.software onto platform details.

http://software.intel.com/en-us/blogs/2008/12/31/top-10-challenges-in-parallel-computing/

http://software.intel.com/en-us/blogs/author/michael-wrinn/

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6.6. Synchronization constructs (and protocols) that Synchronization constructs (and protocols) that enable programmers write programs free from enable programmers write programs free from deadlock and race conditions.deadlock and race conditions.

7.7. Tools, API’s and methodologies to support the Tools, API’s and methodologies to support the debugging process.debugging process.

8.8. Error recovery and support for fault tolerance.Error recovery and support for fault tolerance.

9.9. Support for good software engineering practices: Support for good software engineering practices: composability, incremental parallelism, and code composability, incremental parallelism, and code reuse.reuse.

10.10. Support for portable performance. What are the Support for portable performance. What are the right models (or abstractions) so programmers right models (or abstractions) so programmers can write code once and expect it to execute well can write code once and expect it to execute well on the important parallel platforms?on the important parallel platforms?

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..

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1.1. Matrix multiplyMatrix multiply

2.2. Hello_args2.c (threaded program)Hello_args2.c (threaded program)

– 9 – CSCE 513 Fall 2015

ValgrindVALGRIND(1) VALGRIND(1)

NAMENAME

valgrind - a suite of tools for debugging and profiling programsvalgrind - a suite of tools for debugging and profiling programs

SYNOPSISSYNOPSIS

valgrind [[valgrind] [options]] [your-program] [[your-program-options]]valgrind [[valgrind] [options]] [your-program] [[your-program-options]]

DESCRIPTIONDESCRIPTION

Valgrind is a flexible program for debugging and profiling Linux Valgrind is a flexible program for debugging and profiling Linux executables. It consists of a core, which provides a synthetic CPU in executables. It consists of a core, which provides a synthetic CPU in software, and a series of "tools", each of which is a debugging or software, and a series of "tools", each of which is a debugging or profiling tool. The architecture is modular, so that new tools can be profiling tool. The architecture is modular, so that new tools can be created easily and without disturbing the existing structure.created easily and without disturbing the existing structure.

For more see /usr/share/doc/valgrind/html/index.htmlFor more see /usr/share/doc/valgrind/html/index.html

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Valgrind tools The following tools are available:The following tools are available:• cachegrind is a cache simulator. It can be used to annotate every cachegrind is a cache simulator. It can be used to annotate every

line of your program with the number of instructions executed and line of your program with the number of instructions executed and cache misses incurred.cache misses incurred.

• callgrind adds call graph tracing to cachegrind. It can be used to callgrind adds call graph tracing to cachegrind. It can be used to get call counts and inclusive cost for each call happening in your get call counts and inclusive cost for each call happening in your program. program.

In addition to cachegrind, callgrind can annotate threads separately, In addition to cachegrind, callgrind can annotate threads separately, and every instruction of disassembler output of your program with and every instruction of disassembler output of your program with the number of instructions executed and cache misses incurred.the number of instructions executed and cache misses incurred.

• helgrind spots potential race conditions in your program.helgrind spots potential race conditions in your program.• lackey is a sample tool that can be used as a template for lackey is a sample tool that can be used as a template for

generating your own tools. After the program terminates, it prints generating your own tools. After the program terminates, it prints out some basic statistics about the program execution.out some basic statistics about the program execution.

• massif is a heap profiler. It measures how much heap memory your massif is a heap profiler. It measures how much heap memory your program uses.program uses.

• memcheck is a fine-grained memory checker.memcheck is a fine-grained memory checker.

– 11 – CSCE 513 Fall 2015

Homework HW – Tomasulo’s 3.16 HW – Tomasulo’s 3.16 ROB Fall 2013 Test 2 problem 5ROB Fall 2013 Test 2 problem 5 Modify matmul.c to take an additional command line Modify matmul.c to take an additional command line

argument numThreads and create a multithreaded argument numThreads and create a multithreaded matrix multiply. (dues Tuesday)matrix multiply. (dues Tuesday)

– 12 – CSCE 513 Fall 2015

Data-Level ParallelismWe call these algorithms We call these algorithms data parallel algorithms data parallel algorithms

because their parallelism comes from simultaneous because their parallelism comes from simultaneous operations across large sets of data, rather than operations across large sets of data, rather than from multiple threads of control. W. Daniel Hillis and from multiple threads of control. W. Daniel Hillis and Guy L. Steele “Data Parallel Algorithms,” Comm. Guy L. Steele “Data Parallel Algorithms,” Comm. ACM (1986) ACM (1986)

““If you were plowing a field, which would you rather If you were plowing a field, which would you rather use: two strong oxen or 1024 chickens?” use: two strong oxen or 1024 chickens?”

Seymour Cray, Father of the SupercomputerSeymour Cray, Father of the Supercomputer

Patterson, David A.; Hennessy, John L. (2011-08-01). Computer Patterson, David A.; Hennessy, John L. (2011-08-01). Computer Architecture: A Quantitative Approach (The Morgan Kaufmann Series Architecture: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design) (Kindle Locations 6820-6826). in Computer Architecture and Design) (Kindle Locations 6820-6826). Elsevier Science (reference). Kindle Edition. Elsevier Science (reference). Kindle Edition.

– 13 – CSCE 513 Fall 2015Copyright © 2012, Elsevier Inc. All rights reserved.

Vector ArchitecturesBasic idea:Basic idea:

Read sets of data elements into “vector registers” Operate on those registers Disperse the results back into memory

Registers are controlled by compilerRegisters are controlled by compiler Used to hide memory latency Leverage memory bandwidth

Vector Architectures


VMIPSExample architecture: VMIPSExample architecture: VMIPS

Loosely based on Cray-1 Vector registers

Each register holds a 64-element, 64 bits/element vectorRegister file has 16 read ports and 8 write ports

Vector functional unitsFully pipelinedData and control hazards are detected

Vector load-store unitFully pipelinedOne word per clock cycle after initial latency

Scalar registers32 general-purpose registers32 floating-point registers



VMIPS InstructionsADDVV.D: add two vectorsADDVV.D: add two vectorsADDVS.D: add vector to a scalarADDVS.D: add vector to a scalarLV/SV: vector load and vector store from addressLV/SV: vector load and vector store from address

Example: DAXPYExample: DAXPYL.D F0,a ; load scalar aLV V1,Rx ; load vector XMULVS.D V2,V1,F0 ; vector-scalar multiplyLV V3,Ry ; load vector YADDVV V4,V2,V3 ; addSV Ry,V4 ; store the result

Requires 6 instructions vs. almost 600 for MIPSRequires 6 instructions vs. almost 600 for MIPS



Vector Execution TimeExecution time depends on three factors:Execution time depends on three factors:

Length of operand vectors Structural hazards Data dependencies

VMIPS functional units consume one element per VMIPS functional units consume one element per clock cycleclock cycle Execution time is approximately the vector length

ConveyConvey Set of vector instructions that could potentially execute

together



ChimesSequences with read-after-write dependency Sequences with read-after-write dependency

hazards can be in the same convey via hazards can be in the same convey via chaining chaining

ChainingChaining Allows a vector operation to start as soon as the

individual elements of its vector source operand become available

ChimeChime Unit of time to execute one convey m conveys executes in m chimes For vector length of n, requires m x n clock cycles



ExampleLVLV V1,RxV1,Rx ;load vector X;load vector X

MULVS.DMULVS.D V2,V1,F0V2,V1,F0 ;vector-scalar multiply;vector-scalar multiply

LVLV V3,RyV3,Ry ;load vector Y;load vector Y

ADDVV.DADDVV.D V4,V2,V3V4,V2,V3 ;add two vectors;add two vectors

SVSV Ry,V4Ry,V4 ;store the sum;store the sum

Convoys:Convoys:

11 LVLV MULVS.DMULVS.D

22 LVLV ADDVV.DADDVV.D

33 SVSV

3 chimes, 2 FP ops per result, cycles per FLOP = 1.53 chimes, 2 FP ops per result, cycles per FLOP = 1.5

For 64 element vectors, requires 64 x 3 = 192 clock cyclesFor 64 element vectors, requires 64 x 3 = 192 clock cycles


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ChallengesStart up timeStart up time

Latency of vector functional unit Assume the same as Cray-1

Floating-point add => 6 clock cycles Floating-point multiply => 7 clock cycles Floating-point divide => 20 clock cycles Vector load => 12 clock cycles

ImprovementsImprovements:: > 1 element per clock cycle Non-64 wide vectors IF statements in vector code Memory system optimizations to support vector processors Multiple dimensional matrices Sparse matrices Programming a vector computer



Multiple LanesElement Element n n of vector register of vector register A A is “hardwired” to is “hardwired” to

element element nn of vector register of vector register BB Allows for multiple hardware lanes



Vector Length RegisterVector length not known at compile time?Vector length not known at compile time?

Use Vector Length Register (VLR)Use Vector Length Register (VLR)

Use strip mining for vectors over the maximum Use strip mining for vectors over the maximum length:length:low = 0;VL = (n % MVL); /*find odd-size piece using modulo op % */for (j = 0; j <= (n/MVL); j=j+1) { /*outer loop*/

for (i = low; i < (low+VL); i=i+1) /*runs for length VL*/Y[i] = a * X[i] + Y[i] ; /*main operation*/

low = low + VL; /*start of next vector*/VL = MVL; /*reset the length to maximum vector length*/

}



Consider:Consider:

for (i = 0; i < 64; i=i+1)for (i = 0; i < 64; i=i+1)

if (X[i] != 0)if (X[i] != 0)

X[i] = X[i] – Y[i];X[i] = X[i] – Y[i];

Use vector mask register to “disable” elements:Use vector mask register to “disable” elements:LVLV V1,RxV1,Rx ;load vector X into V1;load vector X into V1

LVLV V2,RyV2,Ry ;load vector Y;load vector Y

L.DL.D F0,#0F0,#0 ;load FP zero into F0;load FP zero into F0

SNEVS.DSNEVS.D V1,F0V1,F0 ;sets VM(i) to 1 if V1(i)!=F0;sets VM(i) to 1 if V1(i)!=F0

SUBVV.DSUBVV.D V1,V1,V2V1,V1,V2 ;subtract under vector mask;subtract under vector mask

SVSV Rx,V1Rx,V1 ;store the result in X;store the result in X

GFLOPS rate decreases!GFLOPS rate decreases!



Memory BanksMemory system must be designed to support high Memory system must be designed to support high

bandwidth for vector loads and storesbandwidth for vector loads and stores

Spread accesses across multiple banksSpread accesses across multiple banks Control bank addresses independently Load or store non sequential words Support multiple vector processors sharing the same

memory

Example:Example: 32 processors, each generating 4 loads and 2 stores/cycle Processor cycle time is 2.167 ns, SRAM cycle time is 15

ns How many memory banks needed?



StrideConsider:Consider:

for (i = 0; i < 100; i=i+1)for (i = 0; i < 100; i=i+1)

for (j = 0; j < 100; j=j+1) {for (j = 0; j < 100; j=j+1) {

A[i][j] = 0.0;A[i][j] = 0.0;

for (k = 0; k < 100; k=k+1)for (k = 0; k < 100; k=k+1)

A[i][j] = A[i][j] + B[i][k] * D[k][j];A[i][j] = A[i][j] + B[i][k] * D[k][j];

}}

Must vectorize multiplication of rows of B with columns of DMust vectorize multiplication of rows of B with columns of D

Use Use non-unit stridenon-unit stride

Bank conflict (stall) occurs when the same bank is hit faster than Bank conflict (stall) occurs when the same bank is hit faster than bank busy time:bank busy time: #banks / LCM(stride,#banks) < bank busy time



Scatter-GatherConsider:Consider:

for (i = 0; i < n; i=i+1)for (i = 0; i < n; i=i+1)

A[K[i]] = A[K[i]] + C[M[i]];A[K[i]] = A[K[i]] + C[M[i]];

Use index vector:Use index vector:

LVLV Vk, RkVk, Rk ;load K;load K

LVILVI Va, (Ra+Vk)Va, (Ra+Vk) ;load A[K[]];load A[K[]]

LVLV Vm, RmVm, Rm ;load M;load M

LVILVI Vc, (Rc+Vm)Vc, (Rc+Vm) ;load C[M[]];load C[M[]]

ADDVV.DADDVV.D Va, Va, VcVa, Va, Vc ;add them;add them

SVISVI (Ra+Vk), Va(Ra+Vk), Va ;store A[K[]];store A[K[]]



Programming Vec. Architectures

Compilers can provide feedback to programmersCompilers can provide feedback to programmers

Programmers can provide hints to compilerProgrammers can provide hints to compiler



SIMD ExtensionsMedia applications operate on data types narrower Media applications operate on data types narrower

than the native word sizethan the native word size Example: disconnect carry chains to “partition” adder

Limitations, compared to vector instructions:Limitations, compared to vector instructions: Number of data operands encoded into op code No sophisticated addressing modes (strided, scatter-

gather) No mask registers

SIMD

Instruction Set Extensions for Multim

edia


SIMD ImplementationsImplementations:Implementations:

Intel MMX (1996)Eight 8-bit integer ops or four 16-bit integer ops

Streaming SIMD Extensions (SSE) (1999)Eight 16-bit integer opsFour 32-bit integer/fp ops or two 64-bit integer/fp ops

Advanced Vector Extensions (2010)Four 64-bit integer/fp ops

Operands must be consecutive and aligned memory locations

SIMD


edia


Example SIMD CodeExample DXPY:Example DXPY:

L.DL.D F0,aF0,a ;load scalar a;load scalar a

MOVMOV F1, F0F1, F0 ;copy a into F1 for SIMD MUL;copy a into F1 for SIMD MUL



DADDIUDADDIU R4,Rx,#512R4,Rx,#512 ;last address to load;last address to load

Loop:Loop: L.4D F4,0[Rx]L.4D F4,0[Rx] ;load X[i], X[i+1], X[i+2], X[i+3];load X[i], X[i+1], X[i+2], X[i+3]

MUL.4DMUL.4D F4,F4,F0F4,F4,F0 ;a×X[i],a×X[i+1],a×X[i+2],a×X[i+3];a×X[i],a×X[i+1],a×X[i+2],a×X[i+3]

L.4DL.4D F8,0[Ry]F8,0[Ry];load Y[i], Y[i+1], Y[i+2], Y[i+3];load Y[i], Y[i+1], Y[i+2], Y[i+3]

ADD.4DADD.4D F8,F8,F4F8,F8,F4 ;a×X[i]+Y[i], ..., a×X[i+3]+Y[i+3];a×X[i]+Y[i], ..., a×X[i+3]+Y[i+3]

S.4DS.4D 0[Ry],F80[Ry],F8;store into Y[i], Y[i+1], Y[i+2], Y[i+3];store into Y[i], Y[i+1], Y[i+2], Y[i+3]

DADDIUDADDIU Rx,Rx,#32Rx,Rx,#32 ;increment index to X;increment index to X

DADDIUDADDIU Ry,Ry,#32Ry,Ry,#32 ;increment index to Y;increment index to Y

DSUBUDSUBU R20,R4,RxR20,R4,Rx ;compute bound;compute bound

BNEZBNEZ R20,LoopR20,Loop ;check if done;check if done

SIMD


edia


Roofline Performance ModelBasic idea:Basic idea:

Plot peak floating-point throughput as a function of arithmetic intensity

Ties together floating-point performance and memory performance for a target machine

Arithmetic intensityArithmetic intensity Floating-point operations per byte read

SIMD


edia


ExamplesAttainable GFLOPs/sec Min = (Peak Memory BW × Attainable GFLOPs/sec Min = (Peak Memory BW ×

Arithmetic Intensity, Peak Floating Point Perf.)Arithmetic Intensity, Peak Floating Point Perf.)

SIMD


edia


Graphical Processing UnitsGiven the hardware invested to do graphics well, Given the hardware invested to do graphics well,

how can be supplement it to improve how can be supplement it to improve performance of a wider range of applications?performance of a wider range of applications?

Basic idea:Basic idea: Heterogeneous execution model

CPU is the host, GPU is the device Develop a C-like programming language for GPU Unify all forms of GPU parallelism as CUDA thread Programming model is “Single Instruction Multiple

Thread”

Graphical Processing U

nits


Threads and BlocksA thread is associated with each data elementA thread is associated with each data element

Threads are organized into blocksThreads are organized into blocks

Blocks are organized into a gridBlocks are organized into a grid

GPU hardware handles thread management, not GPU hardware handles thread management, not applications or OSapplications or OS


nits


NVIDIA GPU ArchitectureSimilarities to vector machines:Similarities to vector machines:

Works well with data-level parallel problems Scatter-gather transfers Mask registers Large register files

Differences:Differences: No scalar processor Uses multithreading to hide memory latency Has many functional units, as opposed to a few deeply

pipelined units like a vector processor


nits

– 35 – CSCE 513 Fall 2015

GTX480 GPU figure 4.15

Copyright © 2011, Elsevier Inc. All rights Reserved.

Figure 4.15 Floor plan of the Fermi GTX 480 GPU. This diagram shows 16 multithreaded SIMD Processors. The Thread Block Scheduler is highlighted on the left. The GTX 480 has 6

GDDR5 ports, each 64 bits wide, supporting up to 6 GB of capacity. The Host Interface is PCI Express 2.0 x 16. Giga Thread is the name of the scheduler that distributes thread blocks to

Multiprocessors, each of which has its own SIMD Thread Scheduler.


ExampleMultiply two vectors of length 8192Multiply two vectors of length 8192

Code that works over all elements is the grid Thread blocks break this down into manageable sizes

512 threads per block SIMD instruction executes 32 elements at a time Thus grid size = 16 blocks Block is analogous to a strip-mined vector loop with

vector length of 32 Block is assigned to a multithreaded SIMD processor by

the thread block scheduler Current-generation GPUs (Fermi) have 7-15

multithreaded SIMD processors


nits


TerminologyThreads of SIMD instructionsThreads of SIMD instructions

Each has its own PC Thread scheduler uses scoreboard to dispatch No data dependencies between threads! Keeps track of up to 48 threads of SIMD instructions

Hides memory latency

Thread block scheduler schedules blocks to SIMD Thread block scheduler schedules blocks to SIMD processorsprocessors

Within each SIMD processor:Within each SIMD processor: 32 SIMD lanes Wide and shallow compared to vector processors


nits


ExampleNVIDIA GPU has 32,768 registersNVIDIA GPU has 32,768 registers

Divided into lanes Each SIMD thread is limited to 64 registers SIMD thread has up to:

64 vector registers of 32 32-bit elements32 vector registers of 32 64-bit elements

Fermi has 16 physical SIMD lanes, each containing 2048 registers


nits


NVIDIA Instruction Set Arch.ISA is an abstraction of the hardware instruction setISA is an abstraction of the hardware instruction set

“Parallel Thread Execution (PTX)” Uses virtual registers Translation to machine code is performed in software Example:shl.s32 R8, blockIdx, 9 ; Thread Block ID * Block size (512 or

29)add.s32 R8, R8, threadIdx ; R8 = i = my CUDA thread IDld.global.f64 RD0, [X+R8] ; RD0 = X[i]ld.global.f64 RD2, [Y+R8] ; RD2 = Y[i]mul.f64 R0D, RD0, RD4 ; Product in RD0 = RD0 * RD4 (scalar

a)add.f64 R0D, RD0, RD2 ; Sum in RD0 = RD0 + RD2 (Y[i])st.global.f64 [Y+R8], RD0 ; Y[i] = sum (X[i]*a + Y[i])


nits


Conditional BranchingLike vector architectures, GPU branch hardware Like vector architectures, GPU branch hardware

uses internal masksuses internal masks

Also usesAlso uses Branch synchronization stack

Entries consist of masks for each SIMD lane I.e. which threads commit their results (all threads execute)

Instruction markers to manage when a branch diverges into multiple execution paths

Push on divergent branch …and when paths converge

Act as barriersPops stack

Per-thread-lane 1-bit predicate register, specified by Per-thread-lane 1-bit predicate register, specified by programmerprogrammer


nits


Exampleif (X[i] != 0)if (X[i] != 0)

X[i] = X[i] – Y[i];X[i] = X[i] – Y[i];

else X[i] = Z[i];else X[i] = Z[i];

ld.global.f64ld.global.f64 RD0, [X+R8]RD0, [X+R8] ; RD0 = X[i]; RD0 = X[i]

setp.neq.s32setp.neq.s32 P1, RD0, #0P1, RD0, #0 ; P1 is predicate register 1; P1 is predicate register 1

@!P1, bra@!P1, bra ELSE1, ELSE1, *Push*Push ; Push old mask, set new mask bits; Push old mask, set new mask bits

; if P1 false, go to ELSE1; if P1 false, go to ELSE1

ld.global.f64ld.global.f64 RD2, [Y+R8]RD2, [Y+R8] ; RD2 = Y[i]; RD2 = Y[i]

sub.f64sub.f64 RD0, RD0, RD2RD0, RD0, RD2 ; Difference in RD0; Difference in RD0

st.global.f64st.global.f64 [X+R8], RD0[X+R8], RD0 ; X[i] = RD0; X[i] = RD0

@P1, bra@P1, bra ENDIF1, ENDIF1, *Comp*Comp ; complement mask bits; complement mask bits

; if P1 true, go to ENDIF1; if P1 true, go to ENDIF1

ELSE1:ELSE1: ld.global.f64 RD0, [Z+R8]ld.global.f64 RD0, [Z+R8] ; RD0 = Z[i]; RD0 = Z[i]

st.global.f64 [X+R8], RD0st.global.f64 [X+R8], RD0 ; X[i] = RD0; X[i] = RD0

ENDIF1: ENDIF1: <next instruction>, *Pop<next instruction>, *Pop ; pop to restore old mask; pop to restore old mask


nits


NVIDIA GPU Memory StructuresEach SIMD Lane has private section of off-chip Each SIMD Lane has private section of off-chip

DRAMDRAM “Private memory” Contains stack frame, spilling registers, and private

variables

Each multithreaded SIMD processor also has local Each multithreaded SIMD processor also has local memorymemory Shared by SIMD lanes / threads within a block

Memory shared by SIMD processors is GPU Memory shared by SIMD processors is GPU MemoryMemory Host can read and write GPU memory


nits


Fermi Architecture Innovations

Each SIMD processor hasEach SIMD processor has Two SIMD thread schedulers, two instruction dispatch units 16 SIMD lanes (SIMD width=32, chime=2 cycles), 16 load-

store units, 4 special function units Thus, two threads of SIMD instructions are scheduled every

two clock cycles

Fast double precisionFast double precision

Caches for GPU memoryCaches for GPU memory

64-bit addressing and unified address space64-bit addressing and unified address space

Error correcting codesError correcting codes

Faster context switchingFaster context switching

Faster atomic instructionsFaster atomic instructions


nits


Fermi Multithreaded SIMD Proc. Graphical Processing U

nits


Loop-Level Parallelism

Focuses on determining whether data accesses in Focuses on determining whether data accesses in later iterations are dependent on data values later iterations are dependent on data values produced in earlier iterationsproduced in earlier iterations Loop-carried dependence

Example 1:Example 1:for (i=999; i>=0; i=i-1)for (i=999; i>=0; i=i-1)

x[i] = x[i] + s;x[i] = x[i] + s;

No loop-carried dependenceNo loop-carried dependence

Detecting and Enhancing Loop-Level Parallelism



Example 2:Example 2:for (i=0; i<100; i=i+1) {for (i=0; i<100; i=i+1) {

A[i+1] = A[i] + C[i]; /* S1 */A[i+1] = A[i] + C[i]; /* S1 */

B[i+1] = B[i] + A[i+1]; /* S2 */B[i+1] = B[i] + A[i+1]; /* S2 */

}}

S1 and S2 use values computed by S1 in previous S1 and S2 use values computed by S1 in previous iterationiteration

S2 uses value computed by S1 in same iterationS2 uses value computed by S1 in same iteration




Example 3:Example 3:for (i=0; i<100; i=i+1) {for (i=0; i<100; i=i+1) {

A[i] = A[i] + B[i]; /* S1 */A[i] = A[i] + B[i]; /* S1 */B[i+1] = C[i] + D[i]; /* S2 */B[i+1] = C[i] + D[i]; /* S2 */

}}S1 uses value computed by S2 in previous iteration but S1 uses value computed by S2 in previous iteration but

dependence is not circular so loop is paralleldependence is not circular so loop is parallelTransform to:Transform to:

A[0] = A[0] + B[0];A[0] = A[0] + B[0];for (i=0; i<99; i=i+1) {for (i=0; i<99; i=i+1) {

B[i+1] = C[i] + D[i];B[i+1] = C[i] + D[i];A[i+1] = A[i+1] + B[i+1];A[i+1] = A[i+1] + B[i+1];

}}B[100] = C[99] + D[99];B[100] = C[99] + D[99];




Example 4:Example 4:

for (i=0;i<100;i=i+1) {for (i=0;i<100;i=i+1) {

A[i] = B[i] + C[i];A[i] = B[i] + C[i];

D[i] = A[i] * E[i];D[i] = A[i] * E[i];

}}

Example 5:Example 5:

for (i=1;i<100;i=i+1) {for (i=1;i<100;i=i+1) {

Y[i] = Y[i-1] + Y[i];Y[i] = Y[i-1] + Y[i];

}}



Finding dependencies

Assume indices are affine:Assume indices are affine: a x i + b (i is loop index)

Assume:Assume: Store to a x i + b, then Load from c x i + d i runs from m to n Dependence exists if:

Given j, k such that m ≤ j ≤ n, m ≤ k ≤ nStore to a x j + b, load from a x k + d, and a x j + b = c x k +

d




Generally cannot determine at compile timeGenerally cannot determine at compile time

Test for absence of a dependence:Test for absence of a dependence: GCD test:

If a dependency exists, GCD(c,a) must evenly divide (d-b)

Example:Example:for (i=0; i<100; i=i+1) {

X[2*i+3] = X[2*i] * 5.0;}




Example 2:Example 2:for (i=0; i<100; i=i+1) {

Y[i] = X[i] / c; /* S1 */X[i] = X[i] + c; /* S2 */Z[i] = Y[i] + c; /* S3 */Y[i] = c - Y[i]; /* S4 */

}

Watch for antidependencies and output Watch for antidependencies and output dependenciesdependencies



ReductionsReduction Operation:Reduction Operation:

for (i=9999; i>=0; i=i-1)for (i=9999; i>=0; i=i-1)

sum = sum + x[i] * y[i];sum = sum + x[i] * y[i];

Transforms to…Transforms to…

for (i=9999; i>=0; i=i-1)for (i=9999; i>=0; i=i-1)

sum [i] = x[i] * y[i];sum [i] = x[i] * y[i];

for (i=9999; i>=0; i=i-1)for (i=9999; i>=0; i=i-1)

finalsum = finalsum + sum[i];finalsum = finalsum + sum[i];

Do on p processors:Do on p processors:

for (i=999; i>=0; i=i-1)for (i=999; i>=0; i=i-1)

finalsum[p] = finalsum[p] + sum[i+1000*p];finalsum[p] = finalsum[p] + sum[i+1000*p];

Note: assumes associativity!Note: assumes associativity!


lecture 12 vector machines/gpus overview topicsreadings: posix threads finished very long...

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