lecture 12 – flip-flops, memory borivoje...
TRANSCRIPT
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inst.eecs.berkeley.edu/~ee241b
Borivoje Nikolić
EE241B : Advanced Digital Circuits
Lecture 12 – Flip-Flops, Memory
March 3, 2020,
Presidential primary election
1EECS241B L12 MEMORY
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Announcements
• Assignment 2 due on Friday• Quiz 2 on Tuesday, March 10
2EECS241B L11 FLIP-FLOPS
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Outline
• Module 3• Design of flip-flops
• SRAM basics
3EECS241B L11 FLIP-FLOPS
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3. Design for Performance
3.D Latch Design
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Lecture 11 Errata
• Latch tD-Q (with CL = Cin)• tD-Q = 4.9 tunit ~ 1 FO4 (not 1.25 FO4)
• tsu = 6.6 tunit ~ 1.3 FO4 (not 1.55 FO4)
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3. Design for Performance
3.E Flip-Flop Design
6EECS241B L11 FLIP-FLOPS
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Key Point
• Two ways to design a flip-flop• Latch pair
• Pulsed latch
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Types of Flip-Flops
Latch Pair
(Master-Slave)
D
Clk
Q D
Clk
Q
Clk
DataD
Clk
Q
Clk
Data
Pulse-Triggered Latch
L1 L2 L
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Latch Pair as a Flip-Flop
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Sources of Noise
Courtesy of IEEE Press, New York. 2000EECS241B L11 FLIP-FLOPS 10
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Master-Slave Latch Pairs
• Example: PowerPC 603 (Gerosa, JSSC 12/94)
Vdd Vdd
Clk
QClk Clkb
Clkb
D
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Flip-Flop Clk-Q, setup, hold
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D
Clk
Clk
Clk
Q
Clk
Clk Clk
ClkCk
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Flip-Flop Timing Characterization
• Combinational logic delay is a function of output load and input slope
• Sequential timing (flip-flop):• tclk-q is function of output load and clock rise time
• tSu, tH are functions of D and Clk rise/fall times
Nikolić, Shao Fall 2019 © UCB 13
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Pulse-Triggered Latches
• First stage is a pulse generator• generates a pulse (glitch) on a rising edge of the clock
• Second stage is a latch• captures the pulse generated in the first stage
• Pulse generation results in a negative setup time
• Frequently exhibit a soft edge property
• Note: power is always consumed in the pulse generator• Often shared by a group (register)
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Pulsed Latch
Kozu, ISSCC’96
Simple pulsed latch
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Intel/HP Itanium 2
Naffziger, ISSCC’02
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Pulsed Latches
Hybrid Latch Flip-Flop, AMD K-6Partovi, ISSCC’96
Vdd
D
Clk
Q
Q
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HLFF Operation
1-0 and 0-1 transitions at the input with 0ps setup time
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Hybrid Latch Flip-Flop
Partovi et al, ISSCC’96
Skew absorption
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Pulsed Latches
AMD K-7
Courtesy of IEEE Press, New York. 2000EECS241B L11 FLIP-FLOPS 20
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Pulsed Latches
Partovi, VLSI’12
Used in a synthesized flow
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Pulsed Latches
7474, from mid-1960’s
Clk
D
Q
Q
S
R
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Pulsed Latches
First stage is a sense amplifier, precharged to high, when Clk = 0After rising edge of the clock sense amplifier generates the pulse on S or RThe pulse is captured in S-R latchCross-coupled NAND has different propagation delays of rising and falling edges
Sense-amplifier-based flip-flop, Matsui 1992.DEC Alpha 21264, StrongARM 110
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Sense Amplifier-Based Flip-Flop
Courtesy of IEEE Press, New York. 2000EECS241B L11 FLIP-FLOPS 24
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Sampling Window Comparison
Naffziger, JSSC 11/02
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3. Memory
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Random Access Memory Architecture
• Conceptual: Linear array of addresses• Each box holds some data
• Not practical to physically realize – millions of 32b/64b words
• Create a 2-D array• Decode Row and Column address to get data
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0x000…0
0xFFF…F
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Basic Memory Array (From 151/251A)• Core
• Wordlines to access rows
• Bitlines to access columns
• Data multiplexed onto columns
• Decoders• Addresses are binary
• Row/column MUXes are ‘one-hot’ - only one is active at a time
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SRAM Cell Trends
0.001
0.01
0.1
1
10
100
1101001000
Cel
l Siz
e [µ
m2 ]
Technology Node (nm)
ITRS CellITRS Eff. CellIndividual CellArray CellEff. Cell
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SRAM Scaling or Not?
• TSMC at IEDM’19
30
0.001
0.01
0.1
1
10
100
1101001000
Cel
l Siz
e [µ
m2 ]
Technology Node (nm)
ITRS CellITRS Eff. CellIndividual CellArray CellEff. Cell
• Bora’s spreadsheet
• TSMC at ISSCC’20
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SRAM Topics
A. Basics and trends
B. Static retention margin
C. Static read/write margins
D. Dynamic margins
D. Assist techniques
E. Periphery, redundancy and error correction
F. Scaling options
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3. Memory3.A SRAM Basics and Trends
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6-T SRAM Cell
• Improve CD control by unidirectional poly• Special SRAM design rules
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SRAM Cell Design Trends
• Key enabling technology:
• Impact:
Cell in 90nm(1m2)
Cell in 32nm(0.171m2)
IEDM
’
02
VDD
GNDWL
BL BLB
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SRAM Cell Trends (22nm)
0.092m2 cell in 22nm from Intel (IDF’09)
0.346m2 cell in 45nm from Intel (IEDM’07)
A little analysis by using a ruler:• Aspect ratio 2.9• Height ~178nm, Width ~518nm• Gate ~ 45nm (Lg is smaller)
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22nm SRAM – Discrete Widths
• FinFET cell design
E. Karl, ISSCC’12
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14nm SRAM
• Aspect ratio ~2.5
• Cell area = 0.05um2
• Height = 140nm (2 gate p)
• Width = 350nm
• Lg ~ 32nm
E. Karl, ISSCC’15
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10nm SRAM
• HDC 1:1:1
• LVC 1:1:2
Guo, ISSCC’18
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10nm SRAM + Ruler
2CPP = 108nm
288nm = 8 MxP
340nm
Lg 20nm
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Next Lecture
• SRAM read and write
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