lecture (03) multiplexers, decoders, and programmable...
TRANSCRIPT
![Page 1: Lecture (03) Multiplexers, Decoders, and Programmable ...draelshafee.net/Spring2019/cse303-logic-design-ii---lecture-03---multiplexers...•Microprocessors, FPGA, Application‐specific](https://reader031.vdocuments.site/reader031/viewer/2022013009/5e70579146036750ec048df8/html5/thumbnails/1.jpg)
Lecture (03)Multiplexers, Decoders, and Programmable Logic Devices
By:
Dr. Ahmed ElShafee
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic Design II1
Introduction
• Integrated Circuits (ICs)
– Small‐scale integration (SSI)
• NAND, NOR, AND, OR, inverter, Flip‐Flop
• 1‐4 gates, 6 inverters, 1‐2 Flip‐flops
– Medium‐scale integration (MSI)
• Adder, multiplexer, decoder, register, counter
• 12‐100 gates
– Large‐scale integration (LSI)
• Memories, microprocessors
• 100‐ a few thousand gates
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II2
![Page 2: Lecture (03) Multiplexers, Decoders, and Programmable ...draelshafee.net/Spring2019/cse303-logic-design-ii---lecture-03---multiplexers...•Microprocessors, FPGA, Application‐specific](https://reader031.vdocuments.site/reader031/viewer/2022013009/5e70579146036750ec048df8/html5/thumbnails/2.jpg)
– Very‐large‐scale integration (VLSI)
• Microprocessors, FPGA, Application‐specific integrated circuit (ASIC),…
• Several thousand gates or more
– Programmable logic devices (PLDs)
• Programmable logic arrays (PLAs)
• Programmable array Logic devices
• (PALs)
• Complex programmable logic devices
• (CPLDs)
• Field‐programmable gate arrays (FPGAs)Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II3
Multiplexers
• Multiplexers (MUX, or data selector)
– A MUX has a group of data inputs and a group of control inputs.
– The control inputs are used to select one of the data inputs and connect it to the output terminal.
• 2‐to 1 MUX
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II4
![Page 3: Lecture (03) Multiplexers, Decoders, and Programmable ...draelshafee.net/Spring2019/cse303-logic-design-ii---lecture-03---multiplexers...•Microprocessors, FPGA, Application‐specific](https://reader031.vdocuments.site/reader031/viewer/2022013009/5e70579146036750ec048df8/html5/thumbnails/3.jpg)
• 4‐to‐1, 8‐to‐1, 2n‐to‐1 MUX
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II5
•
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II6
![Page 4: Lecture (03) Multiplexers, Decoders, and Programmable ...draelshafee.net/Spring2019/cse303-logic-design-ii---lecture-03---multiplexers...•Microprocessors, FPGA, Application‐specific](https://reader031.vdocuments.site/reader031/viewer/2022013009/5e70579146036750ec048df8/html5/thumbnails/4.jpg)
• Logic equation for 8‐to‐1 MUX
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II7
Multiplexers
• Logic Diagram for 8‐to‐1 MUX
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II8
![Page 5: Lecture (03) Multiplexers, Decoders, and Programmable ...draelshafee.net/Spring2019/cse303-logic-design-ii---lecture-03---multiplexers...•Microprocessors, FPGA, Application‐specific](https://reader031.vdocuments.site/reader031/viewer/2022013009/5e70579146036750ec048df8/html5/thumbnails/5.jpg)
• Logic equation for 2n‐to‐1 MUX
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II9
where mk is a minterm of the n control variables and Ik is the corresponding data input
• Quad Multiplexer Used to Select Data
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II10
![Page 6: Lecture (03) Multiplexers, Decoders, and Programmable ...draelshafee.net/Spring2019/cse303-logic-design-ii---lecture-03---multiplexers...•Microprocessors, FPGA, Application‐specific](https://reader031.vdocuments.site/reader031/viewer/2022013009/5e70579146036750ec048df8/html5/thumbnails/6.jpg)
• Quad Multiplexer with Bus Input and Output
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II11
A=0, Z=XA=1, Z=Y
74157 (Quad 2‐line to 1‐line data selectors)•
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II12
![Page 7: Lecture (03) Multiplexers, Decoders, and Programmable ...draelshafee.net/Spring2019/cse303-logic-design-ii---lecture-03---multiplexers...•Microprocessors, FPGA, Application‐specific](https://reader031.vdocuments.site/reader031/viewer/2022013009/5e70579146036750ec048df8/html5/thumbnails/7.jpg)
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic Design II13
Three‐State Buffers
• A gate output can only be connected to a limited number of other device inputs without degrading the performance of a digital system.
• A buffer may be used to increase the driving capability of a gate output.
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II14
![Page 8: Lecture (03) Multiplexers, Decoders, and Programmable ...draelshafee.net/Spring2019/cse303-logic-design-ii---lecture-03---multiplexers...•Microprocessors, FPGA, Application‐specific](https://reader031.vdocuments.site/reader031/viewer/2022013009/5e70579146036750ec048df8/html5/thumbnails/8.jpg)
• A logic circuit will not operate correctly if the outputs of two or more gates or other logic devices are directly connected to each other.
• Use of three‐state logic permits the outputs of two or more gates or other logic devices to be connected together.
• Three‐state buffer (Tri‐state buffer)
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II15
Enable input B=1, output C=A, when B=0, C acts like an open circuit, C is effectively disconnected from the buffer output so that no current can flow.
This is referred to a Hi‐Z (high‐impedance) state of the output
because the circuit offers a very high resistance or impedance to the flow of current.
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II16
![Page 9: Lecture (03) Multiplexers, Decoders, and Programmable ...draelshafee.net/Spring2019/cse303-logic-design-ii---lecture-03---multiplexers...•Microprocessors, FPGA, Application‐specific](https://reader031.vdocuments.site/reader031/viewer/2022013009/5e70579146036750ec048df8/html5/thumbnails/9.jpg)
• Four kinds of Three‐State Buffers
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II17
• Data Selection Using Three‐State Buffers
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II18
D=B’A+BC
![Page 10: Lecture (03) Multiplexers, Decoders, and Programmable ...draelshafee.net/Spring2019/cse303-logic-design-ii---lecture-03---multiplexers...•Microprocessors, FPGA, Application‐specific](https://reader031.vdocuments.site/reader031/viewer/2022013009/5e70579146036750ec048df8/html5/thumbnails/10.jpg)
Decoders and Encoders
• Decoder
• Generates all of minterms
• Exactly one of the outputs lines will be 1 for each combination of the values of the input variables.
Dr. Ahmed ElShafee, NileU : Fall 2017, Microprocessor System Design19
• 3‐to‐8 Decoder
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II20
![Page 11: Lecture (03) Multiplexers, Decoders, and Programmable ...draelshafee.net/Spring2019/cse303-logic-design-ii---lecture-03---multiplexers...•Microprocessors, FPGA, Application‐specific](https://reader031.vdocuments.site/reader031/viewer/2022013009/5e70579146036750ec048df8/html5/thumbnails/11.jpg)
• 4‐to‐10 Line Decoder with Inverted Output
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II21
• n‐to‐2n line decoder:
• Generate all 2n minterms (or maxterms) of the n input variables Outputs
• Noninverted
– yi=mi , i=0,1,2,…,2n‐1
• Inverted
– yi=mi’=Mi , i=0,1,2,…,2n‐1
• Use decoder and gates to realize a function
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II22
![Page 12: Lecture (03) Multiplexers, Decoders, and Programmable ...draelshafee.net/Spring2019/cse303-logic-design-ii---lecture-03---multiplexers...•Microprocessors, FPGA, Application‐specific](https://reader031.vdocuments.site/reader031/viewer/2022013009/5e70579146036750ec048df8/html5/thumbnails/12.jpg)
Example
•
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II23
•
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II24
![Page 13: Lecture (03) Multiplexers, Decoders, and Programmable ...draelshafee.net/Spring2019/cse303-logic-design-ii---lecture-03---multiplexers...•Microprocessors, FPGA, Application‐specific](https://reader031.vdocuments.site/reader031/viewer/2022013009/5e70579146036750ec048df8/html5/thumbnails/13.jpg)
• Encoder
– The inverse function of a decoder
• 8‐to‐3 Priority Encoder
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic design II25
Thanks,..
See you next week (ISA),…
Dr. Ahmed ElShafee, ACU : Spring 2019, CSE303 Logic Design II
26