lect1 introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/introduction.pdf ·...

29
Silicon Photonics (2012/2) Introduction W.-Y. Choi Why Si Photonics? Secret of success? Special Topics in Optoelectronics: Realization of (hopefully) all photonic functions on Si platform Si Photonics ENIAC (1946) A4(2010) Performance (Clock Speed) 10KHz 1 GHz Power 170 KWatts 20 Watts Weight 28 tons Negligible Size 0.9 m (w) x 2.6 m (h) x 26 m (l) ~ 63 m 2 53.3 mm 2 Technology 17468 vacuum tubes 200 million 45nm CMOS TR Cost $ 487,000 $ 637

Upload: others

Post on 14-Aug-2020

6 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

● Why Si Photonics?

Secret of success?

● Special Topics in Optoelectronics: Realization of (hopefully) all photonic functions on Si platform

Si Photonics

ENIAC (1946) A4(2010)

Performance(Clock Speed) 10KHz 1 GHz

Power 170 KWatts 20 Watts

Weight 28 tons Negligible

Size0.9 m (w) x 2.6 m

(h) x 26 m (l)~ 약 63 m2

53.3 mm2

Technology 17468 vacuum tubes

200 million 45nm CMOS TR

Cost $ 487,000 $ 637

Page 2: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

● Why Si Photonics?

- Scaling and Integration

- Can this continue?

More Moore: Continuation of CMOS scaling

More than Moore: New materials, New technology (Photonics )

Moore’s Law

Page 3: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

Del

ay In

crea

sing

Process Technology Scale Down

Transistor delay(gate delay)

Interconnect bottleneck !

(ITRS Roadmap 2009)Channel length

: 250nm

Interconnect delay(RC time constant)

● Why Si Photonics ?

-Interconnect Bottleneck: On-Chip Interconnect

Page 4: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

● Why Si Photonics ?

- Chips are getting larger but clocks are getting faster- Difficult to cover the entire chip within one clock cycle- Interconnection within chip becomes very important for performance

-Interconnect Bottleneck: On-Chip Interconnect

“The development of CMOS-compatible optical components is of paramount importance” (ITRS Road 2009 – Interconnect, p.56)

Page 5: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

● Why photonics for interconect?

-Interconnect Bottleneck: On-Chip Interconnect

Plot of loss for cu-based on-chip interconnect

Page 6: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

- Chip-to-Chip Interconnect

• T – number of pins

• t – constant

• g – number of logic gates

• p – rent exponent

T = t x gp

Pin number limited by chip periphery ! Performance limited by I/O

System type Rent exponent (p)

Static memory 0.12Microprocessor 0.45

Gate array 0.50High-speed computer 0.63

Rent’s Rule Ref. P. Christie, T. VLSI, Dec. 2000.

Page 7: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

Chip-to-Chip Interconnect Serialization

Serial Interconnect: Single but faster connection

Data transferred concurrently !!

Data received concurrently !!

Page 8: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

- More data throughput Higher and higher data rate - Can this trend be maintained? Can photonics help?

Page 9: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

- Optical communication: transmitting lots of serialized data for long distance!- Strong driving force for evolution from left to right- But barriers on the right: Cost- Can Si help?

Page 10: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

- Optical interconnects provide higher data rate with less footprint than electrical interconnects!

IBM cloud computing data center (1,994 of servers)

Page 11: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

Active Optical Cables

- Full duplex 12-channel 850-nm parallel MMF (up to 50 m)- Transmission rate up to 10.3 Gb/s per channel- CXP-based small form-factor hot pluggable interface- 12-channel 850-nm VCSEL/PIN detector array- Power consumption: ~ 3 W (max) Basically an optical communication link

Page 12: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

- Full duplex 4-channel 1490-nm SMF (up to 4,000m)- Transmission rate up to 10.3 Gb/s per channel- High-density Quad Small Form-Factor Pluggable (QSFP) connector

Page 13: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi13

Photonic Integrated Circuits (InP)

- 500 Gb/s PM-QPSK Transmitter- 10 tunable DFBs, 40 MZMs- > 400 functions total

But compared to Si technology … Photonics on Si?

Page 14: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

- 0.13-μm SOI CMOS Technology on Si wafer(Luxtera / Freescale Semiconcutor)

- On-going research activities in realizing optimal individual devicesand integrated circuits

- 1.5m lasers are not available

Page 15: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

- Monolithic integration of optical components and electronics: Modulators, waveguides, PDs, Couplers

Page 16: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

Ref. A. Huang, ISSCC, Feb. 2006

- Realization with 0.13-μm SOI CMOS Technology on Si wafer (Foundry from Freescale Semiconcutor)

Photonics can be compatible with CMOS!

Page 17: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

- First commercialization of silicon photonics! (~ 50 $)- Luxtera sold AOC business to Molex, a fiber-optic connector specialist

Luxtera plant to focus on chip design: Fabless semiconductor company!

Page 18: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

- Paradigm shift in photonics technology!

Page 19: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

● Goals: - Understand the current status of Si photonic device technology Presentation on selected papers by students

- Review of basic optoelectronics

● Special Topics in Optoelectronics (Si Photonics)

● Topics to be covered- Introduction (L) - Si processing technology (L)- Si Waveguide (L, SP, Q)- Si Modulator (L, SP, Q)- Si Laser (L, SP, Q)- Si PD (L, SP, Q)- Optical Interconnect (L, SP)

Details of class schedule and paper list for SP will be announced once the class registration is finalized

Page 20: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

● Prerequisite:Basic knowledge in E&M waves/optics, semiconductor technology,and optoelectronic devices Evaluation Quiz on 9/5 (Passing grade required)

● Required Textbook: None- Lecture materials (Review of basics)- Selected reference papers (Understanding of current research)

● Grades- Quizzes: 4x12.5 = 50%- Student Presentation: 40%- Class Participation: 10%

Page 21: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

● Prof. Woo-Young Choi Email: [email protected], B625

● Class Hours Mon 2:00-4:00 pm, Wed 1:00-2:00 pm

Mon 2:30-4:00 pm, Wed 12:30 – 2:00 pm

● Office Hours - Right after classes- By appointment

Page 22: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

● Lecture Schedule

- Lect. 1: Introduction - Lect. 2: Review of Si technology- Lect. 3-4: Review of waveguides - Lect. 5-6: SP1,2,3,4 (Si waveguides)- Lect. 7: Quiz 1- Lect. 8-9: Review of modulators - Lect. 10-11: SP 5,6,7,8 (Si modulators)- Lect. 12: Quiz 2- Lect. 13-14: Review of lasers- Lect. 15-16: SP 9,10,11,12 (Si lasers)- Lect. 17: Quiz 3- Lect. 18: Review of photodetectors- Lect. 19-20: SP 13,14,15,16 (Si PDs)- Lect. 21: Quiz 4- Lect. 22: Review of optical interconnect- Lect. 23: SP 17,18 (Si EPIC)- Lect. 24-26 : Additional materials/papers if time is allowed

Page 23: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

1

2 3

Lect. 1

4 5

Lect. 2

6 7 8

9 10

Lect. 3

11 12

Lect. 4

13 14

16 18 19Lect. 6SP3, SP4

20 21 22

23

30

27 29

일 월 화 수 목 금 토

2826

Lect. 8

2524Lect. 7Quiz 1

17Lect. 5 SP1,SP2

15

추석

September

Page 24: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

October (tentative)

2 3 4 5 6

7 9 10

Lect. 10

11 12

14 15

Lect. 11

16 17

Lect. 12

18 19 20

21 22 23 24 25 26 27

28 29

Lect. 13

30 31

Lect. 14

1

일 월 화 수 목 금 토

13 8

Lect. 9

추석 개천절

Mid-Term Exam Period

Page 25: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

November (tentative)

1 2 3

4 5

Lect. 15

6 7

Lect. 16

8 9 10

11 12

Lect. 17

13 14

Lect. 18

15 16 17

18 19

Lect. 19

20 21

Lect. 20

22 23 24

25 26

Lect. 21

27 29 30

일 월 화 수 목 금 토

28

Lect. 22

Page 26: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

December (tentative)

1

2 3

Lect. 23

4 5

Lect. 24

7 8

9 10

Lect. 25

11 12

Lect. 26

13 14 15

16 17 18 19 20 21 22

23

30

24

31

25 26 27

일 월 화 수 목 금 토

28 29

6

Final Exam Period

Page 27: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

SP (Student Presentation) Schedule

- SP1: Lect. 5 (Si Technology), 홍주리- SP2: Lect. 5 (Si waveguides), 유병민- SP3: Lect. 6 (Si waveguides), 이정민- SP4: Lect. 6 (Si waveguides), 김민형- SP5: Lect. 10 (Si modulator), 정현용- SP6: Lect. 10 (Si modulator), 권대현- SP7: Lect, 11 (Si modulator), 류윤하- SP8: Lect. 11 (Si modulator), 배규영- SP9: Lect. 15 (Si laser), 원성우- SP10: Lect. 15 (Si laser), 정선영- SP11: Lect. 16 (Si laser), 류주형- SP12: Lect. 16 (Si laser), 정은미- SP13: Lect. 19 (Si PD), 이슬아- SP14: Lect. 19 (Si PD), 양승민- SP15: Lect. 20 (Si PD), 김여명- SP16: Lect. 20 (Si PD), 한희탁- SP17: Lect. 23 (Si EPIC), 최민정- SP18: Lect. 23 (Si EPIC),

Page 28: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

SP Paper List

- SP1 (Lect. 5) “Microelectronics for the Real World: ‘Moore’ versus ‘More than Moore’,Custom Integrated Circuits Conference, p. 395, 2008.

- SP2 (Lect. 5)“Low loss shallow-ridge silicon waveguides”, Optics Express, Vol. 18, No. 14, p. 14474, 2010

- SP3: (Lect. 6)“Optical directional coupler based on Si-wire waveguides”, Photonics Technology Letters, Vol. 17, No. 3, p. 585, 2005

- SP4 (Lect. 6)“An out-of-plane grating coupler for efficient butt-coupling between compact planar waveguides and single-mode fibers”, Journal of Quantum Electronics, Vol. 38, No. 7, p. 949, 2002

Page 29: Lect1 Introduction [호환 모드]tera.yonsei.ac.kr/class/2012_2_2/lecture/Introduction.pdf · Interconnect bottleneck ! (ITRS Roadmap 2009) Channel length: 250nm Interconnect delay

Silicon Photonics (2012/2)

Introduction

W.-Y. Choi

Guidelines for Student Presentation (SP)

- Presentation will be done in English

- SP contributes 40% of final grade

- Criteria for SP evaluation: Understanding, Presentation Skills, Dedication

- You will receive A,B,C for each of the above

- Your score = No. of A’s x 10 + No. of B’s x 8 + No. of C’s x 6) + 10

- Email your presentation materials to me ([email protected]) the day before your presentation. It will be available at tera.yonsei.ac.kr

-If you have difficulty understanding your paper, come and talk to me !